Doc. Thesis Dissertation: Efficient Modelling and Synthesis of Data Intensive Reconfigurable Systems
Date: June 17, 2005 (Friday) at 13:15
Per Andersson presents his doctoral thesis "Efficient Modelling and Synthesis of Data Intensive Reconfigurable Systems"
Faculty opponent: Prof. Christophe Wolinski, University of Rennes
Abstract:
Digital systems are integrated in our environment and have become a natural part of our every day life. As we rely more on these systems our expectations on them increase. We expect them to perform new tasks, communicate and cooperate. The complexity of these systems is increasing. The increasing complexity and the requirement for flexibility, which allows the system to adapt and evolve over time, make them difficult to design and realise using existing techniques and tools. This thesis addresses different problems in the design process of flexible digital systems.
We present our computational model Image Processing-Data Flow Graph (IP-DFG), a computational model tailored for modelling and implementation of image processing algorithms. IP-DFG is based on Data Flow Graphs (DFGs), which have been extended with hierarchy and explicit support for loops. This allows for a natural representation of image processing tasks.
The computational model IP-DFG has been integrated into our run-time system IPAPI. IPAPI manages the execution of all image processing related tasks in our Unmanned Aerial Vehicle (UAV) in the WITAS project. Combining a Java implementation of IPAPI and a library of highly optimised implementations of a few key IP-DFG nodes give high flexibility and sufficient performance. The flexibility greatly simplified the process of migrating the functionality from a simulated system on desktop computers to the on-board system of the UAV.
Hardware acceleration has successfully been used to increase the performance in many applications. We discuss different trade-offs during the design process of hardware accelerated systems and present our hardware software interface. We also suggest a design flow for rapid prototyping for System on Programmable Chip (SoPC).
One part of the design flow is automatic hardware compilation from Java. Our hardware compiler takes a new approach to hardware compilation. The source code is partitioned based on its behaviour and characteristics. Each partition is treated separately, allowing domain specific optimisations and code generators to be used.
Our work with hardware compilation has been focused on memory accesses. We use data dependence analysis to detect data reuse. Data to be reused are stored in local memories close to the data path. This drastically reduces the number of accesses to the data being processed, allowing large data structures to be stored in cost efficient but slow external memory while still running the data path at full speed.
Room: E:1406
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