/*****************************************************************************
* Filename:          C:\temp\PSSpaceInvaders/drivers/gpucore_v2_00_a/src/gpucore.h
* Version:           2.00.a
* Description:       gpucore Driver Header File
* Date:              Wed Sep 16 15:09:19 2015 (by Create and Import Peripheral Wizard)
*****************************************************************************/

#ifndef GPUCORE_H
#define GPUCORE_H

/***************************** Include Files *******************************/

#include "xbasic_types.h"
#include "xstatus.h"
#include "xil_io.h"

/************************** Constant Definitions ***************************/


/**
 * User Logic Slave Space Offsets
 * -- SLV_REG0 : user logic slave module register 0
 * -- SLV_REG1 : user logic slave module register 1
 * -- SLV_REG2 : user logic slave module register 2
 * -- SLV_REG3 : user logic slave module register 3
 * -- SLV_REG4 : user logic slave module register 4
 * -- SLV_REG5 : user logic slave module register 5
 * -- SLV_REG6 : user logic slave module register 6
 * -- SLV_REG7 : user logic slave module register 7
 * -- SLV_REG8 : user logic slave module register 8
 * -- SLV_REG9 : user logic slave module register 9
 */
#define GPUCORE_USER_SLV_SPACE_OFFSET (0x00000000)
#define GPUCORE_SLV_REG0_OFFSET (GPUCORE_USER_SLV_SPACE_OFFSET + 0x00000000)
#define GPUCORE_SLV_REG1_OFFSET (GPUCORE_USER_SLV_SPACE_OFFSET + 0x00000004)
#define GPUCORE_SLV_REG2_OFFSET (GPUCORE_USER_SLV_SPACE_OFFSET + 0x00000008)
#define GPUCORE_SLV_REG3_OFFSET (GPUCORE_USER_SLV_SPACE_OFFSET + 0x0000000C)
#define GPUCORE_SLV_REG4_OFFSET (GPUCORE_USER_SLV_SPACE_OFFSET + 0x00000010)
#define GPUCORE_SLV_REG5_OFFSET (GPUCORE_USER_SLV_SPACE_OFFSET + 0x00000014)
#define GPUCORE_SLV_REG6_OFFSET (GPUCORE_USER_SLV_SPACE_OFFSET + 0x00000018)
#define GPUCORE_SLV_REG7_OFFSET (GPUCORE_USER_SLV_SPACE_OFFSET + 0x0000001C)
#define GPUCORE_SLV_REG8_OFFSET (GPUCORE_USER_SLV_SPACE_OFFSET + 0x00000020)
#define GPUCORE_SLV_REG9_OFFSET (GPUCORE_USER_SLV_SPACE_OFFSET + 0x00000024)
#define GPUCORE_SLV_REG10_OFFSET (GPUCORE_USER_SLV_SPACE_OFFSET + 0x00000028)

/**************************** Type Definitions *****************************/


/***************** Macros (Inline Functions) Definitions *******************/

/**
 *
 * Write a value to a GPUCORE register. A 32 bit write is performed.
 * If the component is implemented in a smaller width, only the least
 * significant data is written.
 *
 * @param   BaseAddress is the base address of the GPUCORE device.
 * @param   RegOffset is the register offset from the base to write to.
 * @param   Data is the data written to the register.
 *
 * @return  None.
 *
 * @note
 * C-style signature:
 * 	void GPUCORE_mWriteReg(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Data)
 *
 */
#define GPUCORE_mWriteReg(BaseAddress, RegOffset, Data) \
 	Xil_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data))

/**
 *
 * Read a value from a GPUCORE register. A 32 bit read is performed.
 * If the component is implemented in a smaller width, only the least
 * significant data is read from the register. The most significant data
 * will be read as 0.
 *
 * @param   BaseAddress is the base address of the GPUCORE device.
 * @param   RegOffset is the register offset from the base to write to.
 *
 * @return  Data is the data from the register.
 *
 * @note
 * C-style signature:
 * 	Xuint32 GPUCORE_mReadReg(Xuint32 BaseAddress, unsigned RegOffset)
 *
 */
#define GPUCORE_mReadReg(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (RegOffset))


/**
 *
 * Write/Read 32 bit value to/from GPUCORE user logic slave registers.
 *
 * @param   BaseAddress is the base address of the GPUCORE device.
 * @param   RegOffset is the offset from the slave register to write to or read from.
 * @param   Value is the data written to the register.
 *
 * @return  Data is the data from the user logic slave register.
 *
 * @note
 * C-style signature:
 * 	void GPUCORE_mWriteSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Value)
 * 	Xuint32 GPUCORE_mReadSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset)
 *
 */
#define GPUCORE_mWriteSlaveReg0(BaseAddress, RegOffset, Value) \
 	Xil_Out32((BaseAddress) + (GPUCORE_SLV_REG0_OFFSET) + (RegOffset), (Xuint32)(Value))
#define GPUCORE_mWriteSlaveReg1(BaseAddress, RegOffset, Value) \
 	Xil_Out32((BaseAddress) + (GPUCORE_SLV_REG1_OFFSET) + (RegOffset), (Xuint32)(Value))
#define GPUCORE_mWriteSlaveReg2(BaseAddress, RegOffset, Value) \
 	Xil_Out32((BaseAddress) + (GPUCORE_SLV_REG2_OFFSET) + (RegOffset), (Xuint32)(Value))
#define GPUCORE_mWriteSlaveReg3(BaseAddress, RegOffset, Value) \
 	Xil_Out32((BaseAddress) + (GPUCORE_SLV_REG3_OFFSET) + (RegOffset), (Xuint32)(Value))
#define GPUCORE_mWriteSlaveReg4(BaseAddress, RegOffset, Value) \
 	Xil_Out32((BaseAddress) + (GPUCORE_SLV_REG4_OFFSET) + (RegOffset), (Xuint32)(Value))
#define GPUCORE_mWriteSlaveReg5(BaseAddress, RegOffset, Value) \
 	Xil_Out32((BaseAddress) + (GPUCORE_SLV_REG5_OFFSET) + (RegOffset), (Xuint32)(Value))
#define GPUCORE_mWriteSlaveReg6(BaseAddress, RegOffset, Value) \
 	Xil_Out32((BaseAddress) + (GPUCORE_SLV_REG6_OFFSET) + (RegOffset), (Xuint32)(Value))
#define GPUCORE_mWriteSlaveReg7(BaseAddress, RegOffset, Value) \
 	Xil_Out32((BaseAddress) + (GPUCORE_SLV_REG7_OFFSET) + (RegOffset), (Xuint32)(Value))
#define GPUCORE_mWriteSlaveReg8(BaseAddress, RegOffset, Value) \
 	Xil_Out32((BaseAddress) + (GPUCORE_SLV_REG8_OFFSET) + (RegOffset), (Xuint32)(Value))
#define GPUCORE_mWriteSlaveReg9(BaseAddress, RegOffset, Value) \
 	Xil_Out32((BaseAddress) + (GPUCORE_SLV_REG9_OFFSET) + (RegOffset), (Xuint32)(Value))
#define GPUCORE_mWriteSlaveReg10(BaseAddress, RegOffset, Value) \
 	Xil_Out32((BaseAddress) + (GPUCORE_SLV_REG10_OFFSET) + (RegOffset), (Xuint32)(Value))


#define GPUCORE_mReadSlaveReg0(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (GPUCORE_SLV_REG0_OFFSET) + (RegOffset))
#define GPUCORE_mReadSlaveReg1(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (GPUCORE_SLV_REG1_OFFSET) + (RegOffset))
#define GPUCORE_mReadSlaveReg2(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (GPUCORE_SLV_REG2_OFFSET) + (RegOffset))
#define GPUCORE_mReadSlaveReg3(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (GPUCORE_SLV_REG3_OFFSET) + (RegOffset))
#define GPUCORE_mReadSlaveReg4(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (GPUCORE_SLV_REG4_OFFSET) + (RegOffset))
#define GPUCORE_mReadSlaveReg5(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (GPUCORE_SLV_REG5_OFFSET) + (RegOffset))
#define GPUCORE_mReadSlaveReg6(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (GPUCORE_SLV_REG6_OFFSET) + (RegOffset))
#define GPUCORE_mReadSlaveReg7(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (GPUCORE_SLV_REG7_OFFSET) + (RegOffset))
#define GPUCORE_mReadSlaveReg8(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (GPUCORE_SLV_REG8_OFFSET) + (RegOffset))
#define GPUCORE_mReadSlaveReg9(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (GPUCORE_SLV_REG9_OFFSET) + (RegOffset))
#define GPUCORE_mReadSlaveReg10(BaseAddress, RegOffset) \
 	Xil_In32((BaseAddress) + (GPUCORE_SLV_REG10_OFFSET) + (RegOffset))

/************************** Function Prototypes ****************************/


/**
 *
 * Run a self-test on the driver/device. Note this may be a destructive test if
 * resets of the device are performed.
 *
 * If the hardware system is not built correctly, this function may never
 * return to the caller.
 *
 * @param   baseaddr_p is the base address of the GPUCORE instance to be worked on.
 *
 * @return
 *
 *    - XST_SUCCESS   if all self-test code passed
 *    - XST_FAILURE   if any self-test code failed
 *
 * @note    Caching must be turned off for this function to work.
 * @note    Self test may fail if data memory and device are not on the same bus.
 *
 */
XStatus GPUCORE_SelfTest(void * baseaddr_p);
/**
*  Defines the number of registers available for read and write*/
#define TEST_AXI_LITE_USER_NUM_REG 10


#endif /** GPUCORE_H */
