knob Project Status (10/08/2015 - 13:20:17)
Project File: knob.xise Parser Errors: No Errors
Module Name: knob Implementation State: Placed and Routed
Target Device: xc6slx16-3csg324
  • Errors:
No Errors
Product Version:ISE 14.2
  • Warnings:
55 Warnings (55 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 37 18,224 1%  
    Number used as Flip Flops 37      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 49 9,112 1%  
    Number used as logic 49 9,112 1%  
        Number using O6 output only 37      
        Number using O5 output only 0      
        Number using O5 and O6 12      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
Number of occupied Slices 20 2,278 1%  
Nummber of MUXCYs used 0 4,556 0%  
Number of LUT Flip Flop pairs used 52      
    Number with an unused Flip Flop 18 52 34%  
    Number with an unused LUT 3 52 5%  
    Number of fully used LUT-FF pairs 31 52 59%  
    Number of unique control sets 7      
    Number of slice register sites lost
        to control set restrictions
27 18,224 1%  
Number of bonded IOBs 53 232 22%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 0 248 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.77      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentto 8. okt 13:19:47 2015055 Warnings (55 new)5 Infos (5 new)
Translation ReportCurrentto 8. okt 13:19:53 2015000
Map ReportCurrentto 8. okt 13:20:05 2015008 Infos (8 new)
Place and Route ReportCurrentto 8. okt 13:20:12 2015003 Infos (3 new)
Power Report     
Post-PAR Static Timing ReportCurrentto 8. okt 13:20:16 2015004 Infos (4 new)
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 10/08/2015 - 13:20:17