breakout_vga_renderer Project Status
Project File: breakout_vga_renderer.xise Parser Errors: No Errors
Module Name: breakout_vga_renderer Implementation State: Synthesized
Target Device: xc6slx16-3csg324
  • Errors:
No Errors
Product Version:ISE 14.2
  • Warnings:
83 Warnings (83 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 1138 18224 6%
Number of Slice LUTs 1590 9112 17%
Number of fully used LUT-FF pairs 567 2161 26%
Number of bonded IOBs 90 232 38%
Number of BUFG/BUFGCTRLs 1 16 6%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentmå 5. okt 12:55:48 2015083 Warnings (83 new)12 Infos (12 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentmå 5. okt 15:20:34 2015

Date Generated: 10/06/2015 - 13:07:43