breakout_vga_renderer Project Status | |||
Project File: | breakout_vga_renderer.xise | Parser Errors: | No Errors |
Module Name: | breakout_vga_renderer | Implementation State: | Synthesized |
Target Device: | xc6slx16-3csg324 |
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No Errors |
Product Version: | ISE 14.2 |
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83 Warnings (83 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 1138 | 18224 | 6% | |
Number of Slice LUTs | 1590 | 9112 | 17% | |
Number of fully used LUT-FF pairs | 567 | 2161 | 26% | |
Number of bonded IOBs | 90 | 232 | 38% | |
Number of BUFG/BUFGCTRLs | 1 | 16 | 6% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | må 5. okt 12:55:48 2015 | 0 | 83 Warnings (83 new) | 12 Infos (12 new) | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | må 5. okt 15:20:34 2015 |