Release 14.6 Map P.68d (nt64)
Xilinx Map Application Log File for Design 'fsl_to_axi'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx16-csg324-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o fsl_to_axi_map.ncd fsl_to_axi.ngd fsl_to_axi.pcf 
Target Device  : xc6slx16
Target Package : csg324
Target Speed   : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Tue Oct 08 12:06:24 2013

Mapping design into LUTs...
Running directed packing...
WARNING:Pack:2238 - Function generator symbol
   "FFT/blk00000001/blk00000101/blk00000102/blk00000e0e" (Output Signal =
   FFT/blk00000001/blk00000101/blk00000102/sig00001395) has an invalid use of
   the LUTNM constraint. There are no other function generator symbols with a
   matching LUTNM constraint value
   (LUTNM=FFT/blk00000001/blk00000101/blk00000102/hlutnm00000071). The
   constraint will be ignored.
WARNING:Pack:2238 - Function generator symbol
   "FFT/blk00000001/blk00000101/blk00000102/blk00000e50" (Output Signal =
   FFT/blk00000001/blk00000101/blk00000102/sig000013b3) has an invalid use of
   the LUTNM constraint. There are no other function generator symbols with a
   matching LUTNM constraint value
   (LUTNM=FFT/blk00000001/blk00000101/blk00000102/hlutnm00000080). The
   constraint will be ignored.
WARNING:Pack:2238 - Function generator symbol
   "FFT/blk00000001/blk00000101/blk00000102/blk00000e10" (Output Signal =
   FFT/blk00000001/blk00000101/blk00000102/sig00001396) has an invalid use of
   the LUTNM constraint. There are no other function generator symbols with a
   matching LUTNM constraint value
   (LUTNM=FFT/blk00000001/blk00000101/blk00000102/hlutnm00000072). The
   constraint will be ignored.
WARNING:Pack:2238 - Function generator symbol
   "FFT/blk00000001/blk00000101/blk00000102/blk00000e15" (Output Signal =
   FFT/blk00000001/blk00000101/blk00000102/sig00001397) has an invalid use of
   the LUTNM constraint. There are no other function generator symbols with a
   matching LUTNM constraint value
   (LUTNM=FFT/blk00000001/blk00000101/blk00000102/hlutnm00000073). The
   constraint will be ignored.
WARNING:Pack:2238 - Function generator symbol
   "FFT/blk00000001/blk00000101/blk00000102/blk00000e17" (Output Signal =
   FFT/blk00000001/blk00000101/blk00000102/sig00001398) has an invalid use of
   the LUTNM constraint. There are no other function generator symbols with a
   matching LUTNM constraint value
   (LUTNM=FFT/blk00000001/blk00000101/blk00000102/hlutnm00000074). The
   constraint will be ignored.
WARNING:Pack:2238 - Function generator symbol
   "FFT/blk00000001/blk00000101/blk00000102/blk00000e5f" (Output Signal =
   FFT/blk00000001/blk00000101/blk00000102/sig000013b9) has an invalid use of
   the LUTNM constraint. There are no other function generator symbols with a
   matching LUTNM constraint value
   (LUTNM=FFT/blk00000001/blk00000101/blk00000102/hlutnm00000083). The
   constraint will be ignored.
WARNING:Pack:2238 - Function generator symbol
   "FFT/blk00000001/blk00000101/blk00000102/blk00000e61" (Output Signal =
   FFT/blk00000001/blk00000101/blk00000102/sig000013ba) has an invalid use of
   the LUTNM constraint. There are no other function generator symbols with a
   matching LUTNM constraint value
   (LUTNM=FFT/blk00000001/blk00000101/blk00000102/hlutnm00000084). The
   constraint will be ignored.
WARNING:Pack:2238 - Function generator symbol
   "FFT/blk00000001/blk00000101/blk00000102/blk00000e70" (Output Signal =
   FFT/blk00000001/blk00000101/blk00000102/sig000013c2) has an invalid use of
   the LUTNM constraint. There are no other function generator symbols with a
   matching LUTNM constraint value
   (LUTNM=FFT/blk00000001/blk00000101/blk00000102/hlutnm00000086). The
   constraint will be ignored.
WARNING:Pack:2238 - Function generator symbol
   "FFT/blk00000001/blk00000101/blk00000102/blk00000eaa" (Output Signal =
   FFT/blk00000001/blk00000101/blk00000102/sig000013f8) has an invalid use of
   the LUTNM constraint. There are no other function generator symbols with a
   matching LUTNM constraint value
   (LUTNM=FFT/blk00000001/blk00000101/blk00000102/hlutnm0000008b). The
   constraint will be ignored.
WARNING:Pack:2238 - Function generator symbol
   "FFT/blk00000001/blk00000101/blk00000102/blk00000e4e" (Output Signal =
   FFT/blk00000001/blk00000101/blk00000102/sig000013b2) has an invalid use of
   the LUTNM constraint. There are no other function generator symbols with a
   matching LUTNM constraint value
   (LUTNM=FFT/blk00000001/blk00000101/blk00000102/hlutnm0000007f). The
   constraint will be ignored.
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 7 secs 
Total CPU  time at the beginning of Placer: 7 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:9be7f9) REAL time: 8 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:9be7f9) REAL time: 8 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:9be7f9) REAL time: 8 secs 

Phase 4.2  Initial Placement for Architecture Specific Features
......
Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:32f1325) REAL time: 11 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:32f1325) REAL time: 11 secs 

Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:32f1325) REAL time: 11 secs 

Phase 7.3  Local Placement Optimization
......
Phase 7.3  Local Placement Optimization (Checksum:338e39a9) REAL time: 13 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:338e39a9) REAL time: 13 secs 

Phase 9.8  Global Placement
....................................................................
.................
Phase 9.8  Global Placement (Checksum:f10ca730) REAL time: 11 mins 44 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:f10ca730) REAL time: 11 mins 45 secs 

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:8f4070b) REAL time: 15 mins 34 secs 

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:8f4070b) REAL time: 15 mins 34 secs 

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:1d53d9b0) REAL time: 15 mins 42 secs 

Total REAL time to Placer completion: 15 mins 51 secs 
Total CPU  time to Placer completion: 15 mins 32 secs 
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
   default, may be incorrect and should not be used.  For more information,
   please reference Xilinx Answer Record 39999.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:   11
Slice Logic Utilization:
  Number of Slice Registers:                 1,864 out of  18,224   10%
    Number used as Flip Flops:               1,864
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                      1,372 out of   9,112   15%
    Number used as logic:                    1,080 out of   9,112   11%
      Number using O6 output only:             696
      Number using O5 output only:               4
      Number using O5 and O6:                  380
      Number used as ROM:                        0
    Number used as Memory:                     213 out of   2,176    9%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:           213
        Number using O6 output only:            20
        Number using O5 output only:             0
        Number using O5 and O6:                193
    Number used exclusively as route-thrus:     79
      Number with same-slice register load:     78
      Number with same-slice carry load:         1
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                   517 out of   2,278   22%
  Number of MUXCYs used:                       492 out of   4,556   10%
  Number of LUT Flip Flop pairs used:        1,623
    Number with an unused Flip Flop:           261 out of   1,623   16%
    Number with an unused LUT:                 251 out of   1,623   15%
    Number of fully used LUT-FF pairs:       1,111 out of   1,623   68%
    Number of unique control sets:              18
    Number of slice register sites lost
      to control set restrictions:              66 out of  18,224    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        54 out of     232   23%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      32    0%
  Number of RAMB8BWERs:                          7 out of      64   10%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
    Number used as BUFGs:                        1
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     248    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     248    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            9 out of      32   28%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                3.21

Peak Memory Usage:  418 MB
Total REAL time to MAP completion:  16 mins 1 secs 
Total CPU time to MAP completion:   15 mins 42 secs 

Mapping completed.
See MAP report file "fsl_to_axi_map.mrp" for details.
