
<EDKSYSTEM EDKVERSION="14.2" EDWVERSION="1.2" TIMESTAMP="Sun Oct 20 18:08:30 2013">

  <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx16" PACKAGE="csg324" PART="xc6slx16csg324-3" SOURCE="C:/Temp/SPgram4/Spectrogram_XPS/system.xmp" SPEEDGRADE="-3"/>

  <EXTERNALPORTS>
    <PORT DIR="O" MHS_INDEX="0" NAME="RS232_Uart_1_sout" SIGNAME="RS232_Uart_1_sout">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[uart_0]" INSTANCE="RS232_Uart_1" PORT="TX"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="1" NAME="RS232_Uart_1_sin" SIGNAME="RS232_Uart_1_sin">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[uart_0]" INSTANCE="RS232_Uart_1" PORT="RX"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="2" NAME="RESET" RSTPOLARITY="1" SIGIS="RST" SIGNAME="RESET">
      <CONNECTIONS>
        <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Ext_Reset_In"/>
        <CONNECTION INSTANCE="clock_generator_0" PORT="RST"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="3" MSB="0" NAME="Push_Buttons_4Bits_TRI_I" RIGHT="3" SIGNAME="Push_Buttons_4Bits_TRI_I">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="Push_Buttons_4Bits" PORT="GPIO_IO_I"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="4" MSB="7" NAME="LEDs_8Bits_TRI_O" RIGHT="0" SIGNAME="LEDs_8Bits_TRI_O">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="LEDs_8Bits" PORT="GPIO_IO_O"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" MHS_INDEX="5" NAME="GCLK" SIGIS="CLK" SIGNAME="GCLK">
      <CONNECTIONS>
        <CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="6" MSB="7" NAME="DIP_Switches_8Bits_TRI_I" RIGHT="0" SIGNAME="DIP_Switches_8Bits_TRI_I">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[gpio_0]" INSTANCE="DIP_Switches_8Bits" PORT="GPIO_IO_I"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="7" NAME="mem_to_vga_0_HS_pin" SIGNAME="mem_to_vga_0_HS">
      <CONNECTIONS>
        <CONNECTION INSTANCE="mem_to_vga_0" PORT="HS"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MHS_INDEX="8" MSB="0" NAME="mem_to_vga_0_rgb_pin" RIGHT="7" SIGNAME="mem_to_vga_0_rgb">
      <CONNECTIONS>
        <CONNECTION INSTANCE="mem_to_vga_0" PORT="rgb"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="9" NAME="mem_to_vga_0_VS_pin" SIGNAME="mem_to_vga_0_VS">
      <CONNECTIONS>
        <CONNECTION INSTANCE="mem_to_vga_0" PORT="VS"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="10" NAME="axi_iic_0_Gpo_pin" SIGNAME="axi_iic_0_Gpo">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="axi_iic_0" PORT="Gpo"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="11" NAME="axi_iic_0_Sda_pin" SIGNAME="axi_iic_0_Sda">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="axi_iic_0" PORT="Sda"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="12" NAME="axi_iic_0_Scl_pin" SIGNAME="axi_iic_0_Scl">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="axi_iic_0" PORT="Scl"/>
      </CONNECTIONS>
    </PORT>
  </EXTERNALPORTS>

  <MODULES>
    <MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="0" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
      <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="lx"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="spartan6"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="debug_module" PORT="Debug_SYS_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="proc_sys_reset_0_Dcm_locked">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="LOCKED"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0" PORT="MB_RESET"/>
            <CONNECTION INSTANCE="fsl_v20_0" PORT="SYS_Rst"/>
            <CONNECTION INSTANCE="fsl_v20_1" PORT="SYS_Rst"/>
            <CONNECTION INSTANCE="fsl_v20_2" PORT="SYS_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="INTERCONNECT_ARESETN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="RESET">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="RESET"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="18" NAME="BUS_STRUCT_RESET" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET" VECFORMULA="[0:C_NUM_BUS_RST-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="SYS_RST"/>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="SYS_RST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="proc_sys_reset_0_Peripheral_Reset" VECFORMULA="[0:C_NUM_PERP_RST-1]">
          <CONNECTIONS/>
        </PORT>
        <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
            <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
            <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
            <PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
            <PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
            <PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
      </IOINTERFACES>
    </MODULE>
    <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.b" INSTANCE="microblaze_0_ilmb" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="lmb_v10">
      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Bus_Struct_Reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_ilmb_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="LMB_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="INSTR_ADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_ilmb_M_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="IFETCH"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_ilmb_M_WriteStrobe">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_ilmb_M_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="I_AS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="Sl_DBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="Sl_Ready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="Sl_Wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="Sl_UE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="Sl_CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="LMB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="LMB_ReadStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="LMB_WriteStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="LMB_AddrStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="INSTR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="LMB_WriteDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_ilmb_LMB_Ready">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="IREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_ilmb_LMB_Wait">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="IWAIT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_ilmb_LMB_UE">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="IUE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_ilmb_LMB_CE">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[ILMB]" INSTANCE="microblaze_0" PORT="ICE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="LMB_BE"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
      </IOINTERFACES>
    </MODULE>
    <MODULE HWVERSION="3.10.a" INSTANCE="microblaze_0_i_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="2" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
      <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00007fff"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x00800000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" ENDIAN="BIG" LSB="31" MPD_INDEX="4" MSB="0" NAME="C_MASK1" TYPE="std_logic_vector" VALUE="0x00800000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" ENDIAN="BIG" LSB="31" MPD_INDEX="5" MSB="0" NAME="C_MASK2" TYPE="std_logic_vector" VALUE="0x00800000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" ENDIAN="BIG" LSB="31" MPD_INDEX="6" MSB="0" NAME="C_MASK3" TYPE="std_logic_vector" VALUE="0x00800000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="7" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="8" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_ECC" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="16" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="17" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="18" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="19" NAME="C_NUM_LMB" TYPE="integer" VALUE="1"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" MPD_INDEX="20" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" MPD_INDEX="21" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="22" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="23" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="24" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="25" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="26" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="27" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="28" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="29" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="30" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" MPD_INDEX="31" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" MPD_INDEX="32" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="33" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="34" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="35" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHz" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_ilmb_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="LMB_RST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="LMB_ABUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="LMB_WRITEDBUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_ilmb_LMB_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="LMB_ADDRSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_ilmb_LMB_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="LMB_READSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_ilmb_LMB_WriteStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="LMB_WRITESTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="LMB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="SL_DBUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_ilmb_Sl_Ready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="SL_READY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_ilmb_Sl_Wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="SL_WAIT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_ilmb_Sl_UE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="SL_UE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_ilmb_Sl_CE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="SL_CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="LMB1_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB1_WriteDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="15" NAME="LMB1_AddrStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="16" NAME="LMB1_ReadStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="LMB1_WriteStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="LMB1_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="Sl1_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="20" NAME="Sl1_Ready" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="21" NAME="Sl1_Wait" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="22" NAME="Sl1_UE" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="23" NAME="Sl1_CE" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="24" MSB="0" NAME="LMB2_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="LMB2_WriteDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="26" NAME="LMB2_AddrStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="27" NAME="LMB2_ReadStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="28" NAME="LMB2_WriteStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="3" MPD_INDEX="29" MSB="0" NAME="LMB2_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="30" MSB="0" NAME="Sl2_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="31" NAME="Sl2_Ready" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="32" NAME="Sl2_Wait" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="33" NAME="Sl2_UE" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="34" NAME="Sl2_CE" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="LMB3_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="36" MSB="0" NAME="LMB3_WriteDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="37" NAME="LMB3_AddrStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="38" NAME="LMB3_ReadStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="39" NAME="LMB3_WriteStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="LMB3_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="Sl3_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="Sl3_Ready" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="43" NAME="Sl3_Wait" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="44" NAME="Sl3_UE" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="45" NAME="Sl3_CE" SIGNAME="__NOC__"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="46" NAME="BRAM_Rst_A" SIGIS="RST" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_Rst_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="47" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_Clk_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="48" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_EN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="49" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_WEN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_Addr_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="51" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_Din_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="52" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTA]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_Dout_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="53" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="54" NAME="UE" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="55" NAME="CE" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="57" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="58" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="59" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="60" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="61" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="62" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="63" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="64" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="65" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="70" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="76" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="81" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="82" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="84" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="86" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="87" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="88" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="89" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="90" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="91" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="92" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="93" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="96" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="97" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="101" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="102" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="105" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="108" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="111" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="112" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="114" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_VALID="FALSE" MPD_INDEX="1" NAME="SLMB1" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="LMB1_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB1_WriteDBus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB1_AddrStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB1_ReadStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB1_WriteStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB1_BE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl1_DBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl1_Ready"/>
            <PORTMAP DIR="O" PHYSICAL="Sl1_Wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl1_UE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl1_CE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_VALID="FALSE" MPD_INDEX="2" NAME="SLMB2" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="LMB2_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB2_WriteDBus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB2_AddrStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB2_ReadStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB2_WriteStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB2_BE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl2_DBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl2_Ready"/>
            <PORTMAP DIR="O" PHYSICAL="Sl2_Wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl2_UE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl2_CE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_VALID="FALSE" MPD_INDEX="3" NAME="SLMB3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="LMB3_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB3_WriteDBus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB3_AddrStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB3_ReadStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB3_WriteStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB3_BE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl3_DBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl3_Ready"/>
            <PORTMAP DIR="O" PHYSICAL="Sl3_Wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl3_UE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl3_CE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="4" NAME="BRAM_PORT" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="5" NAME="SPLB_CTRL" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="6" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="32767" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00007fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="32768" SIZEABRV="32K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SLMB"/>
            <SLAVE BUSINTERFACE="SLMB1"/>
            <SLAVE BUSINTERFACE="SLMB2"/>
            <SLAVE BUSINTERFACE="SLMB3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB_CTRL"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.b" INSTANCE="microblaze_0_dlmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="SYS_RST" SIGIS="RST" SIGNAME="proc_sys_reset_0_BUS_STRUCT_RESET">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Bus_Struct_Reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="LMB_CLK" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="LMB_Rst"/>
            <CONNECTION BUSINTERFACE="[DLMB:ILMB]" INSTANCE="microblaze_0" PORT="RESET"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DATA_ADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="microblaze_0_dlmb_M_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="READ_STROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="microblaze_0_dlmb_M_WriteStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="WRITE_STROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="microblaze_0_dlmb_M_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="D_AS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DATA_WRITE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="BYTE_ENABLE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="Sl_DBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="Sl_Ready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="Sl_Wait"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="Sl_UE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="Sl_CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="LMB_ABus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="LMB_ReadStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="LMB_WriteStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="LMB_AddrStrobe"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DATA_READ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="LMB_WriteDBus"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="microblaze_0_dlmb_LMB_Ready">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="microblaze_0_dlmb_LMB_Wait">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DWAIT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="microblaze_0_dlmb_LMB_UE">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DUE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="microblaze_0_dlmb_LMB_CE">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DLMB]" INSTANCE="microblaze_0" PORT="DCE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="LMB_BE"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
      </IOINTERFACES>
    </MODULE>
    <MODULE HWVERSION="3.10.a" INSTANCE="microblaze_0_d_bram_ctrl" IPTYPE="PERIPHERAL" MHS_INDEX="4" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
      <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00007fff"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x00800000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" ENDIAN="BIG" LSB="31" MPD_INDEX="4" MSB="0" NAME="C_MASK1" TYPE="std_logic_vector" VALUE="0x00800000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" ENDIAN="BIG" LSB="31" MPD_INDEX="5" MSB="0" NAME="C_MASK2" TYPE="std_logic_vector" VALUE="0x00800000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" ENDIAN="BIG" LSB="31" MPD_INDEX="6" MSB="0" NAME="C_MASK3" TYPE="std_logic_vector" VALUE="0x00800000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="7" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="8" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_ECC" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="16" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="17" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="18" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="19" NAME="C_NUM_LMB" TYPE="integer" VALUE="1"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" MPD_INDEX="20" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" MPD_INDEX="21" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="22" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="23" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="24" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="25" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="26" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="27" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="28" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="29" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="30" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" MPD_INDEX="31" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" MPD_INDEX="32" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="33" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="34" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="35" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHz" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="microblaze_0_dlmb_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="LMB_RST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="LMB_ABUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="LMB_WRITEDBUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="microblaze_0_dlmb_LMB_AddrStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="LMB_ADDRSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="microblaze_0_dlmb_LMB_ReadStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="LMB_READSTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="microblaze_0_dlmb_LMB_WriteStrobe">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="LMB_WRITESTROBE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="microblaze_0_dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="LMB_BE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="microblaze_0_dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="SL_DBUS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="microblaze_0_dlmb_Sl_Ready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="SL_READY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="microblaze_0_dlmb_Sl_Wait">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="SL_WAIT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="microblaze_0_dlmb_Sl_UE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="SL_UE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB" DEF_SIGNAME="microblaze_0_dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="microblaze_0_dlmb_Sl_CE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="SL_CE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="LMB1_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB1_WriteDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="15" NAME="LMB1_AddrStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="16" NAME="LMB1_ReadStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="LMB1_WriteStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="LMB1_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="Sl1_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="20" NAME="Sl1_Ready" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="21" NAME="Sl1_Wait" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="22" NAME="Sl1_UE" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="23" NAME="Sl1_CE" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="24" MSB="0" NAME="LMB2_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="LMB2_WriteDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="26" NAME="LMB2_AddrStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="27" NAME="LMB2_ReadStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="28" NAME="LMB2_WriteStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="3" MPD_INDEX="29" MSB="0" NAME="LMB2_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="30" MSB="0" NAME="Sl2_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="31" NAME="Sl2_Ready" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="32" NAME="Sl2_Wait" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="33" NAME="Sl2_UE" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="34" NAME="Sl2_CE" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="LMB3_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="36" MSB="0" NAME="LMB3_WriteDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="37" NAME="LMB3_AddrStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="38" NAME="LMB3_ReadStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="39" NAME="LMB3_WriteStrobe" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="LMB3_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="Sl3_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="Sl3_Ready" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="43" NAME="Sl3_Wait" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="44" NAME="Sl3_UE" SIGNAME="__NOC__"/>
        <PORT BUS="SLMB3" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="45" NAME="Sl3_CE" SIGNAME="__NOC__"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="O" MPD_INDEX="46" NAME="BRAM_Rst_A" SIGIS="RST" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_Rst_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="O" MPD_INDEX="47" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_Clk_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="O" MPD_INDEX="48" NAME="BRAM_EN_A" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_EN_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="49" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_WEN_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_Addr_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="51" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_Din_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="52" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[PORTB]" INSTANCE="microblaze_0_bram_block" PORT="BRAM_Dout_B"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="53" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="54" NAME="UE" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="55" NAME="CE" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="57" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="58" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="59" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="60" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
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            <PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_VALID="FALSE" MPD_INDEX="1" NAME="SLMB1" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="LMB1_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB1_WriteDBus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB1_AddrStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB1_ReadStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB1_WriteStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB1_BE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl1_DBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl1_Ready"/>
            <PORTMAP DIR="O" PHYSICAL="Sl1_Wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl1_UE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl1_CE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_VALID="FALSE" MPD_INDEX="2" NAME="SLMB2" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="LMB2_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB2_WriteDBus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB2_AddrStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB2_ReadStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB2_WriteStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB2_BE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl2_DBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl2_Ready"/>
            <PORTMAP DIR="O" PHYSICAL="Sl2_Wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl2_UE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl2_CE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_VALID="FALSE" MPD_INDEX="3" NAME="SLMB3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="LMB3_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB3_WriteDBus"/>
            <PORTMAP DIR="I" PHYSICAL="LMB3_AddrStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB3_ReadStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB3_WriteStrobe"/>
            <PORTMAP DIR="I" PHYSICAL="LMB3_BE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl3_DBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl3_Ready"/>
            <PORTMAP DIR="O" PHYSICAL="Sl3_Wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl3_UE"/>
            <PORTMAP DIR="O" PHYSICAL="Sl3_CE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="4" NAME="BRAM_PORT" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="5" NAME="SPLB_CTRL" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="6" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="32767" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00007fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="32768" SIZEABRV="32K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SLMB"/>
            <SLAVE BUSINTERFACE="SLMB1"/>
            <SLAVE BUSINTERFACE="SLMB2"/>
            <SLAVE BUSINTERFACE="SLMB3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB_CTRL"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="microblaze_0_bram_block" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY" MODTYPE="bram_block">
      <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x8000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="BRAM_Rst_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="BRAM_Clk_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="BRAM_EN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="BRAM_WEN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="BRAM_Addr_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="BRAM_Din_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTA" DEF_SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="BRAM_Dout_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="BRAM_Rst_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Clk">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="BRAM_Clk_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_EN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="BRAM_EN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="BRAM_WEN_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="BRAM_Addr_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="BRAM_Din_A"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="PORTB" DEF_SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[BRAM_PORT]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="BRAM_Dout_A"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
            <PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
            <PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE HWVERSION="8.40.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="6" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
      <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_40_a/doc/microblaze.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_AVOID_PRIMITIVES" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="7" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_LOCKSTEP_SLAVE" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_ENDIANNESS" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="13" NAME="C_INTERCONNECT" TYPE="integer" VALUE="2"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="15" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="16" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="17" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="18" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="19" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="20" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="21" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="22" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="24" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="26" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="27" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="28" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="29" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="30" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="31" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
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        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="46" NAME="C_I_AXI" TYPE="integer" VALUE="0"/>
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        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="54" NAME="C_USE_FPU" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="55" NAME="C_USE_REORDER_INSTR" TYPE="integer" VALUE="1"/>
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        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="66" NAME="C_PVR" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" ENDIAN="BIG" LSB="7" MPD_INDEX="67" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00"/>
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        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="69" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="70" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="1"/>
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        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="74" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1"/>
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        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="146" NAME="C_USE_ICACHE" TYPE="integer" VALUE="0"/>
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        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="168" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
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        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="170" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="171" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="172" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="173" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/>
        <PARAMETER ADDRESS="NONE" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="174" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0X00000000"/>
        <PARAMETER ADDRESS="NONE" ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="175" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0X3FFFFFFF"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="176" NAME="C_USE_DCACHE" TYPE="integer" VALUE="0"/>
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        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="179" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="8192"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="180" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="181" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4"/>
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        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="186" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="187" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="188" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="189" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="190" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
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        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="192" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="193" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="194" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="195" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="196" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="197" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="198" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="199" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="200" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="201" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="202" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
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        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="93" NAME="DPLB_MRearbitrate" SIGNAME="__NOC__"/>
        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="94" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="DPLB_MTimeout" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="M_AXI_IP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="M_AXI_IP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="98" MSB="7" NAME="M_AXI_IP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="99" MSB="2" NAME="M_AXI_IP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="M_AXI_IP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="M_AXI_IP_AWLOCK" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="102" MSB="3" NAME="M_AXI_IP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="103" MSB="2" NAME="M_AXI_IP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="104" MSB="3" NAME="M_AXI_IP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="M_AXI_IP_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="106" NAME="M_AXI_IP_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="M_AXI_IP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="108" MSB="3" NAME="M_AXI_IP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_IP_DATA_WIDTH/8)-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="M_AXI_IP_WLAST" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="M_AXI_IP_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="111" NAME="M_AXI_IP_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="112" NAME="M_AXI_IP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="113" MSB="1" NAME="M_AXI_IP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="114" NAME="M_AXI_IP_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="115" NAME="M_AXI_IP_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="116" NAME="M_AXI_IP_ARID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="117" MSB="31" NAME="M_AXI_IP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="118" MSB="7" NAME="M_AXI_IP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="119" MSB="2" NAME="M_AXI_IP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="120" MSB="1" NAME="M_AXI_IP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="M_AXI_IP_ARLOCK" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="122" MSB="3" NAME="M_AXI_IP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="123" MSB="2" NAME="M_AXI_IP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="124" MSB="3" NAME="M_AXI_IP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="M_AXI_IP_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="126" NAME="M_AXI_IP_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="127" NAME="M_AXI_IP_RID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="128" MSB="31" NAME="M_AXI_IP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="M_AXI_IP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="130" NAME="M_AXI_IP_RLAST" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="131" NAME="M_AXI_IP_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="132" NAME="M_AXI_IP_RREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWID" DIR="O" MPD_INDEX="133" NAME="M_AXI_DP_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_AWID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="134" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[7:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_AWLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="136" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_AWSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="137" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_AWBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="O" MPD_INDEX="138" NAME="M_AXI_DP_AWLOCK" SIGNAME="axi4lite_0_S_AWLOCK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_AWLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="139" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_AWCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="140" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_AWPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="141" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_AWQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="O" MPD_INDEX="142" NAME="M_AXI_DP_AWVALID" SIGNAME="axi4lite_0_S_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="I" MPD_INDEX="143" NAME="M_AXI_DP_AWREADY" SIGNAME="axi4lite_0_S_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="144" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="145" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[((C_M_AXI_DP_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="O" MPD_INDEX="146" NAME="M_AXI_DP_WLAST" SIGNAME="axi4lite_0_S_WLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_WLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="O" MPD_INDEX="147" NAME="M_AXI_DP_WVALID" SIGNAME="axi4lite_0_S_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="I" MPD_INDEX="148" NAME="M_AXI_DP_WREADY" SIGNAME="axi4lite_0_S_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BID" DIR="I" MPD_INDEX="149" NAME="M_AXI_DP_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_BID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="150" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="I" MPD_INDEX="151" NAME="M_AXI_DP_BVALID" SIGNAME="axi4lite_0_S_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="O" MPD_INDEX="152" NAME="M_AXI_DP_BREADY" SIGNAME="axi4lite_0_S_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARID" DIR="O" MPD_INDEX="153" NAME="M_AXI_DP_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_ARID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="154" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="155" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[7:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="156" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_ARSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="157" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_ARBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="O" MPD_INDEX="158" NAME="M_AXI_DP_ARLOCK" SIGNAME="axi4lite_0_S_ARLOCK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_ARLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="159" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_ARCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="160" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_ARPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="161" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_ARQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="O" MPD_INDEX="162" NAME="M_AXI_DP_ARVALID" SIGNAME="axi4lite_0_S_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="I" MPD_INDEX="163" NAME="M_AXI_DP_ARREADY" SIGNAME="axi4lite_0_S_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RID" DIR="I" MPD_INDEX="164" NAME="M_AXI_DP_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_RID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_DP" DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="165" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="S_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
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            <PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/>
            <PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="DLMB" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="RESET"/>
            <PORTMAP DIR="I" PHYSICAL="DATA_READ"/>
            <PORTMAP DIR="I" PHYSICAL="DREADY"/>
            <PORTMAP DIR="I" PHYSICAL="DWAIT"/>
            <PORTMAP DIR="I" PHYSICAL="DCE"/>
            <PORTMAP DIR="I" PHYSICAL="DUE"/>
            <PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/>
            <PORTMAP DIR="O" PHYSICAL="D_AS"/>
            <PORTMAP DIR="O" PHYSICAL="READ_STROBE"/>
            <PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/>
            <PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="RESET"/>
            <PORTMAP DIR="I" PHYSICAL="INSTR"/>
            <PORTMAP DIR="I" PHYSICAL="IREADY"/>
            <PORTMAP DIR="I" PHYSICAL="IWAIT"/>
            <PORTMAP DIR="I" PHYSICAL="ICE"/>
            <PORTMAP DIR="I" PHYSICAL="IUE"/>
            <PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/>
            <PORTMAP DIR="O" PHYSICAL="IFETCH"/>
            <PORTMAP DIR="O" PHYSICAL="I_AS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="CLK"/>
            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBINTERRUPT" MPD_INDEX="108" NAME="INTERRUPT" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="INTERRUPT"/>
            <PORTMAP DIR="I" PHYSICAL="INTERRUPT_ADDRESS"/>
            <PORTMAP DIR="O" PHYSICAL="INTERRUPT_ACK"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="DBG_CLK"/>
            <PORTMAP DIR="I" PHYSICAL="DBG_TDI"/>
            <PORTMAP DIR="O" PHYSICAL="DBG_TDO"/>
            <PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/>
            <PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/>
            <PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/>
            <PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/>
            <PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_PC"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/>
            <PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="fsl_v20_0" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="fsl_v20_2" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="fsl_v20_1" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/>
            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/>
            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/>
            <PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/>
            <PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="32767" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00007fff" INSTANCE="microblaze_0_d_bram_ctrl" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="32768" SIZEABRV="32K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_dlmb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="32767" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00007fff" INSTANCE="microblaze_0_i_bram_ctrl" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="32768" SIZEABRV="32K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="microblaze_0_ilmb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1094713344" BASENAME="C_BASEADDR" BASEVALUE="0x41400000" HIGHDECIMAL="1094778879" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4140ffff" INSTANCE="debug_module" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" INSTANCE="Push_Buttons_4Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" INSTANCE="LEDs_8Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1074003968" BASENAME="C_BASEADDR" BASEVALUE="0x40040000" HIGHDECIMAL="1074069503" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4004ffff" INSTANCE="DIP_Switches_8Bits" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1082130432" BASENAME="C_BASEADDR" BASEVALUE="0x40800000" HIGHDECIMAL="1082195967" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4080ffff" INSTANCE="axi_iic_0" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi4lite_0"/>
          </ACCESSROUTE>
        </MEMRANGE>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="microblaze_0_d_bram_ctrl"/>
        <PERIPHERAL INSTANCE="microblaze_0_i_bram_ctrl"/>
        <PERIPHERAL INSTANCE="debug_module"/>
        <PERIPHERAL INSTANCE="RS232_Uart_1"/>
        <PERIPHERAL INSTANCE="Push_Buttons_4Bits"/>
        <PERIPHERAL INSTANCE="LEDs_8Bits"/>
        <PERIPHERAL INSTANCE="DIP_Switches_8Bits"/>
        <PERIPHERAL INSTANCE="axi_iic_0"/>
        <PERIPHERAL INSTANCE="mem_to_vga_0"/>
        <PERIPHERAL INSTANCE="fsl_to_axi_0"/>
      </PERIPHERALS>
    </MODULE>
    <MODULE HWVERSION="2.10.a" INSTANCE="debug_module" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="DEBUG" MODTYPE="mdm">
      <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x41400000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x4140ffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="3"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_USE_BSCAN" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="15" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="16" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="17" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Debug_Sys_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="MB_Debug_Sys_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0" PORT="EXT_BRK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="microblaze_0" PORT="EXT_NM_BRK"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="31" MSB="0" NAME="PLB_masterID" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="32" NAME="PLB_abort" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
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        <PORT BUS="MBDEBUG_29" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="304" NAME="Dbg_Rst_29" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_30" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="305" NAME="Dbg_Clk_30" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_30" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="306" NAME="Dbg_TDI_30" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_30" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="307" NAME="Dbg_TDO_30" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_30" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="308" MSB="0" NAME="Dbg_Reg_En_30" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
        <PORT BUS="MBDEBUG_30" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="309" NAME="Dbg_Capture_30" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_30" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="310" NAME="Dbg_Shift_30" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_30" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="311" NAME="Dbg_Update_30" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_30" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="312" NAME="Dbg_Rst_30" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_31" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="313" NAME="Dbg_Clk_31" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_31" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="314" NAME="Dbg_TDI_31" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_31" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="315" NAME="Dbg_TDO_31" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_31" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="316" MSB="0" NAME="Dbg_Reg_En_31" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
        <PORT BUS="MBDEBUG_31" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="317" NAME="Dbg_Capture_31" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_31" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="318" NAME="Dbg_Shift_31" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_31" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="319" NAME="Dbg_Update_31" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_31" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="320" NAME="Dbg_Rst_31" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="321" NAME="bscan_tdi" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="322" NAME="bscan_reset" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="323" NAME="bscan_shift" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="324" NAME="bscan_update" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="325" NAME="bscan_capture" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="326" NAME="bscan_sel1" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="327" NAME="bscan_drck1" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="328" NAME="bscan_tdo1" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="329" NAME="bscan_ext_tdi" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="330" NAME="bscan_ext_reset" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="331" NAME="bscan_ext_shift" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="332" NAME="bscan_ext_update" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="333" NAME="bscan_ext_capture" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="334" NAME="bscan_ext_sel" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="335" NAME="bscan_ext_drck" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="336" NAME="bscan_ext_tdo" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="337" NAME="Ext_JTAG_DRCK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="338" NAME="Ext_JTAG_RESET" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="339" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="340" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="341" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="342" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="343" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="344" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_size"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_type"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
            <PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
            <PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="microblaze_0_debug" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="10" NAME="MBDEBUG_8" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_8"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_8"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_8"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_8"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_8"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_8"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_8"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_8"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="11" NAME="MBDEBUG_9" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_9"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_9"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_9"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_9"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_9"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_9"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_9"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_9"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="12" NAME="MBDEBUG_10" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_10"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_10"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_10"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_10"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_10"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_10"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_10"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_10"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="13" NAME="MBDEBUG_11" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_11"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_11"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_11"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_11"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_11"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_11"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_11"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_11"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="14" NAME="MBDEBUG_12" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_12"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_12"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_12"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_12"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_12"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_12"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_12"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_12"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="15" NAME="MBDEBUG_13" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_13"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_13"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_13"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_13"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_13"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_13"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_13"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_13"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="16" NAME="MBDEBUG_14" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_14"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_14"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_14"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_14"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_14"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_14"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_14"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_14"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="17" NAME="MBDEBUG_15" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_15"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_15"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_15"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_15"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_15"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_15"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_15"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_15"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="18" NAME="MBDEBUG_16" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_16"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_16"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_16"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_16"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_16"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_16"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_16"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_16"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="19" NAME="MBDEBUG_17" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_17"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_17"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_17"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_17"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_17"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_17"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_17"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_17"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="20" NAME="MBDEBUG_18" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_18"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_18"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_18"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_18"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_18"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_18"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_18"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_18"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="21" NAME="MBDEBUG_19" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_19"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_19"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_19"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_19"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_19"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_19"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_19"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_19"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="22" NAME="MBDEBUG_20" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_20"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_20"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_20"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_20"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_20"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_20"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_20"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_20"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="23" NAME="MBDEBUG_21" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_21"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_21"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_21"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_21"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_21"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_21"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_21"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_21"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="24" NAME="MBDEBUG_22" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_22"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_22"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_22"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_22"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_22"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_22"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_22"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_22"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="25" NAME="MBDEBUG_23" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_23"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_23"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_23"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_23"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_23"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_23"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_23"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_23"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="26" NAME="MBDEBUG_24" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_24"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_24"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_24"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_24"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_24"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_24"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_24"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_24"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="27" NAME="MBDEBUG_25" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_25"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_25"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_25"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_25"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_25"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_25"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_25"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_25"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="28" NAME="MBDEBUG_26" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_26"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_26"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_26"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_26"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_26"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_26"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_26"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_26"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="29" NAME="MBDEBUG_27" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_27"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_27"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_27"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_27"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_27"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_27"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_27"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_27"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="30" NAME="MBDEBUG_28" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_28"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_28"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_28"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_28"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_28"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_28"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_28"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_28"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="31" NAME="MBDEBUG_29" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_29"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_29"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_29"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_29"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_29"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_29"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_29"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_29"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="32" NAME="MBDEBUG_30" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_30"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_30"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_30"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_30"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_30"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_30"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_30"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_30"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="33" NAME="MBDEBUG_31" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Clk_31"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_TDI_31"/>
            <PORTMAP DIR="I" PHYSICAL="Dbg_TDO_31"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_31"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Capture_31"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Shift_31"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Update_31"/>
            <PORTMAP DIR="O" PHYSICAL="Dbg_Rst_31"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="34" NAME="XMTC" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/>
            <PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/>
            <PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1094713344" BASENAME="C_BASEADDR" BASEVALUE="0x41400000" HIGHDECIMAL="1094778879" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4140ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="4.03.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="IP" MODTYPE="clock_generator">
      <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_03_a/doc/clock_generator.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx16"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="csg324"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-3"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="25000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="94" NAME="C_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="95" NAME="C_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="96" NAME="C_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="97" NAME="C_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="98" NAME="C_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="99" NAME="C_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="100" NAME="C_CLKOUT6_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="101" NAME="C_CLKOUT7_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="102" NAME="C_CLKOUT8_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="103" NAME="C_CLKOUT9_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="104" NAME="C_CLKOUT10_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="105" NAME="C_CLKOUT11_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="106" NAME="C_CLKOUT12_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="107" NAME="C_CLKOUT13_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="108" NAME="C_CLKOUT14_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="109" NAME="C_CLKOUT15_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="110" NAME="C_CLK_GEN" VALUE="UPDATE"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="24" NAME="LOCKED" SIGNAME="proc_sys_reset_0_Dcm_locked">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Dcm_locked"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Slowest_sync_clk"/>
            <CONNECTION INSTANCE="microblaze_0_ilmb" PORT="LMB_CLK"/>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_i_bram_ctrl" PORT="LMB_Clk"/>
            <CONNECTION INSTANCE="microblaze_0_dlmb" PORT="LMB_CLK"/>
            <CONNECTION BUSINTERFACE="[SLMB]" INSTANCE="microblaze_0_d_bram_ctrl" PORT="LMB_Clk"/>
            <CONNECTION BUSINTERFACE="[DLMB:ILMB:M_AXI_DP:M_AXI_IP]" INSTANCE="microblaze_0" PORT="CLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI_CTRL]" INSTANCE="axi4lite_0" PORT="INTERCONNECT_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_ACLK"/>
            <CONNECTION BUSINTERFACE="[MFSL:SFSL]" INSTANCE="fsl_to_axi_0" PORT="FSL_Clk"/>
            <CONNECTION BUSINTERFACE="[SFSL]" INSTANCE="mem_to_vga_0" PORT="FSL_Clk"/>
            <CONNECTION INSTANCE="fsl_v20_0" PORT="FSL_Clk"/>
            <CONNECTION INSTANCE="fsl_v20_1" PORT="FSL_Clk"/>
            <CONNECTION INSTANCE="fsl_v20_2" PORT="FSL_Clk"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_ACLK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="RESET">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="RESET"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="GCLK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="GCLK"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="25000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="clock_generator_0_CLKOUT1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mem_to_vga_0" PORT="pixel_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.06.a" INSTANCE="axi4lite_0" IPTYPE="BUS" MHS_INDEX="9" MODCLASS="BUS" MODTYPE="axi_interconnect">
      <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="6"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000200000002000000020000000200000002"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="[encoded data, 4098 characters]"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="[encoded data, 4098 characters]"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e10005f5e10005f5e10005f5e10005f5e100"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_S_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_M_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_MAX_DEBUG_THREADS" TYPE="INTEGER" VALUE="1"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="interconnect_aclk" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="proc_sys_reset_0_Interconnect_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="Interconnect_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi4lite_0_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="3" MSB="5" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_ARESETN"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_ARESETN"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_ARESETN"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_ARESETN"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_ARESETN"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_ARESETN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="axi4lite_0_S_ACLK" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="axi4lite_0_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi4lite_0_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_AWID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_AWLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_AWSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_AWBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_AWLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_AWCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_AWPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_AWQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi4lite_0_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_WID" DIR="I" MPD_INDEX="18" NAME="S_AXI_WID" SIGNAME="axi4lite_0_S_WID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_WLAST" DIR="I" MPD_INDEX="21" NAME="S_AXI_WLAST" SIGNAME="axi4lite_0_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_WLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_WUSER" DIR="I" MPD_INDEX="22" NAME="S_AXI_WUSER" SIGNAME="axi4lite_0_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_WVALID" DIR="I" MPD_INDEX="23" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_WREADY" DIR="O" MPD_INDEX="24" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_BID" DIR="O" MPD_INDEX="25" NAME="S_AXI_BID" SIGNAME="axi4lite_0_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_BID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_BUSER" DIR="O" MPD_INDEX="27" NAME="S_AXI_BUSER" SIGNAME="axi4lite_0_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_BVALID" DIR="O" MPD_INDEX="28" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_BREADY" DIR="I" MPD_INDEX="29" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARID" DIR="I" MPD_INDEX="30" NAME="S_AXI_ARID" SIGNAME="axi4lite_0_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_ARID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="31" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="32" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="33" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_ARSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_ARBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="35" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_ARLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="36" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_ARCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_ARPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="38" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_ARQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARUSER" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARUSER" SIGNAME="axi4lite_0_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARVALID" DIR="I" MPD_INDEX="40" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_ARREADY" DIR="O" MPD_INDEX="41" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_RID" DIR="O" MPD_INDEX="42" NAME="S_AXI_RID" SIGNAME="axi4lite_0_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_RID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="43" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_RLAST" DIR="O" MPD_INDEX="45" NAME="S_AXI_RLAST" SIGNAME="axi4lite_0_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_RLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_RUSER" DIR="O" MPD_INDEX="46" NAME="S_AXI_RUSER" SIGNAME="axi4lite_0_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_RVALID" DIR="O" MPD_INDEX="47" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_S_RREADY" DIR="I" MPD_INDEX="48" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_DP]" INSTANCE="microblaze_0" PORT="M_AXI_DP_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="49" MSB="5" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="axi4lite_0_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="50" MSB="5" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi4lite_0_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="191" LSB="0" MPD_INDEX="51" MSB="191" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_AWADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_AWADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_AWADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_AWADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_AWADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="52" MSB="47" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi4lite_0_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="53" MSB="17" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="54" MSB="11" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi4lite_0_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="55" MSB="11" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="56" MSB="23" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="57" MSB="17" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi4lite_0_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="58" MSB="23" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi4lite_0_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="59" MSB="23" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi4lite_0_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="60" MSB="5" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi4lite_0_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="61" MSB="5" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi4lite_0_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_AWVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_AWVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_AWVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_AWVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_AWVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="62" MSB="5" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi4lite_0_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_AWREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_AWREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_AWREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_AWREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_AWREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="63" MSB="5" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi4lite_0_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="191" LSB="0" MPD_INDEX="64" MSB="191" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_WDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_WDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_WDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_WDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_WDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="65" MSB="23" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_WSTRB"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_WSTRB"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_WSTRB"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_WSTRB"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_WSTRB"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="66" MSB="5" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi4lite_0_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="67" MSB="5" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi4lite_0_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="68" MSB="5" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi4lite_0_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_WVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_WVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_WVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_WVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_WVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="69" MSB="5" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi4lite_0_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_WREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_WREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_WREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_WREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_WREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="70" MSB="5" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi4lite_0_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="71" MSB="11" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_BRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_BRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_BRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_BRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_BRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="72" MSB="5" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi4lite_0_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="73" MSB="5" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi4lite_0_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_BVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_BVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_BVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_BVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_BVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="74" MSB="5" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi4lite_0_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_BREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_BREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_BREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_BREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_BREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="75" MSB="5" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi4lite_0_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="191" LSB="0" MPD_INDEX="76" MSB="191" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_ARADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_ARADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_ARADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_ARADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_ARADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="77" MSB="47" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi4lite_0_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="78" MSB="17" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi4lite_0_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="79" MSB="11" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi4lite_0_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="80" MSB="11" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi4lite_0_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="81" MSB="23" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi4lite_0_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="82" MSB="17" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi4lite_0_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="83" MSB="23" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi4lite_0_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="84" MSB="23" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi4lite_0_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="85" MSB="5" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi4lite_0_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="86" MSB="5" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi4lite_0_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_ARVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_ARVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_ARVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_ARVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_ARVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="87" MSB="5" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi4lite_0_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_ARREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_ARREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_ARREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_ARREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_ARREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="88" MSB="5" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi4lite_0_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="191" LSB="0" MPD_INDEX="89" MSB="191" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_RDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_RDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_RDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_RDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_RDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="90" MSB="11" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_RRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_RRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_RRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_RRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_RRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="91" MSB="5" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi4lite_0_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="92" MSB="5" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi4lite_0_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="93" MSB="5" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi4lite_0_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_RVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_RVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_RVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_RVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_RVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="94" MSB="5" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi4lite_0_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="debug_module" PORT="S_AXI_RREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="RS232_Uart_1" PORT="S_AXI_RREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="Push_Buttons_4Bits" PORT="S_AXI_RREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="LEDs_8Bits" PORT="S_AXI_RREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="DIP_Switches_8Bits" PORT="S_AXI_RREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="95" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="96" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="101" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="104" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="105" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="108" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="110" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="111" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="115" MSB="7" NAME="DEBUG_AR_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="116" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="117" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="118" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="122" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="123" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="124" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="125" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="133" MSB="7" NAME="DEBUG_AW_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="DEBUG_AR_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="DEBUG_W_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="136" MSB="7" NAME="DEBUG_W_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="137" MSB="7" NAME="DEBUG_BID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="138" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="139" MSB="7" NAME="DEBUG_RID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="140" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="141" MSB="31" NAME="DEBUG_SR_SC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="142" MSB="23" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="143" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="144" MSB="23" NAME="DEBUG_SR_SC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="145" MSB="4" NAME="DEBUG_SR_SC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="146" MSB="31" NAME="DEBUG_SR_SC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="147" MSB="5" NAME="DEBUG_SR_SC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="148" MSB="31" NAME="DEBUG_SR_SC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="149" MSB="6" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="150" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="151" MSB="23" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="153" MSB="23" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="154" MSB="4" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="155" MSB="31" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="156" MSB="5" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="158" MSB="6" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="159" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="160" MSB="23" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="161" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="162" MSB="23" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="163" MSB="4" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="164" MSB="31" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="165" MSB="5" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="166" MSB="31" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="167" MSB="6" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="168" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="169" MSB="23" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="170" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="171" MSB="23" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="172" MSB="4" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="173" MSB="31" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="174" MSB="5" NAME="DEBUG_CB_MF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="175" MSB="31" NAME="DEBUG_CB_MF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="176" MSB="6" NAME="DEBUG_CB_MF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="177" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="178" MSB="23" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="179" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="180" MSB="23" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="181" MSB="4" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="182" MSB="31" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="183" MSB="5" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="184" MSB="31" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="185" MSB="6" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="187" MSB="23" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="188" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="189" MSB="23" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="190" MSB="4" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="191" MSB="31" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="192" MSB="5" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="193" MSB="31" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="194" MSB="6" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="195" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="196" MSB="23" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="197" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="198" MSB="23" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="199" MSB="4" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="200" MSB="31" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="201" MSB="5" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="202" MSB="31" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="203" MSB="6" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="interconnect_aclk"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.02.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="PERIPHERAL" MODTYPE="axi_uartlite">
      <DESCRIPTION TYPE="SHORT">AXI UART (Lite)</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uartlite_v1_02_a/doc/axi_uartlite_ds741.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_INSTANCE" TYPE="STRING" VALUE="RS232_Uart_1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="2" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40600000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4060ffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="6" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="7" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="9600"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="8" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="9" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="10" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="11" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="21" NAME="TX" SIGNAME="RS232_Uart_1_sout">
          <DESCRIPTION>Serial Data Out</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="RS232_Uart_1_sout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="20" NAME="RX" SIGNAME="RS232_Uart_1_sin">
          <DESCRIPTION>Serial Data In</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="RS232_Uart_1_sin"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="2" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="3" MSB="3" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1_hide">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="TX"/>
            <PORTMAP DIR="I" PHYSICAL="RX"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1080033280" BASENAME="C_BASEADDR" BASEVALUE="0x40600000" HIGHDECIMAL="1080098815" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4060ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.01.b" INSTANCE="Push_Buttons_4Bits" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
      <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_INSTANCE" TYPE="STRING" VALUE="Push_Buttons_4Bits"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4000ffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="9"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="8" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="10" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="13" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="1" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="Push_Buttons_4Bits_TRI_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="Push_Buttons_4Bits_TRI_I"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="2" MSB="8" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="12" MSB="8" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1073807359" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4000ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.01.b" INSTANCE="LEDs_8Bits" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
      <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_INSTANCE" TYPE="STRING" VALUE="LEDs_8Bits"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40020000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4002ffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="9"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="8" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="10" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="13" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="1" MPD_INDEX="21" MSB="7" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="LEDs_8Bits_TRI_O" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="LEDs_8Bits_TRI_O"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="2" MSB="8" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="12" MSB="8" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="7" LSB="0" MPD_INDEX="20" MSB="7" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="7" LSB="0" MPD_INDEX="26" MSB="7" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1073872896" BASENAME="C_BASEADDR" BASEVALUE="0x40020000" HIGHDECIMAL="1073938431" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4002ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.01.b" INSTANCE="DIP_Switches_8Bits" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
      <DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_b/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_INSTANCE" TYPE="STRING" VALUE="DIP_Switches_8Bits"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40040000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4004ffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="9"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="8" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="10" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="13" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="1" MPD_INDEX="20" MSB="7" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="DIP_Switches_8Bits_TRI_I" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="DIP_Switches_8Bits_TRI_I"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="2" MSB="8" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="12" MSB="8" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="7" LSB="0" MPD_INDEX="21" MSB="7" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="7" LSB="0" MPD_INDEX="26" MSB="7" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
            <PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1074003968" BASENAME="C_BASEADDR" BASEVALUE="0x40040000" HIGHDECIMAL="1074069503" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4004ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="fsl_to_axi_0" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="PERIPHERAL" MODTYPE="fsl_to_axi">
      <LICENSEINFO ICON_NAME="ps_core_local"/>
      <PARAMETERS/>
      <PORTS>
        <PORT BUS="MFSL:SFSL" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHz" DIR="I" MPD_INDEX="0" NAME="FSL_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MFSL:SFSL" DEF_SIGNAME="fsl_v20_2_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="FSL_Rst" SIGIS="RST" SIGNAME="fsl_v20_2_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_2" PORT="FSL_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SFSL" DEF_SIGNAME="fsl_v20_1_FSL_S_Clk" DIR="I" MPD_INDEX="2" NAME="FSL_S_Clk" SIGIS="CLK" SIGNAME="fsl_v20_1_FSL_S_Clk">
          <CONNECTIONS/>
        </PORT>
        <PORT BUS="SFSL" DEF_SIGNAME="fsl_v20_1_FSL_S_Read" DIR="O" MPD_INDEX="3" NAME="FSL_S_Read" SIGNAME="fsl_v20_1_FSL_S_Read">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_1" PORT="FSL_S_Read"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SFSL" DEF_SIGNAME="fsl_v20_1_FSL_S_Data" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="FSL_S_Data" RIGHT="31" SIGNAME="fsl_v20_1_FSL_S_Data" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_1" PORT="FSL_S_Data"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SFSL" DEF_SIGNAME="fsl_v20_1_FSL_S_Control" DIR="I" MPD_INDEX="5" NAME="FSL_S_Control" SIGNAME="fsl_v20_1_FSL_S_Control">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_1" PORT="FSL_S_Control"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SFSL" DEF_SIGNAME="fsl_v20_1_FSL_S_Exists" DIR="I" MPD_INDEX="6" NAME="FSL_S_Exists" SIGNAME="fsl_v20_1_FSL_S_Exists">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_1" PORT="FSL_S_Exists"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MFSL" DEF_SIGNAME="fsl_v20_2_FSL_M_Clk" DIR="I" MPD_INDEX="7" NAME="FSL_M_Clk" SIGIS="CLK" SIGNAME="fsl_v20_2_FSL_M_Clk">
          <CONNECTIONS/>
        </PORT>
        <PORT BUS="MFSL" DEF_SIGNAME="fsl_v20_2_FSL_M_Write" DIR="O" MPD_INDEX="8" NAME="FSL_M_Write" SIGNAME="fsl_v20_2_FSL_M_Write">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_2" PORT="FSL_M_Write"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MFSL" DEF_SIGNAME="fsl_v20_2_FSL_M_Data" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="FSL_M_Data" RIGHT="31" SIGNAME="fsl_v20_2_FSL_M_Data" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_2" PORT="FSL_M_Data"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MFSL" DEF_SIGNAME="fsl_v20_2_FSL_M_Control" DIR="O" MPD_INDEX="10" NAME="FSL_M_Control" SIGNAME="fsl_v20_2_FSL_M_Control">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_2" PORT="FSL_M_Control"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="MFSL" DEF_SIGNAME="fsl_v20_2_FSL_M_Full" DIR="I" MPD_INDEX="11" NAME="FSL_M_Full" SIGNAME="fsl_v20_2_FSL_M_Full">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_2" PORT="FSL_M_Full"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="fsl_v20_2" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="MFSL" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_M_Clk"/>
            <PORTMAP DIR="O" PHYSICAL="FSL_M_Write"/>
            <PORTMAP DIR="O" PHYSICAL="FSL_M_Data"/>
            <PORTMAP DIR="O" PHYSICAL="FSL_M_Control"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_M_Full"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="fsl_v20_1" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SFSL" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_S_Clk"/>
            <PORTMAP DIR="O" PHYSICAL="FSL_S_Read"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_S_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_S_Control"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="mem_to_vga_0" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="mem_to_vga">
      <LICENSEINFO ICON_NAME="ps_core_local"/>
      <PARAMETERS/>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="8" NAME="HS" SIGNAME="mem_to_vga_0_HS">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="mem_to_vga_0_HS_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="7" MHS_INDEX="1" MPD_INDEX="10" MSB="0" NAME="rgb" RIGHT="7" SIGNAME="mem_to_vga_0_rgb" VECFORMULA="[0:7]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="mem_to_vga_0_rgb_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="9" NAME="VS" SIGNAME="mem_to_vga_0_VS">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="mem_to_vga_0_VS_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="25000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="7" NAME="pixel_clk" SIGIS="CLK" SIGNAME="clock_generator_0_CLKOUT1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT1"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SFSL" CLKFREQUENCY="100000000" DEF_SIGNAME="clk_100_0000MHz" DIR="I" MPD_INDEX="0" NAME="FSL_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SFSL" DEF_SIGNAME="fsl_v20_0_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="FSL_Rst" SIGIS="RST" SIGNAME="fsl_v20_0_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_0" PORT="FSL_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SFSL" DEF_SIGNAME="fsl_v20_0_FSL_S_Clk" DIR="I" MPD_INDEX="2" NAME="FSL_S_Clk" SIGIS="CLK" SIGNAME="fsl_v20_0_FSL_S_Clk">
          <CONNECTIONS/>
        </PORT>
        <PORT BUS="SFSL" DEF_SIGNAME="fsl_v20_0_FSL_S_Read" DIR="O" MPD_INDEX="3" NAME="FSL_S_Read" SIGNAME="fsl_v20_0_FSL_S_Read">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_0" PORT="FSL_S_Read"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SFSL" DEF_SIGNAME="fsl_v20_0_FSL_S_Data" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="FSL_S_Data" RIGHT="31" SIGNAME="fsl_v20_0_FSL_S_Data" VECFORMULA="[0:31]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_0" PORT="FSL_S_Data"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SFSL" DEF_SIGNAME="fsl_v20_0_FSL_S_Control" DIR="I" MPD_INDEX="5" NAME="FSL_S_Control" SIGNAME="fsl_v20_0_FSL_S_Control">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_0" PORT="FSL_S_Control"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="SFSL" DEF_SIGNAME="fsl_v20_0_FSL_S_Exists" DIR="I" MPD_INDEX="6" NAME="FSL_S_Exists" SIGNAME="fsl_v20_0_FSL_S_Exists">
          <CONNECTIONS>
            <CONNECTION INSTANCE="fsl_v20_0" PORT="FSL_S_Exists"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="fsl_v20_0" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SFSL" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FSL_Clk"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_Rst"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_S_Clk"/>
            <PORTMAP DIR="O" PHYSICAL="FSL_S_Read"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_S_Data"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_S_Control"/>
            <PORTMAP DIR="I" PHYSICAL="FSL_S_Exists"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE BUSSTD="FSL" BUSSTD_PSF="FSL" HWVERSION="2.11.e" INSTANCE="fsl_v20_0" IPTYPE="BUS" MHS_INDEX="16" MODCLASS="BUS" MODTYPE="fsl_v20">
      <DESCRIPTION TYPE="SHORT">Fast Simplex Link (FSL) Bus</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="0" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="1" NAME="C_ASYNC_CLKS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_IMPL_STYLE" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_CONTROL" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="4" NAME="C_FSL_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_FSL_DEPTH" TYPE="integer" VALUE="16"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="6" NAME="C_READ_CLOCK_PERIOD" TYPE="integer" VALUE="0"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="FSL_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="MB_Reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_0_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="FSL_Rst" SIGNAME="fsl_v20_0_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL]" INSTANCE="mem_to_vga_0" PORT="FSL_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" MPD_INDEX="3" NAME="FSL_M_Clk" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="fsl_v20_0_FSL_M_Data" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="FSL_M_Data" RIGHT="31" SIGNAME="fsl_v20_0_FSL_M_Data" VECFORMULA="[0:C_FSL_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL0:DWFSL0]" INSTANCE="microblaze_0" PORT="FSL0_M_DATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_0_FSL_M_Control" DIR="I" MPD_INDEX="5" NAME="FSL_M_Control" SIGNAME="fsl_v20_0_FSL_M_Control">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL0:DWFSL0]" INSTANCE="microblaze_0" PORT="FSL0_M_CONTROL"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_0_FSL_M_Write" DIR="I" MPD_INDEX="6" NAME="FSL_M_Write" SIGNAME="fsl_v20_0_FSL_M_Write">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL0:DWFSL0]" INSTANCE="microblaze_0" PORT="FSL0_M_WRITE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_0_FSL_M_Full" DIR="O" MPD_INDEX="7" NAME="FSL_M_Full" SIGNAME="fsl_v20_0_FSL_M_Full">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL0:DWFSL0]" INSTANCE="microblaze_0" PORT="FSL0_M_FULL"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" MPD_INDEX="8" NAME="FSL_S_Clk" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="fsl_v20_0_FSL_S_Data" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="FSL_S_Data" RIGHT="31" SIGNAME="fsl_v20_0_FSL_S_Data" VECFORMULA="[0:C_FSL_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL]" INSTANCE="mem_to_vga_0" PORT="FSL_S_Data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_0_FSL_S_Control" DIR="O" MPD_INDEX="10" NAME="FSL_S_Control" SIGNAME="fsl_v20_0_FSL_S_Control">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL]" INSTANCE="mem_to_vga_0" PORT="FSL_S_Control"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_0_FSL_S_Read" DIR="I" MPD_INDEX="11" NAME="FSL_S_Read" SIGNAME="fsl_v20_0_FSL_S_Read">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL]" INSTANCE="mem_to_vga_0" PORT="FSL_S_Read"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_0_FSL_S_Exists" DIR="O" MPD_INDEX="12" NAME="FSL_S_Exists" SIGNAME="fsl_v20_0_FSL_S_Exists">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL]" INSTANCE="mem_to_vga_0" PORT="FSL_S_Exists"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="13" NAME="FSL_Full" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="14" NAME="FSL_Has_Data" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="15" NAME="FSL_Control_IRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE BUSSTD="FSL" BUSSTD_PSF="FSL" HWVERSION="2.11.e" INSTANCE="fsl_v20_1" IPTYPE="BUS" MHS_INDEX="17" MODCLASS="BUS" MODTYPE="fsl_v20">
      <DESCRIPTION TYPE="SHORT">Fast Simplex Link (FSL) Bus</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="0" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="1" NAME="C_ASYNC_CLKS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_IMPL_STYLE" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_CONTROL" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="4" NAME="C_FSL_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="5" NAME="C_FSL_DEPTH" TYPE="integer" VALUE="16"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="6" NAME="C_READ_CLOCK_PERIOD" TYPE="integer" VALUE="0"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="FSL_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="MB_Reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_1_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="FSL_Rst" SIGNAME="fsl_v20_1_LMB_Rst">
          <CONNECTIONS/>
        </PORT>
        <PORT DIR="I" MPD_INDEX="3" NAME="FSL_M_Clk" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="fsl_v20_1_FSL_M_Data" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="FSL_M_Data" RIGHT="31" SIGNAME="fsl_v20_1_FSL_M_Data" VECFORMULA="[0:C_FSL_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL1:DWFSL1]" INSTANCE="microblaze_0" PORT="FSL1_M_DATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_1_FSL_M_Control" DIR="I" MPD_INDEX="5" NAME="FSL_M_Control" SIGNAME="fsl_v20_1_FSL_M_Control">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL1:DWFSL1]" INSTANCE="microblaze_0" PORT="FSL1_M_CONTROL"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_1_FSL_M_Write" DIR="I" MPD_INDEX="6" NAME="FSL_M_Write" SIGNAME="fsl_v20_1_FSL_M_Write">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL1:DWFSL1]" INSTANCE="microblaze_0" PORT="FSL1_M_WRITE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_1_FSL_M_Full" DIR="O" MPD_INDEX="7" NAME="FSL_M_Full" SIGNAME="fsl_v20_1_FSL_M_Full">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL1:DWFSL1]" INSTANCE="microblaze_0" PORT="FSL1_M_FULL"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" MPD_INDEX="8" NAME="FSL_S_Clk" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="fsl_v20_1_FSL_S_Data" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="FSL_S_Data" RIGHT="31" SIGNAME="fsl_v20_1_FSL_S_Data" VECFORMULA="[0:C_FSL_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL]" INSTANCE="fsl_to_axi_0" PORT="FSL_S_Data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_1_FSL_S_Control" DIR="O" MPD_INDEX="10" NAME="FSL_S_Control" SIGNAME="fsl_v20_1_FSL_S_Control">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL]" INSTANCE="fsl_to_axi_0" PORT="FSL_S_Control"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_1_FSL_S_Read" DIR="I" MPD_INDEX="11" NAME="FSL_S_Read" SIGNAME="fsl_v20_1_FSL_S_Read">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL]" INSTANCE="fsl_to_axi_0" PORT="FSL_S_Read"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_1_FSL_S_Exists" DIR="O" MPD_INDEX="12" NAME="FSL_S_Exists" SIGNAME="fsl_v20_1_FSL_S_Exists">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL]" INSTANCE="fsl_to_axi_0" PORT="FSL_S_Exists"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="13" NAME="FSL_Full" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="14" NAME="FSL_Has_Data" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="15" NAME="FSL_Control_IRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE BUSSTD="FSL" BUSSTD_PSF="FSL" HWVERSION="2.11.e" INSTANCE="fsl_v20_2" IPTYPE="BUS" MHS_INDEX="18" MODCLASS="BUS" MODTYPE="fsl_v20">
      <DESCRIPTION TYPE="SHORT">Fast Simplex Link (FSL) Bus</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="0" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="1" NAME="C_ASYNC_CLKS" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_IMPL_STYLE" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="C_USE_CONTROL" TYPE="integer" VALUE="0"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="4" NAME="C_FSL_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_FSL_DEPTH" TYPE="integer" VALUE="128"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="6" NAME="C_READ_CLOCK_PERIOD" TYPE="integer" VALUE="0"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="FSL_Clk" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGIS="RST" SIGNAME="proc_sys_reset_0_MB_Reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="proc_sys_reset_0" PORT="MB_Reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_2_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="FSL_Rst" SIGNAME="fsl_v20_2_LMB_Rst">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL:SFSL]" INSTANCE="fsl_to_axi_0" PORT="FSL_Rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" MPD_INDEX="3" NAME="FSL_M_Clk" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="fsl_v20_2_FSL_M_Data" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="FSL_M_Data" RIGHT="31" SIGNAME="fsl_v20_2_FSL_M_Data" VECFORMULA="[0:C_FSL_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL]" INSTANCE="fsl_to_axi_0" PORT="FSL_M_Data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_2_FSL_M_Control" DIR="I" MPD_INDEX="5" NAME="FSL_M_Control" SIGNAME="fsl_v20_2_FSL_M_Control">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL]" INSTANCE="fsl_to_axi_0" PORT="FSL_M_Control"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_2_FSL_M_Write" DIR="I" MPD_INDEX="6" NAME="FSL_M_Write" SIGNAME="fsl_v20_2_FSL_M_Write">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL]" INSTANCE="fsl_to_axi_0" PORT="FSL_M_Write"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_2_FSL_M_Full" DIR="O" MPD_INDEX="7" NAME="FSL_M_Full" SIGNAME="fsl_v20_2_FSL_M_Full">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[MFSL]" INSTANCE="fsl_to_axi_0" PORT="FSL_M_Full"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" MPD_INDEX="8" NAME="FSL_S_Clk" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="fsl_v20_2_FSL_S_Data" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="FSL_S_Data" RIGHT="31" SIGNAME="fsl_v20_2_FSL_S_Data" VECFORMULA="[0:C_FSL_DWIDTH-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL1:DRFSL1]" INSTANCE="microblaze_0" PORT="FSL1_S_DATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_2_FSL_S_Control" DIR="O" MPD_INDEX="10" NAME="FSL_S_Control" SIGNAME="fsl_v20_2_FSL_S_Control">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL1:DRFSL1]" INSTANCE="microblaze_0" PORT="FSL1_S_CONTROL"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_2_FSL_S_Read" DIR="I" MPD_INDEX="11" NAME="FSL_S_Read" SIGNAME="fsl_v20_2_FSL_S_Read">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL1:DRFSL1]" INSTANCE="microblaze_0" PORT="FSL1_S_READ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="fsl_v20_2_FSL_S_Exists" DIR="O" MPD_INDEX="12" NAME="FSL_S_Exists" SIGNAME="fsl_v20_2_FSL_S_Exists">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[SFSL1:DRFSL1]" INSTANCE="microblaze_0" PORT="FSL1_S_EXISTS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="13" NAME="FSL_Full" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="14" NAME="FSL_Has_Data" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="15" NAME="FSL_Control_IRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE HWVERSION="1.02.a" INSTANCE="axi_iic_0" IPTYPE="PERIPHERAL" MHS_INDEX="19" MODCLASS="PERIPHERAL" MODTYPE="axi_iic">
      <DESCRIPTION TYPE="SHORT">AXI IIC Interface</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">AXI interface to Philips I2C bus v2.1</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_iic_v1_02_a/doc/axi_iic_ds756.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_INSTANCE" TYPE="STRING" VALUE="axi_iic_0"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x40800000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4080ffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="9"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_IIC_FREQ" TYPE="INTEGER" VALUE="800000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_TEN_BIT_ADR" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_GPO_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="10" NAME="C_SCL_INERTIAL_DELAY" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="11" NAME="C_SDA_INERTIAL_DELAY" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_SDA_LEVEL" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="13" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="clk_100_0000MHz">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="iic_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="26" NAME="Gpo" SIGNAME="axi_iic_0_Gpo" VECFORMULA="[(C_GPO_WIDTH-1):0]">
          <DESCRIPTION>IIC General Purpose Output</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_iic_0_Gpo_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="iic_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="2" MPD_INDEX="27" NAME="Sda" SIGNAME="axi_iic_0_Sda" TRI_I="Sda_I" TRI_O="Sda_O" TRI_T="Sda_T">
          <DESCRIPTION>IIC Serial Data</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_iic_0_Sda_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="iic_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="3" MPD_INDEX="28" NAME="Scl" SIGNAME="axi_iic_0_Scl" TRI_I="Scl_I" TRI_O="Scl_O" TRI_T="Scl_T">
          <DESCRIPTION>IIC Serial Clock</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_iic_0_Scl_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi4lite_0_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="2" NAME="IIC2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="3" MSB="8" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi4lite_0_M_AWADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi4lite_0_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi4lite_0_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi4lite_0_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi4lite_0_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi4lite_0_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi4lite_0_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi4lite_0_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi4lite_0_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi4lite_0_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="13" MSB="8" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi4lite_0_M_ARADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi4lite_0_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi4lite_0_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi4lite_0_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi4lite_0_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi4lite_0_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi4lite_0_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi4lite_0_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi4lite_0" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="iic_0" MPD_INDEX="20" NAME="Sda_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="21" NAME="Sda_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="22" NAME="Sda_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="iic_0" MPD_INDEX="23" NAME="Scl_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="24" NAME="Scl_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="25" NAME="Scl_T" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi4lite_0" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="iic_0" TYPE="XIL_AXI_IIC_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="Gpo"/>
            <PORTMAP DIR="IO" PHYSICAL="Sda"/>
            <PORTMAP DIR="IO" PHYSICAL="Scl"/>
            <PORTMAP DIR="I" PHYSICAL="Sda_I"/>
            <PORTMAP DIR="O" PHYSICAL="Sda_O"/>
            <PORTMAP DIR="O" PHYSICAL="Sda_T"/>
            <PORTMAP DIR="I" PHYSICAL="Scl_I"/>
            <PORTMAP DIR="O" PHYSICAL="Scl_O"/>
            <PORTMAP DIR="O" PHYSICAL="Scl_T"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1082130432" BASENAME="C_BASEADDR" BASEVALUE="0x40800000" HIGHDECIMAL="1082195967" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4080ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
  </MODULES>

</EDKSYSTEM>