Xilinx Design Summary

mem_to_vga Project Status (10/11/2013 - 15:06:35)
Project File: | mem_to_vga.xise | Parser Errors: | No Errors
Module Name: | mem_to_vga | Implementation State: | Synthesized

Target Device:

xc6slx16-2csg324

- Errors:

No Errors

Product Version:

ISE 14.2

- Warnings:

162 Warnings (1 new)

Design Goal:

Balanced

- Routing Results:

Design Strategy:

Xilinx Default (unlocked)

- Timing Constraints:

Environment:

System Settings

- Final Timing Score:

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slice Registers | 206 | 18224 | 1%
Number of Slice LUTs | 3000 | 9112 | 32%
Number of fully used LUT-FF pairs | 127 | 3079 | 4%
Number of bonded IOBs | 47 | 232 | 20%
Number of Block RAM/FIFO | 16 | 32 | 50%
Number of BUFG/BUFGCTRLs | 2 | 16 | 12%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | fr 11. okt 15:06:33 2013 | 0 | 162 Warnings (1 new) | 131 Infos (0 new)
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 10/11/2013 - 15:24:06