
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 14.2 Build EDK_P.28xd
# Mon Oct 14 12:59:52 2013
# Target Board:  digilent nexys3 Rev B
# Family:    spartan6
# Device:    xc6slx16
# Package:   csg324
# Speed Grade:  -3
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
 PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
 PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT Push_Buttons_4Bits_TRI_I = Push_Buttons_4Bits_TRI_I, DIR = I, VEC = [0:3]
 PORT LEDs_8Bits_TRI_O = LEDs_8Bits_TRI_O, DIR = O, VEC = [7:0]
 PORT GCLK = GCLK, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT DIP_Switches_8Bits_TRI_I = DIP_Switches_8Bits_TRI_I, DIR = I, VEC = [7:0]
 PORT mem_to_vga_0_HS_pin = mem_to_vga_0_HS, DIR = O
 PORT mem_to_vga_0_rgb_pin = mem_to_vga_0_rgb, DIR = O, VEC = [0:7]
 PORT mem_to_vga_0_VS_pin = mem_to_vga_0_VS, DIR = O
 PORT axi_iic_0_Gpo_pin = axi_iic_0_Gpo, DIR = O
 PORT axi_iic_0_Sda_pin = axi_iic_0_Sda, DIR = IO
 PORT axi_iic_0_Scl_pin = axi_iic_0_Scl, DIR = IO


BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
 PORT MB_Reset = proc_sys_reset_0_MB_Reset
 PORT Slowest_sync_clk = clk_100_0000MHz
 PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT Ext_Reset_In = RESET
 PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT Peripheral_Reset = proc_sys_reset_0_Peripheral_Reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
 PARAMETER HW_VER = 3.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = microblaze_0_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
 PARAMETER HW_VER = 3.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = microblaze_0_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
 BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 8.40.a
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 0
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0X00000000
 PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF
 PARAMETER C_USE_ICACHE = 0
 PARAMETER C_ICACHE_ALWAYS_USED = 0
 PARAMETER C_DCACHE_BASEADDR = 0X00000000
 PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF
 PARAMETER C_USE_DCACHE = 0
 PARAMETER C_DCACHE_ALWAYS_USED = 0
 PARAMETER C_FSL_LINKS = 2
 BUS_INTERFACE M_AXI_DP = axi4lite_0
 BUS_INTERFACE DEBUG = microblaze_0_debug
 BUS_INTERFACE DLMB = microblaze_0_dlmb
 BUS_INTERFACE ILMB = microblaze_0_ilmb
 BUS_INTERFACE MFSL1 = fsl_v20_1
 BUS_INTERFACE SFSL1 = fsl_v20_2
 BUS_INTERFACE MFSL0 = fsl_v20_0
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_100_0000MHz
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_UART = 1
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
 PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT S_AXI_ACLK = clk_100_0000MHz
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 100000000
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT1_FREQ = 25000000
 PORT LOCKED = proc_sys_reset_0_Dcm_locked
 PORT CLKOUT0 = clk_100_0000MHz
 PORT RST = RESET
 PORT CLKIN = GCLK
 PORT CLKOUT1 = clock_generator_0_CLKOUT1
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_0
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT interconnect_aclk = clk_100_0000MHz
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 1
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT TX = RS232_Uart_1_sout
 PORT RX = RS232_Uart_1_sin
END

BEGIN axi_gpio
 PARAMETER INSTANCE = Push_Buttons_4Bits
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT GPIO_IO_I = Push_Buttons_4Bits_TRI_I
END

BEGIN axi_gpio
 PARAMETER INSTANCE = LEDs_8Bits
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT GPIO_IO_O = LEDs_8Bits_TRI_O
END

BEGIN axi_gpio
 PARAMETER INSTANCE = DIP_Switches_8Bits
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_BASEADDR = 0x40040000
 PARAMETER C_HIGHADDR = 0x4004ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT GPIO_IO_I = DIP_Switches_8Bits_TRI_I
END

BEGIN fsl_to_axi
 PARAMETER INSTANCE = fsl_to_axi_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE SFSL = fsl_v20_1
 BUS_INTERFACE MFSL = fsl_v20_2
END

BEGIN mem_to_vga
 PARAMETER INSTANCE = mem_to_vga_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE SFSL = fsl_v20_0
 PORT HS = mem_to_vga_0_HS
 PORT rgb = mem_to_vga_0_rgb
 PORT VS = mem_to_vga_0_VS
 PORT pixel_clk = clock_generator_0_CLKOUT1
END

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl_v20_0
 PARAMETER HW_VER = 2.11.e
 PORT FSL_Clk = clk_100_0000MHz
 PORT SYS_Rst = proc_sys_reset_0_MB_Reset
END

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl_v20_1
 PARAMETER HW_VER = 2.11.e
 PORT FSL_Clk = clk_100_0000MHz
 PORT SYS_Rst = proc_sys_reset_0_MB_Reset
END

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl_v20_2
 PARAMETER HW_VER = 2.11.e
 PARAMETER C_USE_CONTROL = 0
 PARAMETER C_FSL_DEPTH = 128
 PORT FSL_Clk = clk_100_0000MHz
 PORT SYS_Rst = proc_sys_reset_0_MB_Reset
END

BEGIN axi_iic
 PARAMETER INSTANCE = axi_iic_0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_IIC_FREQ = 800000
 PARAMETER C_SCL_INERTIAL_DELAY = 4
 PARAMETER C_SDA_INERTIAL_DELAY = 4
 PARAMETER C_BASEADDR = 0x40800000
 PARAMETER C_HIGHADDR = 0x4080ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHz
 PORT Gpo = axi_iic_0_Gpo
 PORT Sda = axi_iic_0_Sda
 PORT Scl = axi_iic_0_Scl
END

