project new D:/workspace/xilinx/xps/test4/pcores/fsl_to_axi_v1_00_a/devl/projnav/fsl_to_axi.xise;
project set family spartan6;
project set device xc6slx16;
project set package csg324;
project set speed -3;
project set top_level_module_type HDL;
project set synthesis_tool "XST (VHDL/Verilog)";
lib_vhdl new fsl_to_axi_v1_00_a;
xfile add D:/workspace/xilinx/xps/test4//pcores/fsl_to_axi_v1_00_a/hdl/vhdl/fsl_to_axi.vhd -lib_vhdl fsl_to_axi_v1_00_a;
project close;
