Running: fuse.exe -relaunch -intstyle "ise" -incremental -lib "secureip" -o "C:/Temp/tupmmama/pcores/mem_to_vga_v1_00_a/devl/projnav/fsl_test_isim_beh.exe" -prj "C:/Temp/tupmmama/pcores/mem_to_vga_v1_00_a/devl/projnav/fsl_test_beh.prj" "work.fsl_test" 
ISim P.28xd (signature 0xa0883be4)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Parsing VHDL file "C:/Temp/tupmmama/pcores/mem_to_vga_v1_00_a/devl/projnav/vga_controller_640_60.vhd" into library work
Parsing VHDL file "C:/Temp/tupmmama/pcores/mem_to_vga_v1_00_a/devl/projnav/block_ram.vhd" into library work
Parsing VHDL file "C:/Temp/tupmmama/pcores/mem_to_vga_v1_00_a/devl/projnav/../../hdl/vhdl/mem_to_vga.vhd" into library work
Parsing VHDL file "C:/Temp/tupmmama/pcores/mem_to_vga_v1_00_a/devl/projnav/fsl_test.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling package textio
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package vcomponents
Compiling architecture behavioral of entity vga_controller_640_60 [vga_controller_640_60_default]
Compiling architecture behavioral of entity block_ram [block_ram_default]
Compiling architecture example of entity mem_to_vga [mem_to_vga_default]
Compiling architecture behavior of entity fsl_test
Time Resolution for simulation is 1ps.
Waiting for 3 sub-compilation(s) to finish...
Compiled 14 VHDL Units
Built simulation executable C:/Temp/tupmmama/pcores/mem_to_vga_v1_00_a/devl/projnav/fsl_test_isim_beh.exe
Fuse Memory Usage: 47864 KB
Fuse CPU Usage: 577 ms
