<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <!--                                                          -->

  <!--             For tool use only. Do not edit.              -->

  <!--                                                          -->

  <!-- ProjectNavigator created generated project file.         -->

  <!-- For use in tracking generated file and other information -->

  <!-- allowing preservation of process status.                 -->

  <!--                                                          -->

  <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->

  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>

  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="mem_to_vga.xise"/>

  <files xmlns="http://www.xilinx.com/XMLSchema">
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="fsl_test_beh.prj"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="fsl_test_isim_beh.exe"/>
    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="fsl_test_isim_beh.wdb"/>
    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="fsl_test_stx_beh.prj"/>
    <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="mem_to_vga.cmd_log"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="mem_to_vga.lso"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="mem_to_vga.ngc"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="mem_to_vga.ngr"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="mem_to_vga.prj"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="mem_to_vga.stx"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="mem_to_vga.syr"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="mem_to_vga.xst"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="mem_to_vga_envsettings.html"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="mem_to_vga_summary.html"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="mem_to_vga_xst.xrpt"/>
    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
  </files>

  <transforms xmlns="http://www.xilinx.com/XMLSchema">
    <transform xil_pn:end_ts="1381497746" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1381497746">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1381498957" xil_pn:in_ck="-939682952501149211" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1381498957">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="../../hdl/vhdl/mem_to_vga.vhd"/>
      <outfile xil_pn:name="block_ram.vhd"/>
      <outfile xil_pn:name="fsl_test.vhd"/>
      <outfile xil_pn:name="vga_controller_640_60.vhd"/>
    </transform>
    <transform xil_pn:end_ts="1381497746" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-7650075756798296220" xil_pn:start_ts="1381497746">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1381497746" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="2462226184112054050" xil_pn:start_ts="1381497746">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1381497746" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2773840779788773946" xil_pn:start_ts="1381497746">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1381498957" xil_pn:in_ck="-939682952501149211" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1381498957">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="../../hdl/vhdl/mem_to_vga.vhd"/>
      <outfile xil_pn:name="block_ram.vhd"/>
      <outfile xil_pn:name="fsl_test.vhd"/>
      <outfile xil_pn:name="vga_controller_640_60.vhd"/>
    </transform>
    <transform xil_pn:end_ts="1381498961" xil_pn:in_ck="-939682952501149211" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6488779266005630494" xil_pn:start_ts="1381498957">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="fsl_test_beh.prj"/>
      <outfile xil_pn:name="fsl_test_isim_beh.exe"/>
      <outfile xil_pn:name="fuse.log"/>
      <outfile xil_pn:name="isim"/>
      <outfile xil_pn:name="isim.log"/>
      <outfile xil_pn:name="xilinxsim.ini"/>
    </transform>
    <transform xil_pn:end_ts="1381498961" xil_pn:in_ck="5771337574892588947" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="6534759296878659233" xil_pn:start_ts="1381498961">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="fsl_test_isim_beh.wdb"/>
      <outfile xil_pn:name="isim.cmd"/>
      <outfile xil_pn:name="isim.log"/>
    </transform>
    <transform xil_pn:end_ts="1381489071" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1381489071">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1381489071" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8859069388215309464" xil_pn:start_ts="1381489071">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1381489071" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2773840779788773946" xil_pn:start_ts="1381489071">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1381489071" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1381489071">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1381489071" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1636405294508341914" xil_pn:start_ts="1381489071">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1381489071" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="1106364426758808884" xil_pn:start_ts="1381489071">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1381489071" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8241026219375691472" xil_pn:start_ts="1381489071">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1381496795" xil_pn:in_ck="-9189183127764890575" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-8846352214082187691" xil_pn:start_ts="1381496771">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForInputs"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="InputAdded"/>
      <status xil_pn:value="InputChanged"/>
      <status xil_pn:value="InputRemoved"/>
      <status xil_pn:value="OutputRemoved"/>
    </transform>
  </transforms>

</generated_project>
