Xilinx Design Summary

fsl_to_axi Project Status (10/14/2013 - 15:50:39)
Project File: | fsl_to_axi.xise | Parser Errors: | No Errors
Module Name: | fsl_to_axi | Implementation State: | Synthesized (Failed)

Target Device:

xc6slx16-2csg324

- Errors:

X 4 Errors (0 new)

Product Version:

ISE 14.6

- Warnings:

No Warnings

Design Goal:

Balanced

- Routing Results:

Design Strategy:

Xilinx Default (unlocked)

- Timing Constraints:

Environment:

System Settings

- Final Timing Score:

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Mon Oct 14 15:50:37 2013 | X 4 Errors (0 new) | 0 | 0
Translation Report | Out of Date | Sun Oct 13 18:17:10 2013 | 0 | 2 Warnings (0 new) | 0
Map Report | Out of Date | Sun Oct 13 18:16:41 2013 | 0 | 11 Warnings (0 new) | 8 Infos (1 new)
Place and Route Report | Out of Date | Sun Oct 13 18:16:57 2013 | 0 | 0 | 3 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Out of Date | Sun Oct 13 18:16:51 2013 | 0 | 0 | 4 Infos (0 new)
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 10/14/2013 - 15:50:39