Xilinx Platform Studio (XPS)
Xilinx EDK 14.2 Build EDK_P.28xd
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Assigned Driver generic 1.00.a for instance fsl_to_axi_0
fsl_to_axi_0 has been added to the project
Assigned Driver generic 1.00.a for instance mem_to_vga_0
mem_to_vga_0 has been added to the project

********************************************************************************
At Local date and time: Tue Oct 15 10:41:02 2013
 make -f system.make bits started...
"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.2 - platgen Xilinx EDK 14.2 Build EDK_P.28xd

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp

C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/ -msg __xps/ise/xmsgprops.lst

system.mhs 



WARNING:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable

   is set to '2100@vm05.cs.lth.se'.

   INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

   INFO:Security:71 - If a license for part 'xc6slx16' is available, it will be

   possible to use 'XPS_TDP' instead of 'XPS'.

   WARNING:Security:43 - No license file was found in the standard Xilinx

   license directory.

   WARNING:Security:44 - Since no license file was found,

          please run the Xilinx License Configuration Manager

          (xlcm or "Manage Xilinx Licenses")

          to assist in obtaining a license.

   WARNING:Security:42 - Your software subscription period has lapsed. Your

   current version of Xilinx tools will continue to function, but you no longer

   qualify for Xilinx software updates or new releases.





Parse H:/EDA385/BramFFT/system.mhs ...



Read MPD definitions ...



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ENDIANNESS value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 196 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ICACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 336 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 366 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_BASEFAMILY value to spartan6 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 80 



Computing clock values...

INFO:EDK:1432 - Frequency for Top-Level Input Clock 'fsl_v20_0_FSL_Clk_pin' is

   not specified. Clock DRCs will not be performed for IPs connected to that

   clock port, unless they are connected through the clock generator IP. 



INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_0:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor microblaze_0

  (0000000000-0x00007fff) microblaze_0_d_bram_ctrl	microblaze_0_dlmb

  (0000000000-0x00007fff) microblaze_0_i_bram_ctrl	microblaze_0_ilmb

  (0x40000000-0x4000ffff) Push_Buttons_4Bits	axi4lite_0

  (0x40020000-0x4002ffff) LEDs_8Bits	axi4lite_0

  (0x40040000-0x4004ffff) DIP_Switches_8Bits	axi4lite_0

  (0x40600000-0x4060ffff) RS232_Uart_1	axi4lite_0

  (0x41400000-0x4140ffff) debug_module	axi4lite_0

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block - tool is

   overriding PARAMETER C_MEMSIZE value to 0x8000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d

   ata\bram_block_v2_1_0.mpd line 77 



Checking platform address map ...



Checking platform configuration ...

IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s) 

IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 5 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_0 - 0 master(s) : 1 slave(s) 

ERROR:EDK:4119 - IPNAME: fsl_v20, INSTANCE: fsl_v20_0 - must have atleast 1

   master assigned - H:\EDA385\BramFFT\system.mhs line 208 

ERROR:EDK:440 - platgen failed with errors!

make: *** [implementation/system.bmm] Fel 2

Done!
Can't connect instance fsl_to_axi_0 bus interface SFSL to bus fsl_v20_0
MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK - MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK:3694 - Could not connect bus interface SFSL to fsl_v20_0.
Can't connect instance fsl_to_axi_0 bus interface SFSL to bus fsl_v20_0
MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK - MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK:3694 - Could not connect bus interface SFSL to fsl_v20_0.

********************************************************************************
At Local date and time: Tue Oct 15 11:03:02 2013
 make -f system.make bits started...
"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.2 - platgen Xilinx EDK 14.2 Build EDK_P.28xd

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp

C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/ -msg __xps/ise/xmsgprops.lst

system.mhs 



WARNING:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable

   is set to '2100@vm05.cs.lth.se'.

   INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

   INFO:Security:71 - If a license for part 'xc6slx16' is available, it will be

   possible to use 'XPS_TDP' instead of 'XPS'.

   WARNING:Security:43 - No license file was found in the standard Xilinx

   license directory.

   WARNING:Security:44 - Since no license file was found,

          please run the Xilinx License Configuration Manager

          (xlcm or "Manage Xilinx Licenses")

          to assist in obtaining a license.

   WARNING:Security:42 - Your software subscription period has lapsed. Your

   current version of Xilinx tools will continue to function, but you no longer

   qualify for Xilinx software updates or new releases.





Parse H:/EDA385/BramFFT/system.mhs ...



Read MPD definitions ...



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ENDIANNESS value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 196 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ICACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 336 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 366 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_BASEFAMILY value to spartan6 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 80 



Computing clock values...

INFO:EDK:1432 - Frequency for Top-Level Input Clock 'fsl_v20_0_FSL_Clk_pin' is

   not specified. Clock DRCs will not be performed for IPs connected to that

   clock port, unless they are connected through the clock generator IP. 



INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_0:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor microblaze_0

  (0000000000-0x00007fff) microblaze_0_d_bram_ctrl	microblaze_0_dlmb

  (0000000000-0x00007fff) microblaze_0_i_bram_ctrl	microblaze_0_ilmb

  (0x40000000-0x4000ffff) Push_Buttons_4Bits	axi4lite_0

  (0x40020000-0x4002ffff) LEDs_8Bits	axi4lite_0

  (0x40040000-0x4004ffff) DIP_Switches_8Bits	axi4lite_0

  (0x40600000-0x4060ffff) RS232_Uart_1	axi4lite_0

  (0x41400000-0x4140ffff) debug_module	axi4lite_0

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block - tool is

   overriding PARAMETER C_MEMSIZE value to 0x8000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d

   ata\bram_block_v2_1_0.mpd line 77 



Checking platform address map ...



Checking platform configuration ...

IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s) 

IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 5 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_0 - 1 master(s) : 1 slave(s) 



Checking port drivers...

WARNING:EDK:4180 - PORT: FSL_M_Clk, CONNECTOR: fsl_v20_0_FSL_M_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   26 

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_0_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\mem_to_vga_v1_00_a\data\mem_to_vga_v2_1_0.mpd line

   19 



Performing Clock DRCs...

INFO:EDK:4060 - INSTANCE: fsl_v20_0, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_i_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_d_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_D_AXI value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 229 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ADDR_TAG_BITS value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 334 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_ADDR_TAG value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 364 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 399 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_NM_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 400 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 148 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...



Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

INFO: Setting timing constaints for microblaze_0_ilmb.


INFO: The microblaze_0_ilmb core has constraints automatically generated by XPS

in implementation/microblaze_0_ilmb_wrapper/microblaze_0_ilmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0_dlmb.


INFO: The microblaze_0_dlmb core has constraints automatically generated by XPS

in implementation/microblaze_0_dlmb_wrapper/microblaze_0_dlmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0.


INFO: The microblaze_0 core has constraints automatically generated by XPS in

implementation/microblaze_0_wrapper/microblaze_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: No asynchronous clock conversions in axi_interconnect axi4lite_0.


INFO: The fsl_v20_0 core has constraints automatically generated by XPS in

implementation/fsl_v20_0_wrapper/fsl_v20_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.







Modify defaults ...



Creating stub ...



Processing licensed instances ...

Completion time: 0.00 seconds



Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...

IPNAME:fsl_to_axi INSTANCE:fsl_to_axi_0 - H:\EDA385\BramFFT\system.mhs line 193

- Copying (BBD-specified) netlist files.



Managing cache ...



Elaborating instances ...

IPNAME:bram_block INSTANCE:microblaze_0_bram_block -

H:\EDA385\BramFFT\system.mhs line 73 - elaborating IP

IPNAME:clock_generator INSTANCE:clock_generator_0 - H:\EDA385\BramFFT\system.mhs

line 116 - elaborating IP

ClkGen elaborate status: PASSED


----------------------------------------


----------------------------------------




Writing HDL for elaborated instances ...



Inserting wrapper level ...

Completion time: 0.00 seconds



Constructing platform-level connectivity ...

Completion time: 1.00 seconds



Writing (top-level) BMM ...



Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...



INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 

INSTANCE:proc_sys_reset_0 - H:\EDA385\BramFFT\system.mhs line 27 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_ilmb - H:\EDA385\BramFFT\system.mhs line 41 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_i_bram_ctrl - H:\EDA385\BramFFT\system.mhs line 48 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_dlmb - H:\EDA385\BramFFT\system.mhs line 57 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_d_bram_ctrl - H:\EDA385\BramFFT\system.mhs line 64 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_bram_block - H:\EDA385\BramFFT\system.mhs line 73 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0 - H:\EDA385\BramFFT\system.mhs line 80 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:debug_module - H:\EDA385\BramFFT\system.mhs line 103 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:clock_generator_0 - H:\EDA385\BramFFT\system.mhs line 116 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:axi4lite_0 - H:\EDA385\BramFFT\system.mhs line 128 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:rs232_uart_1 - H:\EDA385\BramFFT\system.mhs line 136 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:push_buttons_4bits - H:\EDA385\BramFFT\system.mhs line 151 - Running

XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:leds_8bits - H:\EDA385\BramFFT\system.mhs line 165 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:dip_switches_8bits - H:\EDA385\BramFFT\system.mhs line 179 - Running

XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_to_axi_0 - H:\EDA385\BramFFT\system.mhs line 193 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:mem_to_vga_0 - H:\EDA385\BramFFT\system.mhs line 199 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_v20_0 - H:\EDA385\BramFFT\system.mhs line 209 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Running NGCBUILD ...

IPNAME:system_microblaze_0_ilmb_wrapper INSTANCE:microblaze_0_ilmb -

H:\EDA385\BramFFT\system.mhs line 41 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_ilmb_wrapper.ngc

../system_microblaze_0_ilmb_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/microblaze_0_ilmb_wrapper/system_microblaze_0_

ilmb_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_ilmb_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_ilmb_wrapper.blc"...



NGCBUILD done.

IPNAME:system_microblaze_0_dlmb_wrapper INSTANCE:microblaze_0_dlmb -

H:\EDA385\BramFFT\system.mhs line 57 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_dlmb_wrapper.ngc

../system_microblaze_0_dlmb_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/microblaze_0_dlmb_wrapper/system_microblaze_0_

dlmb_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_dlmb_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_dlmb_wrapper.blc"...



NGCBUILD done.

IPNAME:system_microblaze_0_wrapper INSTANCE:microblaze_0 -

H:\EDA385\BramFFT\system.mhs line 80 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_wrapper.ngc

../system_microblaze_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/microblaze_0_wrapper/system_microblaze_0_wrapp

er.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  3 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -

H:\EDA385\BramFFT\system.mhs line 116 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc

../system_clock_generator_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/clock_generator_0_wrapper/system_clock_generat

or_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi4lite_0_wrapper INSTANCE:axi4lite_0 -

H:\EDA385\BramFFT\system.mhs line 128 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_axi4lite_0_wrapper.ngc

../system_axi4lite_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/axi4lite_0_wrapper/system_axi4lite_0_wrapper.n

gc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi4lite_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_axi4lite_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_to_axi_0_wrapper INSTANCE:fsl_to_axi_0 -

H:\EDA385\BramFFT\system.mhs line 193 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_to_axi_0_wrapper.ngc

../system_fsl_to_axi_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/fsl_to_axi_0_wrapper/system_fsl_to_axi_0_wrapp

er.ngc" ...

Loading design module

"H:\EDA385\BramFFT\implementation\fsl_to_axi_0_wrapper/xfft_v8_0.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_to_axi_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  3 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_to_axi_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_v20_0_wrapper INSTANCE:fsl_v20_0 -

H:\EDA385\BramFFT\system.mhs line 209 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_v20_0_wrapper.ngc

../system_fsl_v20_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/fsl_v20_0_wrapper/system_fsl_v20_0_wrapper.ngc

" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_v20_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_v20_0_wrapper.blc"...



NGCBUILD done.

INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

   If any constraint needs to be overridden, this should be done by modifying

   the data/system.ucf file.



Rebuilding cache ...



Total run time: 300.00 seconds

"Running synthesis..."

cd synthesis & synthesis.cmd

"xst -ifn "system_xst.scr" -intstyle silent"

"Running XST synthesis ..."

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

"XST completed"

"*********************************************"

"Running Xilinx Implementation tools.."

"*********************************************"

xflow -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

Release 14.2 - Xflow P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

 

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

.... Copying flowfile C:/Xilinx/14.2/ISE_DS/ISE/xilinx/data/fpga.flw into

working directory H:/EDA385/BramFFT/implementation 



Using Flow File: H:/EDA385/BramFFT/implementation/fpga.flw 

Using Option File(s): 

 H:/EDA385/BramFFT/implementation/xflow.opt 



Creating Script File ... 



#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc6slx16csg324-3 -nt timestamp -bm system.bmm

"H:/EDA385/BramFFT/implementation/system.ngc" -uc system.ucf system.ngd 

#----------------------------------------------#

Release 14.2 - ngdbuild P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>





Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p


xc6slx16csg324-3 -nt timestamp -bm system.bmm


H:/EDA385/BramFFT/implementation/system.ngc -uc system.ucf system.ngd





Reading NGO file "H:/EDA385/BramFFT/implementation/system.ngc" ...


Loading design module


"H:/EDA385/BramFFT/implementation/system_push_buttons_4bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_dip_switches_8bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_rs232_uart_1_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_proc_sys_reset_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_clock_generator_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_to_axi_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_mem_to_vga_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_v20_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_axi4lite_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_i_bram_ctrl_wrapper.ngc"..


.


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_d_bram_ctrl_wrapper.ngc"..


.


Loading design module


"H:/EDA385/BramFFT/implementation/system_debug_module_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_leds_8bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_bram_block_wrapper.ngc"...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ncf" to


module "microblaze_0_ilmb"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ncf" to


module "microblaze_0_dlmb"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_axi4lite_0_wrapper.ncf" to module


"axi4lite_0"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_wrapper.ncf" to module


"microblaze_0"...


Checking Constraint Associations...


Gathering constraint information from source properties...


Done.





Annotating constraints to design from ucf file "system.ucf" ...


Resolving constraint associations...


Checking Constraint Associations...


WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi4lite_0/axi4lite_0\/si_converter_bank\/gen_conv_sl


   ot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_INV_0 TNM =


   FFS:axi4lite_0_reset_resync>: No instances of type FFS were found under block


   "axi4lite_0/axi4lite_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/int

erconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP axi4lite_0_reset_source = FFS


   PADS CPUS;>: CPUS "*" does not match any design objects.





WARNING:ConstraintSystem:194 - The TNM 'axi4lite_0_reset_resync', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification


   'TS_sys_clk_pin', was traced into PLL_ADV instance


   clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM


   groups and period specifications were generated at the PLL_ADV output(s): 


   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0" TS_sys_clk_pin


   HIGH 50>





Done...





Processing BMM file "system.bmm" ...





Checking expanded design ...


WARNING:NgdBuild:443 - SFF primitive


   'microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Decode_I/Using_FPGA.


   Gen_Bits[27].MEM_EX_Result_Inst' has unconnected output pin


WARNING:NgdBuild:452 - logical net 'fsl_v20_0_FSL_M_Control' has no driver


WARNING:NgdBuild:452 - logical net


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/sig00000368' has no


   driver


WARNING:NgdBuild:452 - logical net


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/sig00000581' has no


   driver





Partition Implementation Status


-------------------------------





  No Partitions were found in this design.





-------------------------------





NGDBUILD Design Results Summary:


  Number of errors:     0


  Number of warnings:   7





Writing NGD file "system.ngd" ...


Total REAL time to NGDBUILD completion:  47 sec


Total CPU time to NGDBUILD completion:   43 sec





Writing NGDBUILD log file "system.bld"...





NGDBUILD done.








#----------------------------------------------#

# Starting program map

# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf 

#----------------------------------------------#

Release 14.2 - Map P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>


Using target part "6slx16csg324-3".


vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv


INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to


'2100@vm05.cs.lth.se'.


INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.


INFO:Security:54 - 'xc6slx16' is a WebPack part.


WARNING:Security:43 - No license file was found in the standard Xilinx license


directory.


WARNING:Security:44 - Since no license file was found,


       please run the Xilinx License Configuration Manager


       (xlcm or "Manage Xilinx Licenses")


       to assist in obtaining a license.


WARNING:Security:42 - Your software subscription period has lapsed. Your current


version of Xilinx tools will continue to function, but you no longer qualify for


Xilinx software updates or new releases.


----------------------------------------------------------------------


Mapping design into LUTs...


Writing file system_map.ngm...


Running directed packing...


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e0

e" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig00001395


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000071). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e5

0" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013b3


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000080). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e1

0" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig00001396


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000072). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e1

5" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig00001397


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000073). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e1

7" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig00001398


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000074). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e5

f" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013b9


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000083). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e6

1" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013ba


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000084). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e7

0" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013c2


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000086). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000ea

a" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013f8


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm0000008b). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e4

e" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013b2


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm0000007f). The constraint will be ignored.


Running delay-based LUT packing...


Updating timing models...


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report


   (.mrp).


Running timing-driven placement...


Total REAL time at the beginning of Placer: 17 secs 


Total CPU  time at the beginning of Placer: 13 secs 





Phase 1.1  Initial Placement Analysis


Phase 1.1  Initial Placement Analysis (Checksum:4d9e6944) REAL time: 19 secs 





Phase 2.7  Design Feasibility Check


INFO:Place:834 - Only a subset of IOs are locked. Out of 35 IOs, 24 are locked


   and 11 are not locked. If you would like to print the names of these IOs,


   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 


Phase 2.7  Design Feasibility Check (Checksum:4d9e6944) REAL time: 19 secs 





Phase 3.31  Local Placement Optimization


Phase 3.31  Local Placement Optimization (Checksum:df6c215c) REAL time: 19 secs 





Phase 4.2  Initial Placement for Architecture Specific Features


....


Phase 4.2  Initial Placement for Architecture Specific Features


(Checksum:3e9fa465) REAL time: 22 secs 





Phase 5.36  Local Placement Optimization


Phase 5.36  Local Placement Optimization (Checksum:3e9fa465) REAL time: 22 secs 





Phase 6.30  Global Clock Region Assignment


Phase 6.30  Global Clock Region Assignment (Checksum:3e9fa465) REAL time: 22 secs 





Phase 7.3  Local Placement Optimization


....


Phase 7.3  Local Placement Optimization (Checksum:dc6602ec) REAL time: 23 secs 





Phase 8.5  Local Placement Optimization


Phase 8.5  Local Placement Optimization (Checksum:5140aaf8) REAL time: 23 secs 





Phase 9.8  Global Placement


....................


.....................................................


.........................................................................................................................................................................


..............................................................................................................................................................................................................


......................................................................


Phase 9.8  Global Placement (Checksum:caca80ce) REAL time: 44 secs 





Phase 10.5  Local Placement Optimization


Phase 10.5  Local Placement Optimization (Checksum:caca80ce) REAL time: 44 secs 





Phase 11.18  Placement Optimization


Phase 11.18  Placement Optimization (Checksum:c4230497) REAL time: 49 secs 





Phase 12.5  Local Placement Optimization


Phase 12.5  Local Placement Optimization (Checksum:c4230497) REAL time: 49 secs 





Phase 13.34  Placement Validation


Phase 13.34  Placement Validation (Checksum:f8d2f294) REAL time: 50 secs 





Total REAL time to Placer completion: 50 secs 


Total CPU  time to Placer completion: 44 secs 


Running post-placement packing...


Writing output files...





Design Summary:


Number of errors:      0


Number of warnings:   29


Slice Logic Utilization:


  Number of Slice Registers:                 3,431 out of  18,224   18


    Number used as Flip Flops:               3,424


    Number used as Latches:                      0


    Number used as Latch-thrus:                  0


    Number used as AND/OR logics:                7


  Number of Slice LUTs:                      4,898 out of   9,112   53


    Number used as logic:                    3,410 out of   9,112   37


      Number using O6 output only:           2,611


      Number using O5 output only:              67


      Number using O5 and O6:                  732


      Number used as ROM:                        0


    Number used as Memory:                   1,406 out of   2,176   64


      Number used as Dual Port RAM:             64


        Number using O6 output only:             0


        Number using O5 output only:             0


        Number using O5 and O6:                 64


      Number used as Single Port RAM:        1,024


        Number using O6 output only:         1,024


        Number using O5 output only:             0


        Number using O5 and O6:                  0


      Number used as Shift Register:           318


        Number using O6 output only:            46


        Number using O5 output only:             1


        Number using O5 and O6:                271


    Number used exclusively as route-thrus:     82


      Number with same-slice register load:     69


      Number with same-slice carry load:        13


      Number with other load:                    0





Slice Logic Distribution:


  Number of occupied Slices:                 1,879 out of   2,278   82


  Nummber of MUXCYs used:                      952 out of   4,556   20


  Number of LUT Flip Flop pairs used:        5,608


    Number with an unused Flip Flop:         2,691 out of   5,608   47


    Number with an unused LUT:                 710 out of   5,608   12


    Number of fully used LUT-FF pairs:       2,207 out of   5,608   39


    Number of unique control sets:             275


    Number of slice register sites lost


      to control set restrictions:             595 out of  18,224    3





  A LUT Flip Flop pair for this architecture represents one LUT paired with


  one Flip Flop within a slice.  A control set is a unique combination of


  clock, reset, set, and enable signals for a registered element.


  The Slice Logic Distribution report is not meaningful if the design is


  over-mapped for a non-slice resource or if Placement fails.





IO Utilization:


  Number of bonded IOBs:                        35 out of     232   15


    Number of LOCed IOBs:                       24 out of      35   68


    IOB Flip Flops:                              4





Specific Feature Utilization:


  Number of RAMB16BWERs:                        16 out of      32   50


  Number of RAMB8BWERs:                          7 out of      64   10


  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3


    Number used as BUFIO2s:                      1


    Number used as BUFIO2_2CLKs:                 0


  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0


  Number of BUFG/BUFGMUXs:                       3 out of      16   18


    Number used as BUFGs:                        3


    Number used as BUFGMUX:                      0


  Number of DCM/DCM_CLKGENs:                     0 out of       4    0


  Number of ILOGIC2/ISERDES2s:                   1 out of     248    1


    Number used as ILOGIC2s:                     1


    Number used as ISERDES2s:                    0


  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0


  Number of OLOGIC2/OSERDES2s:                   3 out of     248    1


    Number used as OLOGIC2s:                     3


    Number used as OSERDES2s:                    0


  Number of BSCANs:                              1 out of       4   25


  Number of BUFHs:                               0 out of     128    0


  Number of BUFPLLs:                             0 out of       8    0


  Number of BUFPLL_MCBs:                         0 out of       4    0


  Number of DSP48A1s:                           12 out of      32   37


  Number of ICAPs:                               0 out of       1    0


  Number of MCBs:                                0 out of       2    0


  Number of PCILOGICSEs:                         0 out of       2    0


  Number of PLL_ADVs:                            1 out of       2   50


  Number of PMVs:                                0 out of       1    0


  Number of STARTUPs:                            0 out of       1    0


  Number of SUSPEND_SYNCs:                       0 out of       1    0





Average Fanout of Non-Clock Nets:                4.66





Peak Memory Usage:  499 MB


Total REAL time to MAP completion:  54 secs 


Total CPU time to MAP completion:   48 secs 





Mapping completed.


See MAP report file "system_map.mrp" for details.








#----------------------------------------------#

# Starting program par

# par -w -ol high system_map.ncd system.ncd system.pcf 

#----------------------------------------------#

Release 14.2 - par P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <C:/Xilinx/14.2/ISE_DS/EDK/data/parBmgr.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/data/parBmgr.acd>







Constraints file: system.pcf.

Loading device for application Rf_Device from file '6slx16.nph' in environment

C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv

INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to '2100@vm05.cs.lth.se'.

INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

INFO:Security:54 - 'xc6slx16' is a WebPack part.

WARNING:Security:43 - No license file was found in the standard Xilinx license directory.

WARNING:Security:44 - Since no license file was found,

       please run the Xilinx License Configuration Manager

       (xlcm or "Manage Xilinx Licenses")

       to assist in obtaining a license.

WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue

to function, but you no longer qualify for Xilinx software updates or new releases.



----------------------------------------------------------------------



Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)





Device speed data version:  "PRODUCTION 1.22 2012-07-09".







Device Utilization Summary:



Slice Logic Utilization:

  Number of Slice Registers:                 3,431 out of  18,224   18

    Number used as Flip Flops:               3,424

    Number used as Latches:                      0

    Number used as Latch-thrus:                  0

    Number used as AND/OR logics:                7

  Number of Slice LUTs:                      4,898 out of   9,112   53

    Number used as logic:                    3,410 out of   9,112   37

      Number using O6 output only:           2,611

      Number using O5 output only:              67

      Number using O5 and O6:                  732

      Number used as ROM:                        0

    Number used as Memory:                   1,406 out of   2,176   64

      Number used as Dual Port RAM:             64

        Number using O6 output only:             0

        Number using O5 output only:             0

        Number using O5 and O6:                 64

      Number used as Single Port RAM:        1,024

        Number using O6 output only:         1,024

        Number using O5 output only:             0

        Number using O5 and O6:                  0

      Number used as Shift Register:           318

        Number using O6 output only:            46

        Number using O5 output only:             1

        Number using O5 and O6:                271

    Number used exclusively as route-thrus:     82

      Number with same-slice register load:     69

      Number with same-slice carry load:        13

      Number with other load:                    0



Slice Logic Distribution:

  Number of occupied Slices:                 1,879 out of   2,278   82

  Nummber of MUXCYs used:                      952 out of   4,556   20

  Number of LUT Flip Flop pairs used:        5,608

    Number with an unused Flip Flop:         2,691 out of   5,608   47

    Number with an unused LUT:                 710 out of   5,608   12

    Number of fully used LUT-FF pairs:       2,207 out of   5,608   39

    Number of slice register sites lost

      to control set restrictions:               0 out of  18,224    0



  A LUT Flip Flop pair for this architecture represents one LUT paired with

  one Flip Flop within a slice.  A control set is a unique combination of

  clock, reset, set, and enable signals for a registered element.

  The Slice Logic Distribution report is not meaningful if the design is

  over-mapped for a non-slice resource or if Placement fails.



IO Utilization:

  Number of bonded IOBs:                        35 out of     232   15

    Number of LOCed IOBs:                       24 out of      35   68

    IOB Flip Flops:                              4



Specific Feature Utilization:

  Number of RAMB16BWERs:                        16 out of      32   50

  Number of RAMB8BWERs:                          7 out of      64   10

  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3

    Number used as BUFIO2s:                      1

    Number used as BUFIO2_2CLKs:                 0

  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0

  Number of BUFG/BUFGMUXs:                       3 out of      16   18

    Number used as BUFGs:                        3

    Number used as BUFGMUX:                      0

  Number of DCM/DCM_CLKGENs:                     0 out of       4    0

  Number of ILOGIC2/ISERDES2s:                   1 out of     248    1

    Number used as ILOGIC2s:                     1

    Number used as ISERDES2s:                    0

  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0

  Number of OLOGIC2/OSERDES2s:                   3 out of     248    1

    Number used as OLOGIC2s:                     3

    Number used as OSERDES2s:                    0

  Number of BSCANs:                              1 out of       4   25

  Number of BUFHs:                               0 out of     128    0

  Number of BUFPLLs:                             0 out of       8    0

  Number of BUFPLL_MCBs:                         0 out of       4    0

  Number of DSP48A1s:                           12 out of      32   37

  Number of ICAPs:                               0 out of       1    0

  Number of MCBs:                                0 out of       2    0

  Number of PCILOGICSEs:                         0 out of       2    0

  Number of PLL_ADVs:                            1 out of       2   50

  Number of PMVs:                                0 out of       1    0

  Number of STARTUPs:                            0 out of       1    0

  Number of SUSPEND_SYNCs:                       0 out of       1    0





Overall effort level (-ol):   High 

Router effort level (-rl):    High 



INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx

   Command Line Tools User Guide for information on generating a TSI report.

Starting initial Timing Analysis.  REAL time: 7 secs 

Finished initial Timing Analysis.  REAL time: 7 secs 



WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<31> has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<30> has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

Starting Router





Phase  1  : 35428 unrouted;      REAL time: 7 secs 



Phase  2  : 29581 unrouted;      REAL time: 8 secs 



Phase  3  : 11541 unrouted;      REAL time: 29 secs 



Phase  4  : 11541 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 29 secs 



Updating file: system.ncd with current fully routed design.



Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 



Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 



Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 



Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 



Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 



Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 45 secs 

Total REAL time to Router completion: 45 secs 

Total CPU time to Router completion: 43 secs 



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



Generating "PAR" statistics.



**************************

Generating Clock Report

**************************



+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|     clk_100_0000MHz |  BUFGMUX_X2Y3| No   |  704 |  0.547     |  1.394      |

+---------------------+--------------+------+------+------------+-------------+

|microblaze_0_debug_D |              |      |      |            |             |

|              bg_Clk |  BUFGMUX_X2Y2| No   |   61 |  0.064     |  0.911      |

+---------------------+--------------+------+------+------------+-------------+

|fsl_v20_0_FSL_Clk_pi |              |      |      |            |             |

|             n_BUFGP | BUFGMUX_X3Y13| No   |  873 |  0.067     |  0.913      |

+---------------------+--------------+------+------+------------+-------------+

|microblaze_0_debug_D |              |      |      |            |             |

|           bg_Update |         Local|      |   20 |  3.572     |  4.631      |

+---------------------+--------------+------+------+------------+-------------+



* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.



* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.



Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Number of Timing Constraints that were not applied: 1



Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.



----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   

                                            |             |    Slack   | Achievable | Errors |    Score   

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |     0.344ns|     9.656ns|       0|           0

  G_PLL0_CLKOUT0 = PERIOD TIMEGRP         " | HOLD        |     0.286ns|            |       0|           0

  clock_generator_0_clock_generator_0_SIG_P |             |            |            |        |            

  LL0_CLKOUT0" TS_sys_clk_pin         HIGH  |             |            |            |        |            

  50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.666ns|     3.334ns|       0|           0

  pin" 100 MHz HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_Reset_path" TIG | SETUP       |         N/A|     4.142ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi4lite_0_reset_resync_path" TI | MAXDELAY    |         N/A|     4.574ns|     N/A|           0

  G                                         |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_dlmb_POR_FF_I_p | SETUP       |         N/A|     1.654ns|     N/A|           0

  ath" TIG                                  |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_ilmb_POR_FF_I_p | SETUP       |         N/A|     1.343ns|     N/A|           0

  ath" TIG                                  |             |            |            |        |            

----------------------------------------------------------------------------------------------------------





Derived Constraint Report

Review Timing Report for more details on the following derived constraints.

To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"

or "Run Timing Analysis" from Timing Analyzer (timingan).

Derived Constraints for TS_sys_clk_pin

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |

|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|

|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|TS_sys_clk_pin                 |     10.000ns|      3.334ns|      9.656ns|            0|            0|            0|       254642|

| TS_clock_generator_0_clock_gen|     10.000ns|      9.656ns|          N/A|            0|            0|       254642|            0|

| erator_0_SIG_PLL0_CLKOUT0     |             |             |             |             |             |             |             |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+



All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 

   constraint is not analyzed due to the following: No paths covered by this 

   constraint; Other constraints intersect with this constraint; or This 

   constraint was disabled by a Path Tracing Control. Please run the Timespec 

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.





Generating Pad Report.



All signals are completely routed.



WARNING:Par:283 - There are 18 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.



Total REAL time to PAR completion: 55 secs 

Total CPU time to PAR completion: 46 secs 



Peak Memory Usage:  441 MB



Placer: Placement generated during map.

Routing: Completed - No errors found.

Timing: Completed - No errors found.



Number of error messages: 0

Number of warning messages: 20

Number of info messages: 1



Writing design to file system.ncd







PAR done!







#----------------------------------------------#

# Starting program post_par_trce

# trce -e 3 -xml system.twx system.ncd system.pcf 

#----------------------------------------------#

Release 14.2 - Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.








PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>


Loading device for application Rf_Device from file '6slx16.nph' in environment


C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.


   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3


INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more


   information, see the TSI report.  Please consult the Xilinx Command Line


   Tools User Guide for information on generating a TSI report.


--------------------------------------------------------------------------------


Release 14.2 Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -e 3 -xml system.twx


system.ncd system.pcf








Design file:              system.ncd


Physical constraint file: system.pcf


Device,speed:             xc6slx16,-3 (PRODUCTION 1.22 2012-07-09)


Report level:             error report


--------------------------------------------------------------------------------





INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).


INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in


   the unconstrained paths section(s) of the report.


INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of


   this model, and for more information on accounting for different loading conditions, please see the device datasheet.








Timing summary:


---------------





Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)





Constraints cover 254655 paths, 0 nets, and 11128 connections





Design statistics:


   Minimum period:   9.656ns (Maximum frequency: 103.563MHz)








Analysis completed Tue Oct 15 11:11:28 2013


--------------------------------------------------------------------------------





Generating Report ...





Number of warnings: 0


Number of info messages: 4


Total time: 7 secs 






xflow done!

touch __xps/system_routed

xilperl C:/Xilinx/14.2/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par

"*********************************************"

"Running Bitgen.."

"*********************************************"

cd implementation & bitgen -w -f bitgen.ut system & cd ..

Release 14.2 - Bitgen P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

Loading device for application Rf_Device from file '6slx16.nph' in environment

C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3

Opened constraints file system.pcf.



Tue Oct 15 11:11:34 2013



INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER). 

   9K Block RAM initialization data, both user defined and default, requires a

   special bit stream format.  For more information, please reference Xilinx

   Answer Record 39999.

Running DRC.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<31>> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<30>> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs

   (RAMB8BWER).  9K Block RAM initialization data, both user defined and

   default, may be incorrect and should not be used.  For more information,

   please reference Xilinx Answer Record 39999.

DRC detected 0 errors and 19 warnings.  Please see the previously displayed

individual error or warning messages for more details.

INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to

'2100@vm05.cs.lth.se'.

INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

INFO:Security:54 - 'xc6slx16' is a WebPack part.

WARNING:Security:43 - No license file was found in the standard Xilinx license

directory.

WARNING:Security:44 - Since no license file was found,

       please run the Xilinx License Configuration Manager

       (xlcm or "Manage Xilinx Licenses")

       to assist in obtaining a license.

WARNING:Security:42 - Your software subscription period has lapsed. Your current

version of Xilinx tools will continue to function, but you no longer qualify for

Xilinx software updates or new releases.



Creating bit map...

Saving bit stream in "system.bit".

Bitstream generation is complete.

Done!
Can't connect instance fsl_to_axi_0 bus interface SFSL to bus fsl_v20_0
MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK - MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK:3694 - Could not connect bus interface SFSL to fsl_v20_0.
Can't connect instance fsl_to_axi_0 bus interface SFSL to bus fsl_v20_0
MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK - MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK:3694 - Could not connect bus interface SFSL to fsl_v20_0.
Can't connect instance fsl_to_axi_0 bus interface SFSL to bus fsl_v20_0
MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK - MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK:3694 - Could not connect bus interface SFSL to fsl_v20_0.
Can't connect instance fsl_to_axi_0 bus interface SFSL to bus fsl_v20_0
MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK - MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK:3694 - Could not connect bus interface SFSL to fsl_v20_0.
Can't connect instance fsl_to_axi_0 bus interface SFSL to bus fsl_v20_0
MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK - MAX_SLAVES exceeded for bus instance fsl_v20_0, because there are already 1 slave instances are connected to fsl_v20_0
ERROR:EDK:3694 - Could not connect bus interface SFSL to fsl_v20_0.
fsl_v20_1 has been deleted from the project
Save project successfully
Writing filter settings....
Done writing filter settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.filters
Done writing Tab View settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.2 Build EDK_P.28xd
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Overriding Xilinx file <TextEditor.cfg> with local file <C:/Xilinx/14.2/ISE_DS/EDK/data/TextEditor.cfg>

********************************************************************************
At Local date and time: Tue Oct 15 13:25:03 2013
 make -f system.make bits started...
"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.2 - platgen Xilinx EDK 14.2 Build EDK_P.28xd

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp

C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/ -msg __xps/ise/xmsgprops.lst

system.mhs 



WARNING:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable

   is set to '2100@vm05.cs.lth.se'.

   INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

   INFO:Security:71 - If a license for part 'xc6slx16' is available, it will be

   possible to use 'XPS_TDP' instead of 'XPS'.

   WARNING:Security:43 - No license file was found in the standard Xilinx

   license directory.

   WARNING:Security:44 - Since no license file was found,

          please run the Xilinx License Configuration Manager

          (xlcm or "Manage Xilinx Licenses")

          to assist in obtaining a license.

   WARNING:Security:42 - Your software subscription period has lapsed. Your

   current version of Xilinx tools will continue to function, but you no longer

   qualify for Xilinx software updates or new releases.





Parse H:/EDA385/BramFFT/system.mhs ...



Read MPD definitions ...



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ENDIANNESS value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 196 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ICACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 336 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 366 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_BASEFAMILY value to spartan6 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 80 



Computing clock values...

INFO:EDK:1432 - Frequency for Top-Level Input Clock 'fsl_v20_0_FSL_Clk_pin' is

   not specified. Clock DRCs will not be performed for IPs connected to that

   clock port, unless they are connected through the clock generator IP. 



INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_0:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor microblaze_0

  (0000000000-0x00007fff) microblaze_0_d_bram_ctrl	microblaze_0_dlmb

  (0000000000-0x00007fff) microblaze_0_i_bram_ctrl	microblaze_0_ilmb

  (0x40000000-0x4000ffff) Push_Buttons_4Bits	axi4lite_0

  (0x40020000-0x4002ffff) LEDs_8Bits	axi4lite_0

  (0x40040000-0x4004ffff) DIP_Switches_8Bits	axi4lite_0

  (0x40600000-0x4060ffff) RS232_Uart_1	axi4lite_0

  (0x41400000-0x4140ffff) debug_module	axi4lite_0

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block - tool is

   overriding PARAMETER C_MEMSIZE value to 0x8000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d

   ata\bram_block_v2_1_0.mpd line 77 



Checking platform address map ...



Checking platform configuration ...

IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s) 

IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 5 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_0 - 1 master(s) : 1 slave(s) 



Checking port drivers...

WARNING:EDK:4180 - PORT: FSL_M_Clk, CONNECTOR: fsl_v20_0_FSL_M_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   26 

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_0_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\mem_to_vga_v1_00_a\data\mem_to_vga_v2_1_0.mpd line

   20 



Performing Clock DRCs...

INFO:EDK:4060 - INSTANCE: fsl_v20_0, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_i_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_d_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_D_AXI value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 229 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ADDR_TAG_BITS value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 334 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_ADDR_TAG value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 364 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 399 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_NM_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 400 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 148 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...



Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

INFO: Setting timing constaints for microblaze_0_ilmb.


INFO: The microblaze_0_ilmb core has constraints automatically generated by XPS

in implementation/microblaze_0_ilmb_wrapper/microblaze_0_ilmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0_dlmb.


INFO: The microblaze_0_dlmb core has constraints automatically generated by XPS

in implementation/microblaze_0_dlmb_wrapper/microblaze_0_dlmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0.


INFO: The microblaze_0 core has constraints automatically generated by XPS in

implementation/microblaze_0_wrapper/microblaze_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: No asynchronous clock conversions in axi_interconnect axi4lite_0.


INFO: The fsl_v20_0 core has constraints automatically generated by XPS in

implementation/fsl_v20_0_wrapper/fsl_v20_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.







Modify defaults ...



Creating stub ...



Processing licensed instances ...

Completion time: 0.00 seconds



Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...

IPNAME:fsl_to_axi INSTANCE:fsl_to_axi_0 - H:\EDA385\BramFFT\system.mhs line 193

- Copying (BBD-specified) netlist files.

IPNAME:mem_to_vga INSTANCE:mem_to_vga_0 - H:\EDA385\BramFFT\system.mhs line 199

- Copying (BBD-specified) netlist files.



Managing cache ...

IPNAME:proc_sys_reset INSTANCE:proc_sys_reset_0 - H:\EDA385\BramFFT\system.mhs

line 27 - Copying cache implementation netlist

IPNAME:lmb_v10 INSTANCE:microblaze_0_ilmb - H:\EDA385\BramFFT\system.mhs line 41

- Copying cache implementation netlist

IPNAME:lmb_bram_if_cntlr INSTANCE:microblaze_0_i_bram_ctrl -

H:\EDA385\BramFFT\system.mhs line 48 - Copying cache implementation netlist

IPNAME:lmb_v10 INSTANCE:microblaze_0_dlmb - H:\EDA385\BramFFT\system.mhs line 57

- Copying cache implementation netlist

IPNAME:lmb_bram_if_cntlr INSTANCE:microblaze_0_d_bram_ctrl -

H:\EDA385\BramFFT\system.mhs line 64 - Copying cache implementation netlist

IPNAME:bram_block INSTANCE:microblaze_0_bram_block -

H:\EDA385\BramFFT\system.mhs line 73 - Copying cache implementation netlist

IPNAME:microblaze INSTANCE:microblaze_0 - H:\EDA385\BramFFT\system.mhs line 80 -

Copying cache implementation netlist

IPNAME:mdm INSTANCE:debug_module - H:\EDA385\BramFFT\system.mhs line 103 -

Copying cache implementation netlist

IPNAME:axi_interconnect INSTANCE:axi4lite_0 - H:\EDA385\BramFFT\system.mhs line

128 - Copying cache implementation netlist

IPNAME:axi_uartlite INSTANCE:rs232_uart_1 - H:\EDA385\BramFFT\system.mhs line

136 - Copying cache implementation netlist

IPNAME:axi_gpio INSTANCE:push_buttons_4bits - H:\EDA385\BramFFT\system.mhs line

151 - Copying cache implementation netlist

IPNAME:axi_gpio INSTANCE:leds_8bits - H:\EDA385\BramFFT\system.mhs line 165 -

Copying cache implementation netlist

IPNAME:axi_gpio INSTANCE:dip_switches_8bits - H:\EDA385\BramFFT\system.mhs line

179 - Copying cache implementation netlist

IPNAME:fsl_to_axi INSTANCE:fsl_to_axi_0 - H:\EDA385\BramFFT\system.mhs line 193

- Copying cache implementation netlist

IPNAME:mem_to_vga INSTANCE:mem_to_vga_0 - H:\EDA385\BramFFT\system.mhs line 199

- Copying cache implementation netlist

IPNAME:fsl_v20 INSTANCE:fsl_v20_0 - H:\EDA385\BramFFT\system.mhs line 209 -

Copying cache implementation netlist



Elaborating instances ...

IPNAME:bram_block INSTANCE:microblaze_0_bram_block -

H:\EDA385\BramFFT\system.mhs line 73 - elaborating IP

IPNAME:clock_generator INSTANCE:clock_generator_0 - H:\EDA385\BramFFT\system.mhs

line 116 - elaborating IP

ClkGen elaborate status: PASSED


----------------------------------------


----------------------------------------




Writing HDL for elaborated instances ...



Inserting wrapper level ...

Completion time: 1.00 seconds



Constructing platform-level connectivity ...

Completion time: 0.00 seconds



Writing (top-level) BMM ...



Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...



INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 

INSTANCE:clock_generator_0 - H:\EDA385\BramFFT\system.mhs line 116 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Running NGCBUILD ...

IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -

H:\EDA385\BramFFT\system.mhs line 116 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc

../system_clock_generator_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/clock_generator_0_wrapper/system_clock_generat

or_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...



NGCBUILD done.

INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

   If any constraint needs to be overridden, this should be done by modifying

   the data/system.ucf file.



Rebuilding cache ...



Total run time: 27.00 seconds

"Running synthesis..."

cd synthesis & synthesis.cmd

"xst -ifn "system_xst.scr" -intstyle silent"

"Running XST synthesis ..."

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

"XST completed"

"*********************************************"

"Running Xilinx Implementation tools.."

"*********************************************"

xflow -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

Release 14.2 - Xflow P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

 

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Using Flow File: H:/EDA385/BramFFT/implementation/fpga.flw 

Using Option File(s): 

 H:/EDA385/BramFFT/implementation/xflow.opt 



Creating Script File ... 



#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc6slx16csg324-3 -nt timestamp -bm system.bmm

"H:/EDA385/BramFFT/implementation/system.ngc" -uc system.ucf system.ngd 

#----------------------------------------------#

Release 14.2 - ngdbuild P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>





Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p


xc6slx16csg324-3 -nt timestamp -bm system.bmm


H:/EDA385/BramFFT/implementation/system.ngc -uc system.ucf system.ngd





Reading NGO file "H:/EDA385/BramFFT/implementation/system.ngc" ...


Loading design module


"H:/EDA385/BramFFT/implementation/system_push_buttons_4bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_dip_switches_8bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_rs232_uart_1_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_proc_sys_reset_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_clock_generator_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_to_axi_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_mem_to_vga_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_v20_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_axi4lite_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_i_bram_ctrl_wrapper.ngc"..


.


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_d_bram_ctrl_wrapper.ngc"..


.


Loading design module


"H:/EDA385/BramFFT/implementation/system_debug_module_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_leds_8bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_bram_block_wrapper.ngc"...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ncf" to


module "microblaze_0_ilmb"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ncf" to


module "microblaze_0_dlmb"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_axi4lite_0_wrapper.ncf" to module


"axi4lite_0"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_wrapper.ncf" to module


"microblaze_0"...


Checking Constraint Associations...


Gathering constraint information from source properties...


Done.





Annotating constraints to design from ucf file "system.ucf" ...


Resolving constraint associations...


Checking Constraint Associations...


WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi4lite_0/axi4lite_0\/si_converter_bank\/gen_conv_sl


   ot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_INV_0 TNM =


   FFS:axi4lite_0_reset_resync>: No instances of type FFS were found under block


   "axi4lite_0/axi4lite_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/int

erconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP axi4lite_0_reset_source = FFS


   PADS CPUS;>: CPUS "*" does not match any design objects.





WARNING:ConstraintSystem:194 - The TNM 'axi4lite_0_reset_resync', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification


   'TS_sys_clk_pin', was traced into PLL_ADV instance


   clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM


   groups and period specifications were generated at the PLL_ADV output(s): 


   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0" TS_sys_clk_pin


   HIGH 50>





Done...





Processing BMM file "system.bmm" ...





Checking expanded design ...


WARNING:NgdBuild:443 - SFF primitive


   'microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Decode_I/Using_FPGA.


   Gen_Bits[27].MEM_EX_Result_Inst' has unconnected output pin


WARNING:NgdBuild:452 - logical net 'fsl_v20_0_FSL_M_Control' has no driver


WARNING:NgdBuild:452 - logical net


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/sig00000368' has no


   driver


WARNING:NgdBuild:452 - logical net


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/sig00000581' has no


   driver





Partition Implementation Status


-------------------------------





  No Partitions were found in this design.





-------------------------------





NGDBUILD Design Results Summary:


  Number of errors:     0


  Number of warnings:   7





Writing NGD file "system.ngd" ...


Total REAL time to NGDBUILD completion:  48 sec


Total CPU time to NGDBUILD completion:   44 sec





Writing NGDBUILD log file "system.bld"...





NGDBUILD done.








#----------------------------------------------#

# Starting program map

# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf 

#----------------------------------------------#

Release 14.2 - Map P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>


Using target part "6slx16csg324-3".


vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv


INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to


'2100@vm05.cs.lth.se'.


INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.


INFO:Security:54 - 'xc6slx16' is a WebPack part.


WARNING:Security:43 - No license file was found in the standard Xilinx license


directory.


WARNING:Security:44 - Since no license file was found,


       please run the Xilinx License Configuration Manager


       (xlcm or "Manage Xilinx Licenses")


       to assist in obtaining a license.


WARNING:Security:42 - Your software subscription period has lapsed. Your current


version of Xilinx tools will continue to function, but you no longer qualify for


Xilinx software updates or new releases.


----------------------------------------------------------------------


Mapping design into LUTs...


Writing file system_map.ngm...


Running directed packing...


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e0

e" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig00001395


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000071). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e5

0" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013b3


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000080). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e1

0" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig00001396


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000072). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e1

5" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig00001397


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000073). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e1

7" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig00001398


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000074). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e5

f" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013b9


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000083). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e6

1" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013ba


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000084). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e7

0" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013c2


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm00000086). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000ea

a" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013f8


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm0000008b). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/blk00000e4

e" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/sig000013b2


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000101/blk00000102/hlut


   nm0000007f). The constraint will be ignored.


Running delay-based LUT packing...


Updating timing models...


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report


   (.mrp).


Running timing-driven placement...


Total REAL time at the beginning of Placer: 17 secs 


Total CPU  time at the beginning of Placer: 12 secs 





Phase 1.1  Initial Placement Analysis


Phase 1.1  Initial Placement Analysis (Checksum:f3ca539) REAL time: 18 secs 





Phase 2.7  Design Feasibility Check


INFO:Place:834 - Only a subset of IOs are locked. Out of 35 IOs, 34 are locked


   and 1 are not locked. If you would like to print the names of these IOs,


   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 


Phase 2.7  Design Feasibility Check (Checksum:f3ca539) REAL time: 19 secs 





Phase 3.31  Local Placement Optimization


Phase 3.31  Local Placement Optimization (Checksum:a10a5d51) REAL time: 19 secs 





Phase 4.2  Initial Placement for Architecture Specific Features





Phase 4.2  Initial Placement for Architecture Specific Features


(Checksum:3de05a) REAL time: 21 secs 





Phase 5.36  Local Placement Optimization


Phase 5.36  Local Placement Optimization (Checksum:3de05a) REAL time: 21 secs 





Phase 6.30  Global Clock Region Assignment


Phase 6.30  Global Clock Region Assignment (Checksum:3de05a) REAL time: 21 secs 





Phase 7.3  Local Placement Optimization


Phase 7.3  Local Placement Optimization (Checksum:3de05a) REAL time: 21 secs 





Phase 8.5  Local Placement Optimization


Phase 8.5  Local Placement Optimization (Checksum:3de05a) REAL time: 21 secs 





Phase 9.8  Global Placement


......................


...............................


Trying to terminate Process...
Done!

********************************************************************************
At Local date and time: Tue Oct 15 13:38:09 2013
 make -f system.make netlistclean started...
rm -f implementation/system.ngc

rm -f implementation/system_proc_sys_reset_0_wrapper.ngc implementation/system_microblaze_0_ilmb_wrapper.ngc implementation/system_microblaze_0_i_bram_ctrl_wrapper.ngc implementation/system_microblaze_0_dlmb_wrapper.ngc implementation/system_microblaze_0_d_bram_ctrl_wrapper.ngc implementation/system_microblaze_0_bram_block_wrapper.ngc implementation/system_microblaze_0_wrapper.ngc implementation/system_debug_module_wrapper.ngc implementation/system_clock_generator_0_wrapper.ngc implementation/system_axi4lite_0_wrapper.ngc implementation/system_rs232_uart_1_wrapper.ngc implementation/system_push_buttons_4bits_wrapper.ngc implementation/system_leds_8bits_wrapper.ngc implementation/system_dip_switches_8bits_wrapper.ngc implementation/system_fsl_to_axi_0_wrapper.ngc implementation/system_mem_to_vga_0_wrapper.ngc implementation/system_fsl_v20_0_wrapper.ngc

rm -f platgen.log

rm -f __xps/ise/_xmsgs/platgen.xmsgs

rm -f implementation/system.bmm

rm -rf implementation/cache

Done!
fsl_to_axi_0 has been deleted from the project
Deleting External port : mem_to_vga_0_HS_pin 
Deleting Internal port mem_to_vga_0:HS 
Deleting External port : mem_to_vga_0_VS_pin 
Deleting Internal port mem_to_vga_0:VS 
Deleting External port : mem_to_vga_0_rgb_pin 
Deleting Internal port mem_to_vga_0:rgb 
mem_to_vga_0 has been deleted from the project
Deleting Internal port fsl_v20_0:FSL_Clk 
Deleting Internal port proc_sys_reset_0:Peripheral_Reset 
Deleting Internal port fsl_v20_0:SYS_Rst 
fsl_v20_0 has been deleted from the project
Writing filter settings....
Done writing filter settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.filters
Done writing Tab View settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.gui
Assigned Driver generic 1.00.a for instance fsl_to_axi_0
fsl_to_axi_0 has been added to the project
Assigned Driver generic 1.00.a for instance mem_to_vga_0
mem_to_vga_0 has been added to the project

********************************************************************************
At Local date and time: Tue Oct 15 13:43:16 2013
 make -f system.make exporttosdk started...
IF NOT EXIST "SDK\SDK_Export\hw" @mkdir "SDK\SDK_Export\hw"

psf2Edward -inp system.xmp -exit_on_error -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK\SDK_Export\hw/system.xml 

Release 14.2 - psf2Edward EDK_P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.



Checking platform configuration ...

IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s) 

IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 5 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_0 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_1 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_2 - 1 master(s) : 1 slave(s) 



Checking port drivers...



Performing Clock DRCs...



Performing Reset DRCs...



Overriding system level properties...

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_1_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   21 

WARNING:EDK:4180 - PORT: FSL_M_Clk, CONNECTOR: fsl_v20_2_FSL_M_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   26 

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_0_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\mem_to_vga_v1_00_a\data\mem_to_vga_v2_1_0.mpd line

   20 

WARNING:EDK:4181 - PORT: Peripheral_Reset, CONNECTOR:

   proc_sys_reset_0_Peripheral_Reset - floating connection -

   H:\EDA385\BramFFT\system.mhs line 37 

WARNING:EDK:4181 - PORT: FSL0_M_CLK, CONNECTOR: fsl_v20_0_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 703 

WARNING:EDK:4181 - PORT: FSL1_S_CLK, CONNECTOR: fsl_v20_2_FSL_S_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 708 

WARNING:EDK:4181 - PORT: FSL1_M_CLK, CONNECTOR: fsl_v20_1_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 713 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.




Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Conversion to XML complete.

xdsgen -inp system.xmp -report SDK\SDK_Export\hw/system.html  -make_docs_local

Release 14.2 - xdsgen EDK_P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Generated Block Diagram.

Rasterizing proc_sys_reset_0.jpg.....

Rasterizing microblaze_0_ilmb.jpg.....

Rasterizing microblaze_0_i_bram_ctrl.jpg.....

Rasterizing microblaze_0_dlmb.jpg.....

Rasterizing microblaze_0_d_bram_ctrl.jpg.....

Rasterizing microblaze_0_bram_block.jpg.....

Rasterizing microblaze_0.jpg.....

Rasterizing debug_module.jpg.....

Rasterizing clock_generator_0.jpg.....

Rasterizing axi4lite_0.jpg.....

Rasterizing RS232_Uart_1.jpg.....

Rasterizing Push_Buttons_4Bits.jpg.....

Rasterizing LEDs_8Bits.jpg.....

Rasterizing DIP_Switches_8Bits.jpg.....

Rasterizing fsl_to_axi_0.jpg.....

Rasterizing mem_to_vga_0.jpg.....

Rasterizing fsl_v20_0.jpg.....

Rasterizing fsl_v20_1.jpg.....

Rasterizing fsl_v20_2.jpg.....

Rasterizing system_blkd.jpg.....

Report generated.

Report generation completed.

"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.2 - platgen Xilinx EDK 14.2 Build EDK_P.28xd

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp

C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/ -msg __xps/ise/xmsgprops.lst

system.mhs 



WARNING:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable

   is set to '2100@vm05.cs.lth.se'.

   INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

   INFO:Security:71 - If a license for part 'xc6slx16' is available, it will be

   possible to use 'XPS_TDP' instead of 'XPS'.

   WARNING:Security:43 - No license file was found in the standard Xilinx

   license directory.

   WARNING:Security:44 - Since no license file was found,

          please run the Xilinx License Configuration Manager

          (xlcm or "Manage Xilinx Licenses")

          to assist in obtaining a license.

   WARNING:Security:42 - Your software subscription period has lapsed. Your

   current version of Xilinx tools will continue to function, but you no longer

   qualify for Xilinx software updates or new releases.





Parse H:/EDA385/BramFFT/system.mhs ...



Read MPD definitions ...



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ENDIANNESS value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 196 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ICACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 336 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 366 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_BASEFAMILY value to spartan6 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 80 



Computing clock values...

INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_0:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_1:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_2:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor microblaze_0

  (0000000000-0x00007fff) microblaze_0_d_bram_ctrl	microblaze_0_dlmb

  (0000000000-0x00007fff) microblaze_0_i_bram_ctrl	microblaze_0_ilmb

  (0x40000000-0x4000ffff) Push_Buttons_4Bits	axi4lite_0

  (0x40020000-0x4002ffff) LEDs_8Bits	axi4lite_0

  (0x40040000-0x4004ffff) DIP_Switches_8Bits	axi4lite_0

  (0x40600000-0x4060ffff) RS232_Uart_1	axi4lite_0

  (0x41400000-0x4140ffff) debug_module	axi4lite_0

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block - tool is

   overriding PARAMETER C_MEMSIZE value to 0x8000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d

   ata\bram_block_v2_1_0.mpd line 77 



Checking platform address map ...



Checking platform configuration ...

IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s) 

IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 5 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_0 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_1 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_2 - 1 master(s) : 1 slave(s) 



Checking port drivers...

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_1_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   21 

WARNING:EDK:4180 - PORT: FSL_M_Clk, CONNECTOR: fsl_v20_2_FSL_M_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   26 

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_0_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\mem_to_vga_v1_00_a\data\mem_to_vga_v2_1_0.mpd line

   20 

WARNING:EDK:4181 - PORT: Peripheral_Reset, CONNECTOR:

   proc_sys_reset_0_Peripheral_Reset - floating connection -

   H:\EDA385\BramFFT\system.mhs line 37 

WARNING:EDK:4181 - PORT: FSL0_M_CLK, CONNECTOR: fsl_v20_0_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 703 

WARNING:EDK:4181 - PORT: FSL1_S_CLK, CONNECTOR: fsl_v20_2_FSL_S_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 708 

WARNING:EDK:4181 - PORT: FSL1_M_CLK, CONNECTOR: fsl_v20_1_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 713 



Performing Clock DRCs...

INFO:EDK:4060 - INSTANCE: fsl_v20_0, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.

INFO:EDK:4060 - INSTANCE: fsl_v20_1, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.

INFO:EDK:4060 - INSTANCE: fsl_v20_2, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_i_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_d_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_D_AXI value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 229 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ADDR_TAG_BITS value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 334 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_ADDR_TAG value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 364 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 399 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_NM_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 400 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 148 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...



Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

INFO: Setting timing constaints for microblaze_0_ilmb.


INFO: The microblaze_0_ilmb core has constraints automatically generated by XPS

in implementation/microblaze_0_ilmb_wrapper/microblaze_0_ilmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0_dlmb.


INFO: The microblaze_0_dlmb core has constraints automatically generated by XPS

in implementation/microblaze_0_dlmb_wrapper/microblaze_0_dlmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0.


INFO: The microblaze_0 core has constraints automatically generated by XPS in

implementation/microblaze_0_wrapper/microblaze_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: No asynchronous clock conversions in axi_interconnect axi4lite_0.


INFO: The fsl_v20_0 core has constraints automatically generated by XPS in

implementation/fsl_v20_0_wrapper/fsl_v20_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: The fsl_v20_1 core has constraints automatically generated by XPS in

implementation/fsl_v20_1_wrapper/fsl_v20_1_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: The fsl_v20_2 core has constraints automatically generated by XPS in

implementation/fsl_v20_2_wrapper/fsl_v20_2_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.







Modify defaults ...



Creating stub ...



Processing licensed instances ...

Completion time: 0.00 seconds



Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...

IPNAME:fsl_to_axi INSTANCE:fsl_to_axi_0 - H:\EDA385\BramFFT\system.mhs line 198

- Copying (BBD-specified) netlist files.

IPNAME:mem_to_vga INSTANCE:mem_to_vga_0 - H:\EDA385\BramFFT\system.mhs line 205

- Copying (BBD-specified) netlist files.



Managing cache ...



Elaborating instances ...

IPNAME:bram_block INSTANCE:microblaze_0_bram_block -

H:\EDA385\BramFFT\system.mhs line 72 - elaborating IP

IPNAME:clock_generator INSTANCE:clock_generator_0 - H:\EDA385\BramFFT\system.mhs

line 119 - elaborating IP

ClkGen elaborate status: PASSED


----------------------------------------


----------------------------------------




Writing HDL for elaborated instances ...



Inserting wrapper level ...

Completion time: 1.00 seconds



Constructing platform-level connectivity ...

Completion time: 0.00 seconds



Writing (top-level) BMM ...



Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...



INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 

INSTANCE:proc_sys_reset_0 - H:\EDA385\BramFFT\system.mhs line 26 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_ilmb - H:\EDA385\BramFFT\system.mhs line 40 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_i_bram_ctrl - H:\EDA385\BramFFT\system.mhs line 47 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_dlmb - H:\EDA385\BramFFT\system.mhs line 56 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_d_bram_ctrl - H:\EDA385\BramFFT\system.mhs line 63 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_bram_block - H:\EDA385\BramFFT\system.mhs line 72 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0 - H:\EDA385\BramFFT\system.mhs line 79 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:debug_module - H:\EDA385\BramFFT\system.mhs line 106 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:clock_generator_0 - H:\EDA385\BramFFT\system.mhs line 119 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:axi4lite_0 - H:\EDA385\BramFFT\system.mhs line 133 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:rs232_uart_1 - H:\EDA385\BramFFT\system.mhs line 141 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:push_buttons_4bits - H:\EDA385\BramFFT\system.mhs line 156 - Running

XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:leds_8bits - H:\EDA385\BramFFT\system.mhs line 170 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:dip_switches_8bits - H:\EDA385\BramFFT\system.mhs line 184 - Running

XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_to_axi_0 - H:\EDA385\BramFFT\system.mhs line 198 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:mem_to_vga_0 - H:\EDA385\BramFFT\system.mhs line 205 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_v20_0 - H:\EDA385\BramFFT\system.mhs line 215 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_v20_1 - H:\EDA385\BramFFT\system.mhs line 222 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_v20_2 - H:\EDA385\BramFFT\system.mhs line 229 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Running NGCBUILD ...

IPNAME:system_microblaze_0_ilmb_wrapper INSTANCE:microblaze_0_ilmb -

H:\EDA385\BramFFT\system.mhs line 40 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_ilmb_wrapper.ngc

../system_microblaze_0_ilmb_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/microblaze_0_ilmb_wrapper/system_microblaze_0_

ilmb_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_ilmb_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_ilmb_wrapper.blc"...



NGCBUILD done.

IPNAME:system_microblaze_0_dlmb_wrapper INSTANCE:microblaze_0_dlmb -

H:\EDA385\BramFFT\system.mhs line 56 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_dlmb_wrapper.ngc

../system_microblaze_0_dlmb_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/microblaze_0_dlmb_wrapper/system_microblaze_0_

dlmb_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_dlmb_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_dlmb_wrapper.blc"...



NGCBUILD done.

IPNAME:system_microblaze_0_wrapper INSTANCE:microblaze_0 -

H:\EDA385\BramFFT\system.mhs line 79 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_wrapper.ngc

../system_microblaze_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/microblaze_0_wrapper/system_microblaze_0_wrapp

er.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  3 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -

H:\EDA385\BramFFT\system.mhs line 119 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc

../system_clock_generator_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/clock_generator_0_wrapper/system_clock_generat

or_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi4lite_0_wrapper INSTANCE:axi4lite_0 -

H:\EDA385\BramFFT\system.mhs line 133 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_axi4lite_0_wrapper.ngc

../system_axi4lite_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/axi4lite_0_wrapper/system_axi4lite_0_wrapper.n

gc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi4lite_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_axi4lite_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_to_axi_0_wrapper INSTANCE:fsl_to_axi_0 -

H:\EDA385\BramFFT\system.mhs line 198 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_to_axi_0_wrapper.ngc

../system_fsl_to_axi_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/fsl_to_axi_0_wrapper/system_fsl_to_axi_0_wrapp

er.ngc" ...

Loading design module

"H:\EDA385\BramFFT\implementation\fsl_to_axi_0_wrapper/xfft_v8_0.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_to_axi_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  3 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_to_axi_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_mem_to_vga_0_wrapper INSTANCE:mem_to_vga_0 -

H:\EDA385\BramFFT\system.mhs line 205 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_mem_to_vga_0_wrapper.ngc

../system_mem_to_vga_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/mem_to_vga_0_wrapper/system_mem_to_vga_0_wrapp

er.ngc" ...

Loading design module

"H:\EDA385\BramFFT\implementation\mem_to_vga_0_wrapper/bram.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_mem_to_vga_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_mem_to_vga_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_v20_0_wrapper INSTANCE:fsl_v20_0 -

H:\EDA385\BramFFT\system.mhs line 215 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_v20_0_wrapper.ngc

../system_fsl_v20_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/fsl_v20_0_wrapper/system_fsl_v20_0_wrapper.ngc

" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_v20_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_v20_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_v20_1_wrapper INSTANCE:fsl_v20_1 -

H:\EDA385\BramFFT\system.mhs line 222 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_v20_1_wrapper.ngc

../system_fsl_v20_1_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/fsl_v20_1_wrapper/system_fsl_v20_1_wrapper.ngc

" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_v20_1_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_v20_1_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_v20_2_wrapper INSTANCE:fsl_v20_2 -

H:\EDA385\BramFFT\system.mhs line 229 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_v20_2_wrapper.ngc

../system_fsl_v20_2_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/fsl_v20_2_wrapper/system_fsl_v20_2_wrapper.ngc

" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_v20_2_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_v20_2_wrapper.blc"...



NGCBUILD done.

INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

   If any constraint needs to be overridden, this should be done by modifying

   the data/system.ucf file.



Rebuilding cache ...



Total run time: 325.00 seconds

"Running synthesis..."

cd synthesis & synthesis.cmd

"xst -ifn "system_xst.scr" -intstyle silent"

"Running XST synthesis ..."

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

"XST completed"

"*********************************************"

"Running Xilinx Implementation tools.."

"*********************************************"

xflow -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

Release 14.2 - Xflow P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

 

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Using Flow File: H:/EDA385/BramFFT/implementation/fpga.flw 

Using Option File(s): 

 H:/EDA385/BramFFT/implementation/xflow.opt 



Creating Script File ... 



#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc6slx16csg324-3 -nt timestamp -bm system.bmm

"H:/EDA385/BramFFT/implementation/system.ngc" -uc system.ucf system.ngd 

#----------------------------------------------#

Release 14.2 - ngdbuild P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>





Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p


xc6slx16csg324-3 -nt timestamp -bm system.bmm


H:/EDA385/BramFFT/implementation/system.ngc -uc system.ucf system.ngd





Reading NGO file "H:/EDA385/BramFFT/implementation/system.ngc" ...


Loading design module


"H:/EDA385/BramFFT/implementation/system_push_buttons_4bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_dip_switches_8bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_rs232_uart_1_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_proc_sys_reset_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_clock_generator_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_axi4lite_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_v20_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_v20_1_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_v20_2_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_mem_to_vga_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_i_bram_ctrl_wrapper.ngc"..


.


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_d_bram_ctrl_wrapper.ngc"..


.


Loading design module


"H:/EDA385/BramFFT/implementation/system_debug_module_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_to_axi_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_leds_8bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_bram_block_wrapper.ngc"...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ncf" to


module "microblaze_0_ilmb"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ncf" to


module "microblaze_0_dlmb"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_axi4lite_0_wrapper.ncf" to module


"axi4lite_0"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_wrapper.ncf" to module


"microblaze_0"...


Checking Constraint Associations...


Gathering constraint information from source properties...


Done.





Annotating constraints to design from ucf file "system.ucf" ...


Resolving constraint associations...


Checking Constraint Associations...


WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi4lite_0/axi4lite_0\/si_converter_bank\/gen_conv_sl


   ot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_INV_0 TNM =


   FFS:axi4lite_0_reset_resync>: No instances of type FFS were found under block


   "axi4lite_0/axi4lite_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/int

erconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP axi4lite_0_reset_source = FFS


   PADS CPUS;>: CPUS "*" does not match any design objects.





WARNING:ConstraintSystem:194 - The TNM 'axi4lite_0_reset_resync', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification


   'TS_sys_clk_pin', was traced into PLL_ADV instance


   clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM


   groups and period specifications were generated at the PLL_ADV output(s): 


   CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT1 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT1" TS_sys_clk_pin


   * 0.25 HIGH 50>





INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification


   'TS_sys_clk_pin', was traced into PLL_ADV instance


   clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM


   groups and period specifications were generated at the PLL_ADV output(s): 


   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0" TS_sys_clk_pin


   HIGH 50>





Done...





Processing BMM file "system.bmm" ...





Checking expanded design ...


WARNING:NgdBuild:443 - SFF primitive


   'microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Decode_I/Using_FPGA.


   Gen_Bits[27].MEM_EX_Result_Inst' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000050


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000055


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000066


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000067


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000067


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk00000fe


   b' has unconnected output pin


WARNING:NgdBuild:452 - logical net 'fsl_v20_2_FSL_M_Control' has no driver


WARNING:NgdBuild:452 - logical net


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/sig0000073d' has no


   driver





Partition Implementation Status


-------------------------------





  No Partitions were found in this design.





-------------------------------





NGDBUILD Design Results Summary:


  Number of errors:     0


  Number of warnings:  79





Writing NGD file "system.ngd" ...


Total REAL time to NGDBUILD completion:  48 sec


Total CPU time to NGDBUILD completion:   44 sec





Writing NGDBUILD log file "system.bld"...





NGDBUILD done.








#----------------------------------------------#

# Starting program map

# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf 

#----------------------------------------------#

Release 14.2 - Map P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>


Using target part "6slx16csg324-3".


vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv


INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to


'2100@vm05.cs.lth.se'.


INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.


INFO:Security:54 - 'xc6slx16' is a WebPack part.


WARNING:Security:43 - No license file was found in the standard Xilinx license


directory.


WARNING:Security:44 - Since no license file was found,


       please run the Xilinx License Configuration Manager


       (xlcm or "Manage Xilinx Licenses")


       to assist in obtaining a license.


WARNING:Security:42 - Your software subscription period has lapsed. Your current


version of Xilinx tools will continue to function, but you no longer qualify for


Xilinx software updates or new releases.


----------------------------------------------------------------------


Mapping design into LUTs...


Writing file system_map.ngm...


Running directed packing...


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

4" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175c


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000091). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

6" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175d


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000092). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

1" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000172f


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000076). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

8" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175e


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000093). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

3" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001730


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000077). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

5" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001731


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000078). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

a" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001732


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000079). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

c" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001733


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000007a). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

e" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001734


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000007b). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010c

f" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001753


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008b). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010d

1" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001754


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008c). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010d

3" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001755


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008d). The constraint will be ignored.


Running delay-based LUT packing...


Updating timing models...


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report


   (.mrp).


Running timing-driven placement...


Total REAL time at the beginning of Placer: 19 secs 


Total CPU  time at the beginning of Placer: 14 secs 





Phase 1.1  Initial Placement Analysis


Phase 1.1  Initial Placement Analysis (Checksum:229373d9) REAL time: 20 secs 





Phase 2.7  Design Feasibility Check


Phase 2.7  Design Feasibility Check (Checksum:229373d9) REAL time: 20 secs 





Phase 3.31  Local Placement Optimization


Phase 3.31  Local Placement Optimization (Checksum:f35fea41) REAL time: 20 secs 





Phase 4.2  Initial Placement for Architecture Specific Features





Phase 4.2  Initial Placement for Architecture Specific Features


(Checksum:f4ab6800) REAL time: 24 secs 





Phase 5.36  Local Placement Optimization


Phase 5.36  Local Placement Optimization (Checksum:f4ab6800) REAL time: 24 secs 





Phase 6.30  Global Clock Region Assignment


Phase 6.30  Global Clock Region Assignment (Checksum:f4ab6800) REAL time: 24 secs 





Phase 7.3  Local Placement Optimization


Phase 7.3  Local Placement Optimization (Checksum:f4ab6800) REAL time: 24 secs 





Phase 8.5  Local Placement Optimization


Phase 8.5  Local Placement Optimization (Checksum:f4ab6800) REAL time: 24 secs 





Phase 9.8  Global Placement


.....................


...............................................................


.........................................


...............................................................


...........................


Phase 9.8  Global Placement (Checksum:7bfd2261) REAL time: 1 mins 19 secs 





Phase 10.5  Local Placement Optimization


Phase 10.5  Local Placement Optimization (Checksum:7bfd2261) REAL time: 1 mins 19 secs 





Phase 11.18  Placement Optimization


Phase 11.18  Placement Optimization (Checksum:cd0926ed) REAL time: 1 mins 33 secs 





Phase 12.5  Local Placement Optimization


Phase 12.5  Local Placement Optimization (Checksum:cd0926ed) REAL time: 1 mins 33 secs 





Phase 13.34  Placement Validation


Phase 13.34  Placement Validation (Checksum:f0c607da) REAL time: 1 mins 33 secs 





Total REAL time to Placer completion: 1 mins 34 secs 


Total CPU  time to Placer completion: 1 mins 29 secs 


Running post-placement packing...


Writing output files...





Design Summary:


Number of errors:      0


Number of warnings:   51


Slice Logic Utilization:


  Number of Slice Registers:                 3,750 out of  18,224   20


    Number used as Flip Flops:               3,743


    Number used as Latches:                      0


    Number used as Latch-thrus:                  0


    Number used as AND/OR logics:                7


  Number of Slice LUTs:                      4,005 out of   9,112   43


    Number used as logic:                    3,381 out of   9,112   37


      Number using O6 output only:           2,508


      Number using O5 output only:              71


      Number using O5 and O6:                  802


      Number used as ROM:                        0


    Number used as Memory:                     504 out of   2,176   23


      Number used as Dual Port RAM:            152


        Number using O6 output only:            88


        Number using O5 output only:             0


        Number using O5 and O6:                 64


      Number used as Single Port RAM:            0


      Number used as Shift Register:           352


        Number using O6 output only:            47


        Number using O5 output only:             1


        Number using O5 and O6:                304


    Number used exclusively as route-thrus:    120


      Number with same-slice register load:    111


      Number with same-slice carry load:         9


      Number with other load:                    0





Slice Logic Distribution:


  Number of occupied Slices:                 1,555 out of   2,278   68


  Nummber of MUXCYs used:                      860 out of   4,556   18


  Number of LUT Flip Flop pairs used:        4,633


    Number with an unused Flip Flop:         1,515 out of   4,633   32


    Number with an unused LUT:                 628 out of   4,633   13


    Number of fully used LUT-FF pairs:       2,490 out of   4,633   53


    Number of unique control sets:             159


    Number of slice register sites lost


      to control set restrictions:             609 out of  18,224    3





  A LUT Flip Flop pair for this architecture represents one LUT paired with


  one Flip Flop within a slice.  A control set is a unique combination of


  clock, reset, set, and enable signals for a registered element.


  The Slice Logic Distribution report is not meaningful if the design is


  over-mapped for a non-slice resource or if Placement fails.





IO Utilization:


  Number of bonded IOBs:                        34 out of     232   14


    Number of LOCed IOBs:                       34 out of      34  100


    IOB Flip Flops:                              4





Specific Feature Utilization:


  Number of RAMB16BWERs:                        24 out of      32   75


  Number of RAMB8BWERs:                          7 out of      64   10


  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3


    Number used as BUFIO2s:                      1


    Number used as BUFIO2_2CLKs:                 0


  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0


  Number of BUFG/BUFGMUXs:                       3 out of      16   18


    Number used as BUFGs:                        3


    Number used as BUFGMUX:                      0


  Number of DCM/DCM_CLKGENs:                     0 out of       4    0


  Number of ILOGIC2/ISERDES2s:                   1 out of     248    1


    Number used as ILOGIC2s:                     1


    Number used as ISERDES2s:                    0


  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0


  Number of OLOGIC2/OSERDES2s:                   3 out of     248    1


    Number used as OLOGIC2s:                     3


    Number used as OSERDES2s:                    0


  Number of BSCANs:                              1 out of       4   25


  Number of BUFHs:                               0 out of     128    0


  Number of BUFPLLs:                             0 out of       8    0


  Number of BUFPLL_MCBs:                         0 out of       4    0


  Number of DSP48A1s:                           12 out of      32   37


  Number of ICAPs:                               0 out of       1    0


  Number of MCBs:                                0 out of       2    0


  Number of PCILOGICSEs:                         0 out of       2    0


  Number of PLL_ADVs:                            1 out of       2   50


  Number of PMVs:                                0 out of       1    0


  Number of STARTUPs:                            0 out of       1    0


  Number of SUSPEND_SYNCs:                       0 out of       1    0





Average Fanout of Non-Clock Nets:                3.81





Peak Memory Usage:  510 MB


Total REAL time to MAP completion:  1 mins 38 secs 


Total CPU time to MAP completion:   1 mins 33 secs 





Mapping completed.


See MAP report file "system_map.mrp" for details.








#----------------------------------------------#

# Starting program par

# par -w -ol high system_map.ncd system.ncd system.pcf 

#----------------------------------------------#

Release 14.2 - par P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <C:/Xilinx/14.2/ISE_DS/EDK/data/parBmgr.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/data/parBmgr.acd>







Constraints file: system.pcf.

Loading device for application Rf_Device from file '6slx16.nph' in environment

C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv

INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to '2100@vm05.cs.lth.se'.

INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

INFO:Security:54 - 'xc6slx16' is a WebPack part.

WARNING:Security:43 - No license file was found in the standard Xilinx license directory.

WARNING:Security:44 - Since no license file was found,

       please run the Xilinx License Configuration Manager

       (xlcm or "Manage Xilinx Licenses")

       to assist in obtaining a license.

WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue

to function, but you no longer qualify for Xilinx software updates or new releases.



----------------------------------------------------------------------



Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)





Device speed data version:  "PRODUCTION 1.22 2012-07-09".







Device Utilization Summary:



Slice Logic Utilization:

  Number of Slice Registers:                 3,750 out of  18,224   20

    Number used as Flip Flops:               3,743

    Number used as Latches:                      0

    Number used as Latch-thrus:                  0

    Number used as AND/OR logics:                7

  Number of Slice LUTs:                      4,005 out of   9,112   43

    Number used as logic:                    3,381 out of   9,112   37

      Number using O6 output only:           2,508

      Number using O5 output only:              71

      Number using O5 and O6:                  802

      Number used as ROM:                        0

    Number used as Memory:                     504 out of   2,176   23

      Number used as Dual Port RAM:            152

        Number using O6 output only:            88

        Number using O5 output only:             0

        Number using O5 and O6:                 64

      Number used as Single Port RAM:            0

      Number used as Shift Register:           352

        Number using O6 output only:            47

        Number using O5 output only:             1

        Number using O5 and O6:                304

    Number used exclusively as route-thrus:    120

      Number with same-slice register load:    111

      Number with same-slice carry load:         9

      Number with other load:                    0



Slice Logic Distribution:

  Number of occupied Slices:                 1,555 out of   2,278   68

  Nummber of MUXCYs used:                      860 out of   4,556   18

  Number of LUT Flip Flop pairs used:        4,633

    Number with an unused Flip Flop:         1,515 out of   4,633   32

    Number with an unused LUT:                 628 out of   4,633   13

    Number of fully used LUT-FF pairs:       2,490 out of   4,633   53

    Number of slice register sites lost

      to control set restrictions:               0 out of  18,224    0



  A LUT Flip Flop pair for this architecture represents one LUT paired with

  one Flip Flop within a slice.  A control set is a unique combination of

  clock, reset, set, and enable signals for a registered element.

  The Slice Logic Distribution report is not meaningful if the design is

  over-mapped for a non-slice resource or if Placement fails.



IO Utilization:

  Number of bonded IOBs:                        34 out of     232   14

    Number of LOCed IOBs:                       34 out of      34  100

    IOB Flip Flops:                              4



Specific Feature Utilization:

  Number of RAMB16BWERs:                        24 out of      32   75

  Number of RAMB8BWERs:                          7 out of      64   10

  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3

    Number used as BUFIO2s:                      1

    Number used as BUFIO2_2CLKs:                 0

  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0

  Number of BUFG/BUFGMUXs:                       3 out of      16   18

    Number used as BUFGs:                        3

    Number used as BUFGMUX:                      0

  Number of DCM/DCM_CLKGENs:                     0 out of       4    0

  Number of ILOGIC2/ISERDES2s:                   1 out of     248    1

    Number used as ILOGIC2s:                     1

    Number used as ISERDES2s:                    0

  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0

  Number of OLOGIC2/OSERDES2s:                   3 out of     248    1

    Number used as OLOGIC2s:                     3

    Number used as OSERDES2s:                    0

  Number of BSCANs:                              1 out of       4   25

  Number of BUFHs:                               0 out of     128    0

  Number of BUFPLLs:                             0 out of       8    0

  Number of BUFPLL_MCBs:                         0 out of       4    0

  Number of DSP48A1s:                           12 out of      32   37

  Number of ICAPs:                               0 out of       1    0

  Number of MCBs:                                0 out of       2    0

  Number of PCILOGICSEs:                         0 out of       2    0

  Number of PLL_ADVs:                            1 out of       2   50

  Number of PMVs:                                0 out of       1    0

  Number of STARTUPs:                            0 out of       1    0

  Number of SUSPEND_SYNCs:                       0 out of       1    0





Overall effort level (-ol):   High 

Router effort level (-rl):    High 



INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx

   Command Line Tools User Guide for information on generating a TSI report.

Starting initial Timing Analysis.  REAL time: 8 secs 

Finished initial Timing Analysis.  REAL time: 8 secs 



WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM14_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM8_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM20_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM19_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM17_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM13_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM5_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM7_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM16_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM15_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM6_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM4_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<31> has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM10_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM9_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM3_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM12_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM11_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM2_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM1_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM18_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<30> has no load.  PAR will not attempt to route

   this signal.

Starting Router





Phase  1  : 29143 unrouted;      REAL time: 11 secs 



Phase  2  : 22573 unrouted;      REAL time: 12 secs 



Phase  3  : 9351 unrouted;      REAL time: 26 secs 



Phase  4  : 9351 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 27 secs 



Updating file: system.ncd with current fully routed design.



Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 40 secs 

Total REAL time to Router completion: 40 secs 

Total CPU time to Router completion: 36 secs 



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



Generating "PAR" statistics.



**************************

Generating Clock Report

**************************



+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|     clk_100_0000MHz | BUFGMUX_X3Y13| No   | 1379 |  0.544     |  1.390      |

+---------------------+--------------+------+------+------------+-------------+

|microblaze_0_debug_D |              |      |      |            |             |

|              bg_Clk |  BUFGMUX_X2Y2| No   |   61 |  0.056     |  0.909      |

+---------------------+--------------+------+------+------------+-------------+

|clock_generator_0_CL |              |      |      |            |             |

|               KOUT1 |  BUFGMUX_X2Y3| No   |    9 |  0.478     |  1.366      |

+---------------------+--------------+------+------+------------+-------------+

|microblaze_0_debug_D |              |      |      |            |             |

|           bg_Update |         Local|      |   21 |  2.312     |  3.414      |

+---------------------+--------------+------+------+------------+-------------+



* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.



* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.



Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Number of Timing Constraints that were not applied: 1



Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.



----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   

                                            |             |    Slack   | Achievable | Errors |    Score   

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |     1.128ns|     8.872ns|       0|           0

  G_PLL0_CLKOUT0 = PERIOD TIMEGRP         " | HOLD        |     0.216ns|            |       0|           0

  clock_generator_0_clock_generator_0_SIG_P |             |            |            |        |            

  LL0_CLKOUT0" TS_sys_clk_pin         HIGH  |             |            |            |        |            

  50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |     5.224ns|    19.104ns|       0|           0

  G_PLL0_CLKOUT1 = PERIOD TIMEGRP         " | HOLD        |     0.425ns|            |       0|           0

  clock_generator_0_clock_generator_0_SIG_P |             |            |            |        |            

  LL0_CLKOUT1" TS_sys_clk_pin         * 0.2 |             |            |            |        |            

  5 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.666ns|     3.334ns|       0|           0

  pin" 100 MHz HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_Reset_path" TIG | SETUP       |         N/A|     2.384ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi4lite_0_reset_resync_path" TI | MAXDELAY    |         N/A|     4.599ns|     N/A|           0

  G                                         |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_dlmb_POR_FF_I_p | SETUP       |         N/A|     1.751ns|     N/A|           0

  ath" TIG                                  |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_ilmb_POR_FF_I_p | SETUP       |         N/A|     2.524ns|     N/A|           0

  ath" TIG                                  |             |            |            |        |            

----------------------------------------------------------------------------------------------------------





Derived Constraint Report

Review Timing Report for more details on the following derived constraints.

To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"

or "Run Timing Analysis" from Timing Analyzer (timingan).

Derived Constraints for TS_sys_clk_pin

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |

|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|

|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|TS_sys_clk_pin                 |     10.000ns|      3.334ns|      8.872ns|            0|            0|            0|       312110|

| TS_clock_generator_0_clock_gen|     40.000ns|     19.104ns|          N/A|            0|            0|          620|            0|

| erator_0_SIG_PLL0_CLKOUT1     |             |             |             |             |             |             |             |

| TS_clock_generator_0_clock_gen|     10.000ns|      8.872ns|          N/A|            0|            0|       311490|            0|

| erator_0_SIG_PLL0_CLKOUT0     |             |             |             |             |             |             |             |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+



All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 

   constraint is not analyzed due to the following: No paths covered by this 

   constraint; Other constraints intersect with this constraint; or This 

   constraint was disabled by a Path Tracing Control. Please run the Timespec 

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.





Generating Pad Report.



All signals are completely routed.



WARNING:Par:283 - There are 38 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.



Total REAL time to PAR completion: 51 secs 

Total CPU time to PAR completion: 40 secs 



Peak Memory Usage:  469 MB



Placer: Placement generated during map.

Routing: Completed - No errors found.

Timing: Completed - No errors found.



Number of error messages: 0

Number of warning messages: 40

Number of info messages: 1



Writing design to file system.ncd







PAR done!







#----------------------------------------------#

# Starting program post_par_trce

# trce -e 3 -xml system.twx system.ncd system.pcf 

#----------------------------------------------#

Release 14.2 - Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.








PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>


Loading device for application Rf_Device from file '6slx16.nph' in environment


C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.


   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3


INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more


   information, see the TSI report.  Please consult the Xilinx Command Line


   Tools User Guide for information on generating a TSI report.


--------------------------------------------------------------------------------


Release 14.2 Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -e 3 -xml system.twx


system.ncd system.pcf








Design file:              system.ncd


Physical constraint file: system.pcf


Device,speed:             xc6slx16,-3 (PRODUCTION 1.22 2012-07-09)


Report level:             error report


--------------------------------------------------------------------------------





INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).


INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in


   the unconstrained paths section(s) of the report.


INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of


   this model, and for more information on accounting for different loading conditions, please see the device datasheet.








Timing summary:


---------------





Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)





Constraints cover 312123 paths, 0 nets, and 22706 connections





Design statistics:


   Minimum period:  19.104ns (Maximum frequency:  52.345MHz)








Analysis completed Tue Oct 15 13:53:07 2013


--------------------------------------------------------------------------------





Generating Report ...





Number of warnings: 0


Number of info messages: 4


Total time: 9 secs 






xflow done!

touch __xps/system_routed

xilperl C:/Xilinx/14.2/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par

"*********************************************"

"Running Bitgen.."

"*********************************************"

cd implementation & bitgen -w -f bitgen.ut system & cd ..

Release 14.2 - Bitgen P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

Loading device for application Rf_Device from file '6slx16.nph' in environment

C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3

Opened constraints file system.pcf.



Tue Oct 15 13:53:14 2013



INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER). 

   9K Block RAM initialization data, both user defined and default, requires a

   special bit stream format.  For more information, please reference Xilinx

   Answer Record 39999.

Running DRC.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM14_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM8_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM20_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM19_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM17_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM13_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM5_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM7_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM16_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM15_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM6_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM4_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<31>> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM10_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM9_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM3_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM12_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM11_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM2_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM1_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM18_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<30>> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs

   (RAMB8BWER).  9K Block RAM initialization data, both user defined and

   default, may be incorrect and should not be used.  For more information,

   please reference Xilinx Answer Record 39999.

DRC detected 0 errors and 39 warnings.  Please see the previously displayed

individual error or warning messages for more details.

INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to

'2100@vm05.cs.lth.se'.

INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

INFO:Security:54 - 'xc6slx16' is a WebPack part.

WARNING:Security:43 - No license file was found in the standard Xilinx license

directory.

WARNING:Security:44 - Since no license file was found,

       please run the Xilinx License Configuration Manager

       (xlcm or "Manage Xilinx Licenses")

       to assist in obtaining a license.

WARNING:Security:42 - Your software subscription period has lapsed. Your current

version of Xilinx tools will continue to function, but you no longer qualify for

Xilinx software updates or new releases.



Creating bit map...

Saving bit stream in "system.bit".

Bitstream generation is complete.

Done!

********************************************************************************
At Local date and time: Tue Oct 15 13:53:33 2013
 xsdk.exe -hwspec \\tiger\et09mo0\EDA385\BramFFT\SDK\SDK_Export\hw\system.xml started...
Xilinx Software Development Kit

Xilinx EDK 14.2 Build EDK_P.28xd

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Done!

********************************************************************************
At Local date and time: Tue Oct 15 14:33:42 2013
 make -f system.make netlistclean started...
rm -f implementation/system.ngc

rm -f implementation/system_proc_sys_reset_0_wrapper.ngc implementation/system_microblaze_0_ilmb_wrapper.ngc implementation/system_microblaze_0_i_bram_ctrl_wrapper.ngc implementation/system_microblaze_0_dlmb_wrapper.ngc implementation/system_microblaze_0_d_bram_ctrl_wrapper.ngc implementation/system_microblaze_0_bram_block_wrapper.ngc implementation/system_microblaze_0_wrapper.ngc implementation/system_debug_module_wrapper.ngc implementation/system_clock_generator_0_wrapper.ngc implementation/system_axi4lite_0_wrapper.ngc implementation/system_rs232_uart_1_wrapper.ngc implementation/system_push_buttons_4bits_wrapper.ngc implementation/system_leds_8bits_wrapper.ngc implementation/system_dip_switches_8bits_wrapper.ngc implementation/system_fsl_to_axi_0_wrapper.ngc implementation/system_mem_to_vga_0_wrapper.ngc implementation/system_fsl_v20_0_wrapper.ngc implementation/system_fsl_v20_1_wrapper.ngc implementation/system_fsl_v20_2_wrapper.ngc

rm -f platgen.log

rm -f __xps/ise/_xmsgs/platgen.xmsgs

rm -f implementation/system.bmm

rm -rf implementation/cache

Done!

********************************************************************************
At Local date and time: Tue Oct 15 14:34:09 2013
 make -f system.make exporttosdk started...
"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.2 - platgen Xilinx EDK 14.2 Build EDK_P.28xd

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp

C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/ -msg __xps/ise/xmsgprops.lst

system.mhs 



WARNING:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable

   is set to '2100@vm05.cs.lth.se'.

   INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

   INFO:Security:71 - If a license for part 'xc6slx16' is available, it will be

   possible to use 'XPS_TDP' instead of 'XPS'.

   WARNING:Security:43 - No license file was found in the standard Xilinx

   license directory.

   WARNING:Security:44 - Since no license file was found,

          please run the Xilinx License Configuration Manager

          (xlcm or "Manage Xilinx Licenses")

          to assist in obtaining a license.

   WARNING:Security:42 - Your software subscription period has lapsed. Your

   current version of Xilinx tools will continue to function, but you no longer

   qualify for Xilinx software updates or new releases.





Parse H:/EDA385/BramFFT/system.mhs ...



Read MPD definitions ...



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ENDIANNESS value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 196 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ICACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 336 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 366 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_BASEFAMILY value to spartan6 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 80 



Computing clock values...

INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_0:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_1:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_2:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor microblaze_0

  (0000000000-0x00007fff) microblaze_0_d_bram_ctrl	microblaze_0_dlmb

  (0000000000-0x00007fff) microblaze_0_i_bram_ctrl	microblaze_0_ilmb

  (0x40000000-0x4000ffff) Push_Buttons_4Bits	axi4lite_0

  (0x40020000-0x4002ffff) LEDs_8Bits	axi4lite_0

  (0x40040000-0x4004ffff) DIP_Switches_8Bits	axi4lite_0

  (0x40600000-0x4060ffff) RS232_Uart_1	axi4lite_0

  (0x41400000-0x4140ffff) debug_module	axi4lite_0

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block - tool is

   overriding PARAMETER C_MEMSIZE value to 0x8000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d

   ata\bram_block_v2_1_0.mpd line 77 



Checking platform address map ...



Checking platform configuration ...

IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s) 

IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 5 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_0 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_1 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_2 - 1 master(s) : 1 slave(s) 



Checking port drivers...

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_1_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   21 

WARNING:EDK:4180 - PORT: FSL_M_Clk, CONNECTOR: fsl_v20_2_FSL_M_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   26 

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_0_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\mem_to_vga_v1_00_a\data\mem_to_vga_v2_1_0.mpd line

   20 

WARNING:EDK:4181 - PORT: Peripheral_Reset, CONNECTOR:

   proc_sys_reset_0_Peripheral_Reset - floating connection -

   H:\EDA385\BramFFT\system.mhs line 37 

WARNING:EDK:4181 - PORT: FSL0_M_CLK, CONNECTOR: fsl_v20_0_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 703 

WARNING:EDK:4181 - PORT: FSL1_S_CLK, CONNECTOR: fsl_v20_2_FSL_S_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 708 

WARNING:EDK:4181 - PORT: FSL1_M_CLK, CONNECTOR: fsl_v20_1_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 713 



Performing Clock DRCs...

INFO:EDK:4060 - INSTANCE: fsl_v20_0, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.

INFO:EDK:4060 - INSTANCE: fsl_v20_1, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.

INFO:EDK:4060 - INSTANCE: fsl_v20_2, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_i_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_d_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_D_AXI value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 229 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ADDR_TAG_BITS value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 334 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_ADDR_TAG value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 364 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 399 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_NM_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 400 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 148 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...



Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

INFO: Setting timing constaints for microblaze_0_ilmb.


INFO: The microblaze_0_ilmb core has constraints automatically generated by XPS

in implementation/microblaze_0_ilmb_wrapper/microblaze_0_ilmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0_dlmb.


INFO: The microblaze_0_dlmb core has constraints automatically generated by XPS

in implementation/microblaze_0_dlmb_wrapper/microblaze_0_dlmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0.


INFO: The microblaze_0 core has constraints automatically generated by XPS in

implementation/microblaze_0_wrapper/microblaze_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: No asynchronous clock conversions in axi_interconnect axi4lite_0.


INFO: The fsl_v20_0 core has constraints automatically generated by XPS in

implementation/fsl_v20_0_wrapper/fsl_v20_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: The fsl_v20_1 core has constraints automatically generated by XPS in

implementation/fsl_v20_1_wrapper/fsl_v20_1_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: The fsl_v20_2 core has constraints automatically generated by XPS in

implementation/fsl_v20_2_wrapper/fsl_v20_2_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.







Modify defaults ...



Creating stub ...



Processing licensed instances ...

Completion time: 0.00 seconds



Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...

IPNAME:fsl_to_axi INSTANCE:fsl_to_axi_0 - H:\EDA385\BramFFT\system.mhs line 198

- Copying (BBD-specified) netlist files.

IPNAME:mem_to_vga INSTANCE:mem_to_vga_0 - H:\EDA385\BramFFT\system.mhs line 205

- Copying (BBD-specified) netlist files.



Managing cache ...



Elaborating instances ...

IPNAME:bram_block INSTANCE:microblaze_0_bram_block -

H:\EDA385\BramFFT\system.mhs line 72 - elaborating IP

IPNAME:clock_generator INSTANCE:clock_generator_0 - H:\EDA385\BramFFT\system.mhs

line 119 - elaborating IP

ClkGen elaborate status: PASSED


----------------------------------------


----------------------------------------




Writing HDL for elaborated instances ...



Inserting wrapper level ...

Completion time: 1.00 seconds



Constructing platform-level connectivity ...

Completion time: 0.00 seconds



Writing (top-level) BMM ...



Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...



INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 

INSTANCE:proc_sys_reset_0 - H:\EDA385\BramFFT\system.mhs line 26 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_ilmb - H:\EDA385\BramFFT\system.mhs line 40 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_i_bram_ctrl - H:\EDA385\BramFFT\system.mhs line 47 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_dlmb - H:\EDA385\BramFFT\system.mhs line 56 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_d_bram_ctrl - H:\EDA385\BramFFT\system.mhs line 63 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_bram_block - H:\EDA385\BramFFT\system.mhs line 72 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0 - H:\EDA385\BramFFT\system.mhs line 79 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:debug_module - H:\EDA385\BramFFT\system.mhs line 106 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:clock_generator_0 - H:\EDA385\BramFFT\system.mhs line 119 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:axi4lite_0 - H:\EDA385\BramFFT\system.mhs line 133 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:rs232_uart_1 - H:\EDA385\BramFFT\system.mhs line 141 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:push_buttons_4bits - H:\EDA385\BramFFT\system.mhs line 156 - Running

XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:leds_8bits - H:\EDA385\BramFFT\system.mhs line 170 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:dip_switches_8bits - H:\EDA385\BramFFT\system.mhs line 184 - Running

XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_to_axi_0 - H:\EDA385\BramFFT\system.mhs line 198 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:mem_to_vga_0 - H:\EDA385\BramFFT\system.mhs line 205 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_v20_0 - H:\EDA385\BramFFT\system.mhs line 215 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_v20_1 - H:\EDA385\BramFFT\system.mhs line 222 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_v20_2 - H:\EDA385\BramFFT\system.mhs line 229 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Running NGCBUILD ...

IPNAME:system_microblaze_0_ilmb_wrapper INSTANCE:microblaze_0_ilmb -

H:\EDA385\BramFFT\system.mhs line 40 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_ilmb_wrapper.ngc

../system_microblaze_0_ilmb_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/microblaze_0_ilmb_wrapper/system_microblaze_0_

ilmb_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_ilmb_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_ilmb_wrapper.blc"...



NGCBUILD done.

IPNAME:system_microblaze_0_dlmb_wrapper INSTANCE:microblaze_0_dlmb -

H:\EDA385\BramFFT\system.mhs line 56 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_dlmb_wrapper.ngc

../system_microblaze_0_dlmb_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/microblaze_0_dlmb_wrapper/system_microblaze_0_

dlmb_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_dlmb_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_dlmb_wrapper.blc"...



NGCBUILD done.

IPNAME:system_microblaze_0_wrapper INSTANCE:microblaze_0 -

H:\EDA385\BramFFT\system.mhs line 79 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_wrapper.ngc

../system_microblaze_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/microblaze_0_wrapper/system_microblaze_0_wrapp

er.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  3 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -

H:\EDA385\BramFFT\system.mhs line 119 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc

../system_clock_generator_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/clock_generator_0_wrapper/system_clock_generat

or_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi4lite_0_wrapper INSTANCE:axi4lite_0 -

H:\EDA385\BramFFT\system.mhs line 133 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_axi4lite_0_wrapper.ngc

../system_axi4lite_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/axi4lite_0_wrapper/system_axi4lite_0_wrapper.n

gc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi4lite_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_axi4lite_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_to_axi_0_wrapper INSTANCE:fsl_to_axi_0 -

H:\EDA385\BramFFT\system.mhs line 198 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_to_axi_0_wrapper.ngc

../system_fsl_to_axi_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/fsl_to_axi_0_wrapper/system_fsl_to_axi_0_wrapp

er.ngc" ...

Loading design module

"H:\EDA385\BramFFT\implementation\fsl_to_axi_0_wrapper/xfft_v8_0.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_to_axi_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  3 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_to_axi_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_mem_to_vga_0_wrapper INSTANCE:mem_to_vga_0 -

H:\EDA385\BramFFT\system.mhs line 205 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_mem_to_vga_0_wrapper.ngc

../system_mem_to_vga_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/mem_to_vga_0_wrapper/system_mem_to_vga_0_wrapp

er.ngc" ...

Loading design module

"H:\EDA385\BramFFT\implementation\mem_to_vga_0_wrapper/bram.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_mem_to_vga_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_mem_to_vga_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_v20_0_wrapper INSTANCE:fsl_v20_0 -

H:\EDA385\BramFFT\system.mhs line 215 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_v20_0_wrapper.ngc

../system_fsl_v20_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/fsl_v20_0_wrapper/system_fsl_v20_0_wrapper.ngc

" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_v20_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_v20_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_v20_1_wrapper INSTANCE:fsl_v20_1 -

H:\EDA385\BramFFT\system.mhs line 222 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_v20_1_wrapper.ngc

../system_fsl_v20_1_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/fsl_v20_1_wrapper/system_fsl_v20_1_wrapper.ngc

" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_v20_1_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_v20_1_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_v20_2_wrapper INSTANCE:fsl_v20_2 -

H:\EDA385\BramFFT\system.mhs line 229 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_v20_2_wrapper.ngc

../system_fsl_v20_2_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/fsl_v20_2_wrapper/system_fsl_v20_2_wrapper.ngc

" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_v20_2_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_v20_2_wrapper.blc"...



NGCBUILD done.

INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

   If any constraint needs to be overridden, this should be done by modifying

   the data/system.ucf file.



Rebuilding cache ...



Total run time: 330.00 seconds

"Running synthesis..."

cd synthesis & synthesis.cmd

"xst -ifn "system_xst.scr" -intstyle silent"

"Running XST synthesis ..."

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

"XST completed"

"*********************************************"

"Running Xilinx Implementation tools.."

"*********************************************"

xflow -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

Release 14.2 - Xflow P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

 

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Using Flow File: H:/EDA385/BramFFT/implementation/fpga.flw 

Using Option File(s): 

 H:/EDA385/BramFFT/implementation/xflow.opt 



Creating Script File ... 



#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc6slx16csg324-3 -nt timestamp -bm system.bmm

"H:/EDA385/BramFFT/implementation/system.ngc" -uc system.ucf system.ngd 

#----------------------------------------------#

Release 14.2 - ngdbuild P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>





Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p


xc6slx16csg324-3 -nt timestamp -bm system.bmm


H:/EDA385/BramFFT/implementation/system.ngc -uc system.ucf system.ngd





Reading NGO file "H:/EDA385/BramFFT/implementation/system.ngc" ...


Loading design module


"H:/EDA385/BramFFT/implementation/system_push_buttons_4bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_dip_switches_8bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_rs232_uart_1_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_proc_sys_reset_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_clock_generator_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_axi4lite_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_v20_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_v20_1_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_v20_2_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_mem_to_vga_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_i_bram_ctrl_wrapper.ngc"..


.


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_d_bram_ctrl_wrapper.ngc"..


.


Loading design module


"H:/EDA385/BramFFT/implementation/system_debug_module_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_to_axi_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_leds_8bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_bram_block_wrapper.ngc"...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ncf" to


module "microblaze_0_ilmb"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ncf" to


module "microblaze_0_dlmb"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_axi4lite_0_wrapper.ncf" to module


"axi4lite_0"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_wrapper.ncf" to module


"microblaze_0"...


Checking Constraint Associations...


Gathering constraint information from source properties...


Done.





Annotating constraints to design from ucf file "system.ucf" ...


Resolving constraint associations...


Checking Constraint Associations...


WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi4lite_0/axi4lite_0\/si_converter_bank\/gen_conv_sl


   ot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_INV_0 TNM =


   FFS:axi4lite_0_reset_resync>: No instances of type FFS were found under block


   "axi4lite_0/axi4lite_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/int

erconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP axi4lite_0_reset_source = FFS


   PADS CPUS;>: CPUS "*" does not match any design objects.





WARNING:ConstraintSystem:194 - The TNM 'axi4lite_0_reset_resync', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification


   'TS_sys_clk_pin', was traced into PLL_ADV instance


   clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM


   groups and period specifications were generated at the PLL_ADV output(s): 


   CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT1 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT1" TS_sys_clk_pin


   * 0.25 HIGH 50>





INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification


   'TS_sys_clk_pin', was traced into PLL_ADV instance


   clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM


   groups and period specifications were generated at the PLL_ADV output(s): 


   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0" TS_sys_clk_pin


   HIGH 50>





Done...





Processing BMM file "system.bmm" ...





Checking expanded design ...


WARNING:NgdBuild:443 - SFF primitive


   'microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Decode_I/Using_FPGA.


   Gen_Bits[27].MEM_EX_Result_Inst' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000050


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000055


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000066


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000067


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000067


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk00000fe


   b' has unconnected output pin


WARNING:NgdBuild:452 - logical net 'fsl_v20_2_FSL_M_Control' has no driver


WARNING:NgdBuild:452 - logical net


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/sig0000073d' has no


   driver





Partition Implementation Status


-------------------------------





  No Partitions were found in this design.





-------------------------------





NGDBUILD Design Results Summary:


  Number of errors:     0


  Number of warnings:  79





Writing NGD file "system.ngd" ...


Total REAL time to NGDBUILD completion:  49 sec


Total CPU time to NGDBUILD completion:   45 sec





Writing NGDBUILD log file "system.bld"...





NGDBUILD done.








#----------------------------------------------#

# Starting program map

# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf 

#----------------------------------------------#

Release 14.2 - Map P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>


Using target part "6slx16csg324-3".


vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv


INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to


'2100@vm05.cs.lth.se'.


INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.


INFO:Security:54 - 'xc6slx16' is a WebPack part.


WARNING:Security:43 - No license file was found in the standard Xilinx license


directory.


WARNING:Security:44 - Since no license file was found,


       please run the Xilinx License Configuration Manager


       (xlcm or "Manage Xilinx Licenses")


       to assist in obtaining a license.


WARNING:Security:42 - Your software subscription period has lapsed. Your current


version of Xilinx tools will continue to function, but you no longer qualify for


Xilinx software updates or new releases.


----------------------------------------------------------------------


Mapping design into LUTs...


Writing file system_map.ngm...


Running directed packing...


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

4" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175c


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000091). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

6" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175d


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000092). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

1" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000172f


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000076). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

8" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175e


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000093). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

3" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001730


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000077). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

5" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001731


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000078). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

a" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001732


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000079). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

c" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001733


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000007a). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

e" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001734


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000007b). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010c

f" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001753


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008b). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010d

1" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001754


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008c). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010d

3" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001755


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008d). The constraint will be ignored.


Running delay-based LUT packing...


Updating timing models...


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report


   (.mrp).


Running timing-driven placement...


Total REAL time at the beginning of Placer: 19 secs 


Total CPU  time at the beginning of Placer: 15 secs 





Phase 1.1  Initial Placement Analysis


Phase 1.1  Initial Placement Analysis (Checksum:ab0884e9) REAL time: 21 secs 





Phase 2.7  Design Feasibility Check


Phase 2.7  Design Feasibility Check (Checksum:ab0884e9) REAL time: 21 secs 





Phase 3.31  Local Placement Optimization


Phase 3.31  Local Placement Optimization (Checksum:875ee71) REAL time: 21 secs 





Phase 4.2  Initial Placement for Architecture Specific Features





Phase 4.2  Initial Placement for Architecture Specific Features


(Checksum:6d737848) REAL time: 25 secs 





Phase 5.36  Local Placement Optimization


Phase 5.36  Local Placement Optimization (Checksum:6d737848) REAL time: 25 secs 





Phase 6.30  Global Clock Region Assignment


Phase 6.30  Global Clock Region Assignment (Checksum:6d737848) REAL time: 25 secs 





Phase 7.3  Local Placement Optimization


Phase 7.3  Local Placement Optimization (Checksum:6d737848) REAL time: 25 secs 





Phase 8.5  Local Placement Optimization


Phase 8.5  Local Placement Optimization (Checksum:6d737848) REAL time: 25 secs 





Phase 9.8  Global Placement


......................


..................................................


......................................................................................


.............................................................................


....................


Phase 9.8  Global Placement (Checksum:6a5f7172) REAL time: 1 mins 38 secs 





Phase 10.5  Local Placement Optimization


Phase 10.5  Local Placement Optimization (Checksum:6a5f7172) REAL time: 1 mins 38 secs 





Phase 11.18  Placement Optimization


Phase 11.18  Placement Optimization (Checksum:14393006) REAL time: 1 mins 45 secs 





Phase 12.5  Local Placement Optimization


Phase 12.5  Local Placement Optimization (Checksum:14393006) REAL time: 1 mins 45 secs 





Phase 13.34  Placement Validation


Phase 13.34  Placement Validation (Checksum:9d4bb8d8) REAL time: 1 mins 45 secs 





Total REAL time to Placer completion: 1 mins 46 secs 


Total CPU  time to Placer completion: 1 mins 40 secs 


Running post-placement packing...


Writing output files...





Design Summary:


Number of errors:      0


Number of warnings:   51


Slice Logic Utilization:


  Number of Slice Registers:                 3,750 out of  18,224   20


    Number used as Flip Flops:               3,743


    Number used as Latches:                      0


    Number used as Latch-thrus:                  0


    Number used as AND/OR logics:                7


  Number of Slice LUTs:                      4,017 out of   9,112   44


    Number used as logic:                    3,381 out of   9,112   37


      Number using O6 output only:           2,500


      Number using O5 output only:              71


      Number using O5 and O6:                  810


      Number used as ROM:                        0


    Number used as Memory:                     504 out of   2,176   23


      Number used as Dual Port RAM:            152


        Number using O6 output only:            88


        Number using O5 output only:             0


        Number using O5 and O6:                 64


      Number used as Single Port RAM:            0


      Number used as Shift Register:           352


        Number using O6 output only:            47


        Number using O5 output only:             1


        Number using O5 and O6:                304


    Number used exclusively as route-thrus:    132


      Number with same-slice register load:    122


      Number with same-slice carry load:        10


      Number with other load:                    0





Slice Logic Distribution:


  Number of occupied Slices:                 1,549 out of   2,278   67


  Nummber of MUXCYs used:                      860 out of   4,556   18


  Number of LUT Flip Flop pairs used:        4,597


    Number with an unused Flip Flop:         1,497 out of   4,597   32


    Number with an unused LUT:                 580 out of   4,597   12


    Number of fully used LUT-FF pairs:       2,520 out of   4,597   54


    Number of unique control sets:             159


    Number of slice register sites lost


      to control set restrictions:             609 out of  18,224    3





  A LUT Flip Flop pair for this architecture represents one LUT paired with


  one Flip Flop within a slice.  A control set is a unique combination of


  clock, reset, set, and enable signals for a registered element.


  The Slice Logic Distribution report is not meaningful if the design is


  over-mapped for a non-slice resource or if Placement fails.





IO Utilization:


  Number of bonded IOBs:                        34 out of     232   14


    Number of LOCed IOBs:                       34 out of      34  100


    IOB Flip Flops:                              4





Specific Feature Utilization:


  Number of RAMB16BWERs:                        24 out of      32   75


  Number of RAMB8BWERs:                          7 out of      64   10


  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3


    Number used as BUFIO2s:                      1


    Number used as BUFIO2_2CLKs:                 0


  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0


  Number of BUFG/BUFGMUXs:                       3 out of      16   18


    Number used as BUFGs:                        3


    Number used as BUFGMUX:                      0


  Number of DCM/DCM_CLKGENs:                     0 out of       4    0


  Number of ILOGIC2/ISERDES2s:                   1 out of     248    1


    Number used as ILOGIC2s:                     1


    Number used as ISERDES2s:                    0


  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0


  Number of OLOGIC2/OSERDES2s:                   3 out of     248    1


    Number used as OLOGIC2s:                     3


    Number used as OSERDES2s:                    0


  Number of BSCANs:                              1 out of       4   25


  Number of BUFHs:                               0 out of     128    0


  Number of BUFPLLs:                             0 out of       8    0


  Number of BUFPLL_MCBs:                         0 out of       4    0


  Number of DSP48A1s:                           12 out of      32   37


  Number of ICAPs:                               0 out of       1    0


  Number of MCBs:                                0 out of       2    0


  Number of PCILOGICSEs:                         0 out of       2    0


  Number of PLL_ADVs:                            1 out of       2   50


  Number of PMVs:                                0 out of       1    0


  Number of STARTUPs:                            0 out of       1    0


  Number of SUSPEND_SYNCs:                       0 out of       1    0





Average Fanout of Non-Clock Nets:                3.81





Peak Memory Usage:  509 MB


Total REAL time to MAP completion:  1 mins 50 secs 


Total CPU time to MAP completion:   1 mins 44 secs 





Mapping completed.


See MAP report file "system_map.mrp" for details.








#----------------------------------------------#

# Starting program par

# par -w -ol high system_map.ncd system.ncd system.pcf 

#----------------------------------------------#

Release 14.2 - par P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <C:/Xilinx/14.2/ISE_DS/EDK/data/parBmgr.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/data/parBmgr.acd>







Constraints file: system.pcf.

Loading device for application Rf_Device from file '6slx16.nph' in environment

C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv

INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to '2100@vm05.cs.lth.se'.

INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

INFO:Security:54 - 'xc6slx16' is a WebPack part.

WARNING:Security:43 - No license file was found in the standard Xilinx license directory.

WARNING:Security:44 - Since no license file was found,

       please run the Xilinx License Configuration Manager

       (xlcm or "Manage Xilinx Licenses")

       to assist in obtaining a license.

WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue

to function, but you no longer qualify for Xilinx software updates or new releases.



----------------------------------------------------------------------



Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)





Device speed data version:  "PRODUCTION 1.22 2012-07-09".







Device Utilization Summary:



Slice Logic Utilization:

  Number of Slice Registers:                 3,750 out of  18,224   20

    Number used as Flip Flops:               3,743

    Number used as Latches:                      0

    Number used as Latch-thrus:                  0

    Number used as AND/OR logics:                7

  Number of Slice LUTs:                      4,017 out of   9,112   44

    Number used as logic:                    3,381 out of   9,112   37

      Number using O6 output only:           2,500

      Number using O5 output only:              71

      Number using O5 and O6:                  810

      Number used as ROM:                        0

    Number used as Memory:                     504 out of   2,176   23

      Number used as Dual Port RAM:            152

        Number using O6 output only:            88

        Number using O5 output only:             0

        Number using O5 and O6:                 64

      Number used as Single Port RAM:            0

      Number used as Shift Register:           352

        Number using O6 output only:            47

        Number using O5 output only:             1

        Number using O5 and O6:                304

    Number used exclusively as route-thrus:    132

      Number with same-slice register load:    122

      Number with same-slice carry load:        10

      Number with other load:                    0



Slice Logic Distribution:

  Number of occupied Slices:                 1,549 out of   2,278   67

  Nummber of MUXCYs used:                      860 out of   4,556   18

  Number of LUT Flip Flop pairs used:        4,597

    Number with an unused Flip Flop:         1,497 out of   4,597   32

    Number with an unused LUT:                 580 out of   4,597   12

    Number of fully used LUT-FF pairs:       2,520 out of   4,597   54

    Number of slice register sites lost

      to control set restrictions:               0 out of  18,224    0



  A LUT Flip Flop pair for this architecture represents one LUT paired with

  one Flip Flop within a slice.  A control set is a unique combination of

  clock, reset, set, and enable signals for a registered element.

  The Slice Logic Distribution report is not meaningful if the design is

  over-mapped for a non-slice resource or if Placement fails.



IO Utilization:

  Number of bonded IOBs:                        34 out of     232   14

    Number of LOCed IOBs:                       34 out of      34  100

    IOB Flip Flops:                              4



Specific Feature Utilization:

  Number of RAMB16BWERs:                        24 out of      32   75

  Number of RAMB8BWERs:                          7 out of      64   10

  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3

    Number used as BUFIO2s:                      1

    Number used as BUFIO2_2CLKs:                 0

  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0

  Number of BUFG/BUFGMUXs:                       3 out of      16   18

    Number used as BUFGs:                        3

    Number used as BUFGMUX:                      0

  Number of DCM/DCM_CLKGENs:                     0 out of       4    0

  Number of ILOGIC2/ISERDES2s:                   1 out of     248    1

    Number used as ILOGIC2s:                     1

    Number used as ISERDES2s:                    0

  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0

  Number of OLOGIC2/OSERDES2s:                   3 out of     248    1

    Number used as OLOGIC2s:                     3

    Number used as OSERDES2s:                    0

  Number of BSCANs:                              1 out of       4   25

  Number of BUFHs:                               0 out of     128    0

  Number of BUFPLLs:                             0 out of       8    0

  Number of BUFPLL_MCBs:                         0 out of       4    0

  Number of DSP48A1s:                           12 out of      32   37

  Number of ICAPs:                               0 out of       1    0

  Number of MCBs:                                0 out of       2    0

  Number of PCILOGICSEs:                         0 out of       2    0

  Number of PLL_ADVs:                            1 out of       2   50

  Number of PMVs:                                0 out of       1    0

  Number of STARTUPs:                            0 out of       1    0

  Number of SUSPEND_SYNCs:                       0 out of       1    0





Overall effort level (-ol):   High 

Router effort level (-rl):    High 



INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx

   Command Line Tools User Guide for information on generating a TSI report.

Starting initial Timing Analysis.  REAL time: 8 secs 

Finished initial Timing Analysis.  REAL time: 8 secs 



WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM1_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<30> has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM10_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM18_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM20_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM2_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM16_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM9_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM17_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM14_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM13_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM19_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM12_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM15_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM3_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM4_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<31> has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM6_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM5_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM11_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM7_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM8_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

Starting Router





Phase  1  : 29090 unrouted;      REAL time: 11 secs 



Phase  2  : 22518 unrouted;      REAL time: 12 secs 



Phase  3  : 9359 unrouted;      REAL time: 26 secs 



Phase  4  : 9359 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 27 secs 



Updating file: system.ncd with current fully routed design.



Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 40 secs 

Total REAL time to Router completion: 40 secs 

Total CPU time to Router completion: 36 secs 



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



Generating "PAR" statistics.



**************************

Generating Clock Report

**************************



+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|     clk_100_0000MHz | BUFGMUX_X3Y13| No   | 1362 |  0.544     |  1.391      |

+---------------------+--------------+------+------+------------+-------------+

|microblaze_0_debug_D |              |      |      |            |             |

|              bg_Clk |  BUFGMUX_X2Y2| No   |   56 |  0.061     |  0.912      |

+---------------------+--------------+------+------+------------+-------------+

|clock_generator_0_CL |              |      |      |            |             |

|               KOUT1 |  BUFGMUX_X2Y3| No   |    9 |  0.488     |  1.366      |

+---------------------+--------------+------+------+------------+-------------+

|microblaze_0_debug_D |              |      |      |            |             |

|           bg_Update |         Local|      |   20 |  1.016     |  2.630      |

+---------------------+--------------+------+------+------------+-------------+



* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.



* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.



Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Number of Timing Constraints that were not applied: 1



Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.



----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   

                                            |             |    Slack   | Achievable | Errors |    Score   

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |     0.419ns|     9.581ns|       0|           0

  G_PLL0_CLKOUT0 = PERIOD TIMEGRP         " | HOLD        |     0.073ns|            |       0|           0

  clock_generator_0_clock_generator_0_SIG_P |             |            |            |        |            

  LL0_CLKOUT0" TS_sys_clk_pin         HIGH  |             |            |            |        |            

  50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |     5.707ns|    17.172ns|       0|           0

  G_PLL0_CLKOUT1 = PERIOD TIMEGRP         " | HOLD        |     0.427ns|            |       0|           0

  clock_generator_0_clock_generator_0_SIG_P |             |            |            |        |            

  LL0_CLKOUT1" TS_sys_clk_pin         * 0.2 |             |            |            |        |            

  5 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.666ns|     3.334ns|       0|           0

  pin" 100 MHz HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_Reset_path" TIG | SETUP       |         N/A|     3.753ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi4lite_0_reset_resync_path" TI | MAXDELAY    |         N/A|     4.568ns|     N/A|           0

  G                                         |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_dlmb_POR_FF_I_p | SETUP       |         N/A|     2.056ns|     N/A|           0

  ath" TIG                                  |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_ilmb_POR_FF_I_p | SETUP       |         N/A|     1.987ns|     N/A|           0

  ath" TIG                                  |             |            |            |        |            

----------------------------------------------------------------------------------------------------------





Derived Constraint Report

Review Timing Report for more details on the following derived constraints.

To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"

or "Run Timing Analysis" from Timing Analyzer (timingan).

Derived Constraints for TS_sys_clk_pin

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |

|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|

|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|TS_sys_clk_pin                 |     10.000ns|      3.334ns|      9.581ns|            0|            0|            0|       312148|

| TS_clock_generator_0_clock_gen|     40.000ns|     17.172ns|          N/A|            0|            0|          620|            0|

| erator_0_SIG_PLL0_CLKOUT1     |             |             |             |             |             |             |             |

| TS_clock_generator_0_clock_gen|     10.000ns|      9.581ns|          N/A|            0|            0|       311528|            0|

| erator_0_SIG_PLL0_CLKOUT0     |             |             |             |             |             |             |             |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+



All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 

   constraint is not analyzed due to the following: No paths covered by this 

   constraint; Other constraints intersect with this constraint; or This 

   constraint was disabled by a Path Tracing Control. Please run the Timespec 

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.





Generating Pad Report.



All signals are completely routed.



WARNING:Par:283 - There are 38 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.



Total REAL time to PAR completion: 51 secs 

Total CPU time to PAR completion: 40 secs 



Peak Memory Usage:  467 MB



Placer: Placement generated during map.

Routing: Completed - No errors found.

Timing: Completed - No errors found.



Number of error messages: 0

Number of warning messages: 40

Number of info messages: 1



Writing design to file system.ncd







PAR done!







#----------------------------------------------#

# Starting program post_par_trce

# trce -e 3 -xml system.twx system.ncd system.pcf 

#----------------------------------------------#

Release 14.2 - Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.








PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>


Loading device for application Rf_Device from file '6slx16.nph' in environment


C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.


   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3


INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more


   information, see the TSI report.  Please consult the Xilinx Command Line


   Tools User Guide for information on generating a TSI report.


--------------------------------------------------------------------------------


Release 14.2 Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -e 3 -xml system.twx


system.ncd system.pcf








Design file:              system.ncd


Physical constraint file: system.pcf


Device,speed:             xc6slx16,-3 (PRODUCTION 1.22 2012-07-09)


Report level:             error report


--------------------------------------------------------------------------------





INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).


INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in


   the unconstrained paths section(s) of the report.


INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of


   this model, and for more information on accounting for different loading conditions, please see the device datasheet.








Timing summary:


---------------





Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)





Constraints cover 312161 paths, 0 nets, and 22657 connections





Design statistics:


   Minimum period:  17.172ns (Maximum frequency:  58.234MHz)








Analysis completed Tue Oct 15 14:44:02 2013


--------------------------------------------------------------------------------





Generating Report ...





Number of warnings: 0


Number of info messages: 4


Total time: 10 secs 






xflow done!

touch __xps/system_routed

xilperl C:/Xilinx/14.2/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par

"*********************************************"

"Running Bitgen.."

"*********************************************"

cd implementation & bitgen -w -f bitgen.ut system & cd ..

Release 14.2 - Bitgen P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

Loading device for application Rf_Device from file '6slx16.nph' in environment

C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3

Opened constraints file system.pcf.



Tue Oct 15 14:44:09 2013



INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER). 

   9K Block RAM initialization data, both user defined and default, requires a

   special bit stream format.  For more information, please reference Xilinx

   Answer Record 39999.

Running DRC.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM1_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<30>> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM10_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM18_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM20_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM2_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM16_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM9_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM17_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM14_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM13_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM19_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM12_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM15_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM3_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM4_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<31>> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM6_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM5_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM11_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM7_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM8_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs

   (RAMB8BWER).  9K Block RAM initialization data, both user defined and

   default, may be incorrect and should not be used.  For more information,

   please reference Xilinx Answer Record 39999.

DRC detected 0 errors and 39 warnings.  Please see the previously displayed

individual error or warning messages for more details.

INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to

'2100@vm05.cs.lth.se'.

INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

INFO:Security:54 - 'xc6slx16' is a WebPack part.

WARNING:Security:43 - No license file was found in the standard Xilinx license

directory.

WARNING:Security:44 - Since no license file was found,

       please run the Xilinx License Configuration Manager

       (xlcm or "Manage Xilinx Licenses")

       to assist in obtaining a license.

WARNING:Security:42 - Your software subscription period has lapsed. Your current

version of Xilinx tools will continue to function, but you no longer qualify for

Xilinx software updates or new releases.



Creating bit map...

Saving bit stream in "system.bit".

Bitstream generation is complete.

Done!
Writing filter settings....
Done writing filter settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.filters
Done writing Tab View settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.2 Build EDK_P.28xd
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


********************************************************************************
At Local date and time: Tue Oct 15 15:54:29 2013
 make -f system.make exporttosdk started...
make: Inget behöver göras för "exporttosdk".

Done!

********************************************************************************
At Local date and time: Tue Oct 15 16:09:47 2013
 make -f system.make exporttosdk started...
make: Inget behöver göras för "exporttosdk".

Done!

********************************************************************************
At Local date and time: Tue Oct 15 16:16:09 2013
 make -f system.make exporttosdk started...
make: Inget behöver göras för "exporttosdk".

Done!

********************************************************************************
At Local date and time: Tue Oct 15 16:17:52 2013
 make -f system.make exporttosdk started...
make: Inget behöver göras för "exporttosdk".

Done!

********************************************************************************
At Local date and time: Tue Oct 15 16:26:10 2013
 make -f system.make exporttosdk started...
make: Inget behöver göras för "exporttosdk".

Done!

********************************************************************************
At Local date and time: Tue Oct 15 16:28:14 2013
 make -f system.make exporttosdk started...
make: Inget behöver göras för "exporttosdk".

Done!
Writing filter settings....
Done writing filter settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.filters
Done writing Tab View settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.2 Build EDK_P.28xd
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.filters
Done writing Tab View settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.2 Build EDK_P.28xd
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Assigned Driver iic 2.05.a for instance axi_iic_0
axi_iic_0 has been added to the project
ERROR:EDK:4125 - IPNAME: axi_iic, INSTANCE: axi_iic_0, PARAMETER: C_BASEADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS. 
ERROR:EDK:4125 - IPNAME: axi_iic, INSTANCE: axi_iic_0, PARAMETER: C_HIGHADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS. 
WARNING:EDK:2137 - Peripheral axi_iic_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters. 
Address Map for Processor microblaze_0
  (0000000000-0x00007fff) microblaze_0_d_bram_ctrl	microblaze_0_dlmb
  (0000000000-0x00007fff) microblaze_0_i_bram_ctrl	microblaze_0_ilmb
  (0x40000000-0x4000ffff) Push_Buttons_4Bits	axi4lite_0
  (0x40020000-0x4002ffff) LEDs_8Bits	axi4lite_0
  (0x40040000-0x4004ffff) DIP_Switches_8Bits	axi4lite_0
  (0x40600000-0x4060ffff) RS232_Uart_1	axi4lite_0
  (0x40800000-0x4080ffff) axi_iic_0	axi4lite_0
  (0x41400000-0x4140ffff) debug_module	axi4lite_0
INFO:EDK - Use Push_Buttons_4Bits as reference
INFO:EDK - Connect bus interface S_AXI to axi4lite_0
INFO:EDK - Connect clock port S_AXI_ACLK to clk_100_0000MHz
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: axi_iic_0
Overriding Xilinx file <TextEditor.cfg> with local file <C:/Xilinx/14.2/ISE_DS/EDK/data/TextEditor.cfg>

********************************************************************************
At Local date and time: Tue Oct 15 17:02:02 2013
 make -f system.make exporttosdk started...
IF NOT EXIST "SDK\SDK_Export\hw" @mkdir "SDK\SDK_Export\hw"

psf2Edward -inp system.xmp -exit_on_error -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK\SDK_Export\hw/system.xml 

Release 14.2 - psf2Edward EDK_P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.



Checking platform configuration ...

IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s) 

IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 6 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_0 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_1 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_2 - 1 master(s) : 1 slave(s) 



Checking port drivers...



Performing Clock DRCs...



Performing Reset DRCs...



Overriding system level properties...

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_1_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   21 

WARNING:EDK:4180 - PORT: FSL_M_Clk, CONNECTOR: fsl_v20_2_FSL_M_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   26 

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_0_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\mem_to_vga_v1_00_a\data\mem_to_vga_v2_1_0.mpd line

   20 

WARNING:EDK:4181 - PORT: Peripheral_Reset, CONNECTOR:

   proc_sys_reset_0_Peripheral_Reset - floating connection -

   H:\EDA385\BramFFT\system.mhs line 40 

WARNING:EDK:4181 - PORT: FSL0_M_CLK, CONNECTOR: fsl_v20_0_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 703 

WARNING:EDK:4181 - PORT: FSL1_S_CLK, CONNECTOR: fsl_v20_2_FSL_S_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 708 

WARNING:EDK:4181 - PORT: FSL1_M_CLK, CONNECTOR: fsl_v20_1_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 713 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.




Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

Conversion to XML complete.

xdsgen -inp system.xmp -report SDK\SDK_Export\hw/system.html  -make_docs_local

Release 14.2 - xdsgen EDK_P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Generated Block Diagram.

Rasterizing proc_sys_reset_0.jpg.....

Rasterizing microblaze_0_ilmb.jpg.....

Rasterizing microblaze_0_i_bram_ctrl.jpg.....

Rasterizing microblaze_0_dlmb.jpg.....

Rasterizing microblaze_0_d_bram_ctrl.jpg.....

Rasterizing microblaze_0_bram_block.jpg.....

Rasterizing microblaze_0.jpg.....

Rasterizing debug_module.jpg.....

Rasterizing clock_generator_0.jpg.....

Rasterizing axi4lite_0.jpg.....

Rasterizing RS232_Uart_1.jpg.....

Rasterizing Push_Buttons_4Bits.jpg.....

Rasterizing LEDs_8Bits.jpg.....

Rasterizing DIP_Switches_8Bits.jpg.....

Rasterizing fsl_to_axi_0.jpg.....

Rasterizing mem_to_vga_0.jpg.....

Rasterizing fsl_v20_0.jpg.....

Rasterizing fsl_v20_1.jpg.....

Rasterizing fsl_v20_2.jpg.....

Rasterizing axi_iic_0.jpg.....

Rasterizing system_blkd.jpg.....

Report generated.

Report generation completed.

"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.2 - platgen Xilinx EDK 14.2 Build EDK_P.28xd

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp

C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/ -msg __xps/ise/xmsgprops.lst

system.mhs 



WARNING:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable

   is set to '2100@vm05.cs.lth.se'.

   INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

   INFO:Security:71 - If a license for part 'xc6slx16' is available, it will be

   possible to use 'XPS_TDP' instead of 'XPS'.

   WARNING:Security:43 - No license file was found in the standard Xilinx

   license directory.

   WARNING:Security:44 - Since no license file was found,

          please run the Xilinx License Configuration Manager

          (xlcm or "Manage Xilinx Licenses")

          to assist in obtaining a license.

   WARNING:Security:42 - Your software subscription period has lapsed. Your

   current version of Xilinx tools will continue to function, but you no longer

   qualify for Xilinx software updates or new releases.





Parse H:/EDA385/BramFFT/system.mhs ...



Read MPD definitions ...



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ENDIANNESS value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 196 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ICACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 336 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 366 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_BASEFAMILY value to spartan6 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 80 



Computing clock values...

INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_0:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_1:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_2:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor microblaze_0

  (0000000000-0x00007fff) microblaze_0_d_bram_ctrl	microblaze_0_dlmb

  (0000000000-0x00007fff) microblaze_0_i_bram_ctrl	microblaze_0_ilmb

  (0x40000000-0x4000ffff) Push_Buttons_4Bits	axi4lite_0

  (0x40020000-0x4002ffff) LEDs_8Bits	axi4lite_0

  (0x40040000-0x4004ffff) DIP_Switches_8Bits	axi4lite_0

  (0x40600000-0x4060ffff) RS232_Uart_1	axi4lite_0

  (0x40800000-0x4080ffff) axi_iic_0	axi4lite_0

  (0x41400000-0x4140ffff) debug_module	axi4lite_0

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block - tool is

   overriding PARAMETER C_MEMSIZE value to 0x8000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d

   ata\bram_block_v2_1_0.mpd line 77 



Checking platform address map ...



Checking platform configuration ...

IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s) 

IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 6 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_0 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_1 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_2 - 1 master(s) : 1 slave(s) 



Checking port drivers...

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_1_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   21 

WARNING:EDK:4180 - PORT: FSL_M_Clk, CONNECTOR: fsl_v20_2_FSL_M_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd line

   26 

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_0_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   H:\EDA385\BramFFT\pcores\mem_to_vga_v1_00_a\data\mem_to_vga_v2_1_0.mpd line

   20 

WARNING:EDK:4181 - PORT: Peripheral_Reset, CONNECTOR:

   proc_sys_reset_0_Peripheral_Reset - floating connection -

   H:\EDA385\BramFFT\system.mhs line 40 

WARNING:EDK:4181 - PORT: FSL0_M_CLK, CONNECTOR: fsl_v20_0_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 703 

WARNING:EDK:4181 - PORT: FSL1_S_CLK, CONNECTOR: fsl_v20_2_FSL_S_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 708 

WARNING:EDK:4181 - PORT: FSL1_M_CLK, CONNECTOR: fsl_v20_1_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 713 



Performing Clock DRCs...

INFO:EDK:4060 - INSTANCE: fsl_v20_0, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.

INFO:EDK:4060 - INSTANCE: fsl_v20_1, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.

INFO:EDK:4060 - INSTANCE: fsl_v20_2, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_i_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_d_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_D_AXI value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 229 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ADDR_TAG_BITS value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 334 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_ADDR_TAG value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 364 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 399 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_NM_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 400 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 148 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...



Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

INFO: Setting timing constaints for microblaze_0_ilmb.


INFO: The microblaze_0_ilmb core has constraints automatically generated by XPS

in implementation/microblaze_0_ilmb_wrapper/microblaze_0_ilmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0_dlmb.


INFO: The microblaze_0_dlmb core has constraints automatically generated by XPS

in implementation/microblaze_0_dlmb_wrapper/microblaze_0_dlmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0.


INFO: The microblaze_0 core has constraints automatically generated by XPS in

implementation/microblaze_0_wrapper/microblaze_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: No asynchronous clock conversions in axi_interconnect axi4lite_0.


INFO: The fsl_v20_0 core has constraints automatically generated by XPS in

implementation/fsl_v20_0_wrapper/fsl_v20_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: The fsl_v20_1 core has constraints automatically generated by XPS in

implementation/fsl_v20_1_wrapper/fsl_v20_1_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: The fsl_v20_2 core has constraints automatically generated by XPS in

implementation/fsl_v20_2_wrapper/fsl_v20_2_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.







Modify defaults ...



Creating stub ...



Processing licensed instances ...

Completion time: 0.00 seconds



Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...

IPNAME:fsl_to_axi INSTANCE:fsl_to_axi_0 - H:\EDA385\BramFFT\system.mhs line 201

- Copying (BBD-specified) netlist files.

IPNAME:mem_to_vga INSTANCE:mem_to_vga_0 - H:\EDA385\BramFFT\system.mhs line 208

- Copying (BBD-specified) netlist files.



Managing cache ...

IPNAME:proc_sys_reset INSTANCE:proc_sys_reset_0 - H:\EDA385\BramFFT\system.mhs

line 29 - Copying cache implementation netlist

IPNAME:lmb_v10 INSTANCE:microblaze_0_ilmb - H:\EDA385\BramFFT\system.mhs line 43

- Copying cache implementation netlist

IPNAME:lmb_bram_if_cntlr INSTANCE:microblaze_0_i_bram_ctrl -

H:\EDA385\BramFFT\system.mhs line 50 - Copying cache implementation netlist

IPNAME:lmb_v10 INSTANCE:microblaze_0_dlmb - H:\EDA385\BramFFT\system.mhs line 59

- Copying cache implementation netlist

IPNAME:lmb_bram_if_cntlr INSTANCE:microblaze_0_d_bram_ctrl -

H:\EDA385\BramFFT\system.mhs line 66 - Copying cache implementation netlist

IPNAME:bram_block INSTANCE:microblaze_0_bram_block -

H:\EDA385\BramFFT\system.mhs line 75 - Copying cache implementation netlist

IPNAME:microblaze INSTANCE:microblaze_0 - H:\EDA385\BramFFT\system.mhs line 82 -

Copying cache implementation netlist

IPNAME:mdm INSTANCE:debug_module - H:\EDA385\BramFFT\system.mhs line 109 -

Copying cache implementation netlist

IPNAME:axi_uartlite INSTANCE:rs232_uart_1 - H:\EDA385\BramFFT\system.mhs line

144 - Copying cache implementation netlist

IPNAME:axi_gpio INSTANCE:push_buttons_4bits - H:\EDA385\BramFFT\system.mhs line

159 - Copying cache implementation netlist

IPNAME:axi_gpio INSTANCE:leds_8bits - H:\EDA385\BramFFT\system.mhs line 173 -

Copying cache implementation netlist

IPNAME:axi_gpio INSTANCE:dip_switches_8bits - H:\EDA385\BramFFT\system.mhs line

187 - Copying cache implementation netlist

IPNAME:fsl_to_axi INSTANCE:fsl_to_axi_0 - H:\EDA385\BramFFT\system.mhs line 201

- Copying cache implementation netlist

IPNAME:mem_to_vga INSTANCE:mem_to_vga_0 - H:\EDA385\BramFFT\system.mhs line 208

- Copying cache implementation netlist

IPNAME:fsl_v20 INSTANCE:fsl_v20_0 - H:\EDA385\BramFFT\system.mhs line 218 -

Copying cache implementation netlist

IPNAME:fsl_v20 INSTANCE:fsl_v20_1 - H:\EDA385\BramFFT\system.mhs line 225 -

Copying cache implementation netlist

IPNAME:fsl_v20 INSTANCE:fsl_v20_2 - H:\EDA385\BramFFT\system.mhs line 232 -

Copying cache implementation netlist



Elaborating instances ...

IPNAME:bram_block INSTANCE:microblaze_0_bram_block -

H:\EDA385\BramFFT\system.mhs line 75 - elaborating IP

IPNAME:clock_generator INSTANCE:clock_generator_0 - H:\EDA385\BramFFT\system.mhs

line 122 - elaborating IP

ClkGen elaborate status: PASSED


----------------------------------------


----------------------------------------




Writing HDL for elaborated instances ...



Inserting wrapper level ...

Completion time: 0.00 seconds



Constructing platform-level connectivity ...

Completion time: 0.00 seconds



Writing (top-level) BMM ...



Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...



INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 

INSTANCE:clock_generator_0 - H:\EDA385\BramFFT\system.mhs line 122 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:axi4lite_0 - H:\EDA385\BramFFT\system.mhs line 136 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:axi_iic_0 - H:\EDA385\BramFFT\system.mhs line 241 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Running NGCBUILD ...

IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -

H:\EDA385\BramFFT\system.mhs line 122 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc

../system_clock_generator_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/clock_generator_0_wrapper/system_clock_generat

or_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  3 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi4lite_0_wrapper INSTANCE:axi4lite_0 -

H:\EDA385\BramFFT\system.mhs line 136 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_axi4lite_0_wrapper.ngc

../system_axi4lite_0_wrapper



Reading NGO file

"H:/EDA385/BramFFT/implementation/axi4lite_0_wrapper/system_axi4lite_0_wrapper.n

gc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi4lite_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  3 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_axi4lite_0_wrapper.blc"...



NGCBUILD done.

INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

   If any constraint needs to be overridden, this should be done by modifying

   the data/system.ucf file.



Rebuilding cache ...



Total run time: 80.00 seconds

"Running synthesis..."

cd synthesis & synthesis.cmd

"xst -ifn "system_xst.scr" -intstyle silent"

"Running XST synthesis ..."

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

"XST completed"

"*********************************************"

"Running Xilinx Implementation tools.."

"*********************************************"

xflow -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

Release 14.2 - Xflow P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

 

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Using Flow File: H:/EDA385/BramFFT/implementation/fpga.flw 

Using Option File(s): 

 H:/EDA385/BramFFT/implementation/xflow.opt 



Creating Script File ... 



#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc6slx16csg324-3 -nt timestamp -bm system.bmm

"H:/EDA385/BramFFT/implementation/system.ngc" -uc system.ucf system.ngd 

#----------------------------------------------#

Release 14.2 - ngdbuild P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>





Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p


xc6slx16csg324-3 -nt timestamp -bm system.bmm


H:/EDA385/BramFFT/implementation/system.ngc -uc system.ucf system.ngd





Reading NGO file "H:/EDA385/BramFFT/implementation/system.ngc" ...


Loading design module


"H:/EDA385/BramFFT/implementation/system_push_buttons_4bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_dip_switches_8bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_rs232_uart_1_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_proc_sys_reset_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_clock_generator_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_axi4lite_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_v20_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_v20_1_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_v20_2_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_mem_to_vga_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_i_bram_ctrl_wrapper.ngc"..


.


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_d_bram_ctrl_wrapper.ngc"..


.


Loading design module


"H:/EDA385/BramFFT/implementation/system_debug_module_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_fsl_to_axi_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_leds_8bits_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_axi_iic_0_wrapper.ngc"...


Loading design module


"H:/EDA385/BramFFT/implementation/system_microblaze_0_bram_block_wrapper.ngc"...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ncf" to


module "microblaze_0_ilmb"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ncf" to


module "microblaze_0_dlmb"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_axi4lite_0_wrapper.ncf" to module


"axi4lite_0"...


Checking Constraint Associations...


Applying constraints in


"H:/EDA385/BramFFT/implementation/system_microblaze_0_wrapper.ncf" to module


"microblaze_0"...


Checking Constraint Associations...


Gathering constraint information from source properties...


Done.





Annotating constraints to design from ucf file "system.ucf" ...


Resolving constraint associations...


Checking Constraint Associations...


WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi4lite_0/axi4lite_0\/si_converter_bank\/gen_conv_sl


   ot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_INV_0 TNM =


   FFS:axi4lite_0_reset_resync>: No instances of type FFS were found under block


   "axi4lite_0/axi4lite_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/int

erconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP axi4lite_0_reset_source = FFS


   PADS CPUS;>: CPUS "*" does not match any design objects.





WARNING:ConstraintSystem:194 - The TNM 'axi4lite_0_reset_resync', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification


   'TS_sys_clk_pin', was traced into PLL_ADV instance


   clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM


   groups and period specifications were generated at the PLL_ADV output(s): 


   CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT1 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT1" TS_sys_clk_pin


   * 0.25 HIGH 50>





INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification


   'TS_sys_clk_pin', was traced into PLL_ADV instance


   clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM


   groups and period specifications were generated at the PLL_ADV output(s): 


   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0" TS_sys_clk_pin


   HIGH 50>





Done...





Processing BMM file "system.bmm" ...





Checking expanded design ...


WARNING:NgdBuild:443 - SFF primitive


   'microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Decode_I/Using_FPGA.


   Gen_Bits[27].MEM_EX_Result_Inst' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000050


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000055


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000066


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000067


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000067


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk00000fe


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_0/axi_iic_0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:452 - logical net 'fsl_v20_2_FSL_M_Control' has no driver


WARNING:NgdBuild:452 - logical net


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/sig0000073d' has no


   driver





Partition Implementation Status


-------------------------------





  No Partitions were found in this design.





-------------------------------





NGDBUILD Design Results Summary:


  Number of errors:     0


  Number of warnings:  80





Writing NGD file "system.ngd" ...


Total REAL time to NGDBUILD completion:  50 sec


Total CPU time to NGDBUILD completion:   45 sec





Writing NGDBUILD log file "system.bld"...





NGDBUILD done.








#----------------------------------------------#

# Starting program map

# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf 

#----------------------------------------------#

Release 14.2 - Map P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>


Using target part "6slx16csg324-3".


vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv


INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to


'2100@vm05.cs.lth.se'.


INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.


INFO:Security:54 - 'xc6slx16' is a WebPack part.


WARNING:Security:43 - No license file was found in the standard Xilinx license


directory.


WARNING:Security:44 - Since no license file was found,


       please run the Xilinx License Configuration Manager


       (xlcm or "Manage Xilinx Licenses")


       to assist in obtaining a license.


WARNING:Security:42 - Your software subscription period has lapsed. Your current


version of Xilinx tools will continue to function, but you no longer qualify for


Xilinx software updates or new releases.


----------------------------------------------------------------------


Mapping design into LUTs...


Writing file system_map.ngm...


Running directed packing...


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

4" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175c


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000091). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

6" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175d


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000092). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

1" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000172f


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000076). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

8" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175e


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000093). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

3" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001730


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000077). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

5" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001731


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000078). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

a" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001732


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000079). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

c" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001733


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000007a). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

e" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001734


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000007b). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010c

f" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001753


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008b). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010d

1" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001754


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008c). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010d

3" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001755


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008d). The constraint will be ignored.


Running delay-based LUT packing...


Updating timing models...


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report


   (.mrp).


Running timing-driven placement...


Total REAL time at the beginning of Placer: 23 secs 


Total CPU  time at the beginning of Placer: 16 secs 





Phase 1.1  Initial Placement Analysis


Phase 1.1  Initial Placement Analysis (Checksum:30844a5a) REAL time: 26 secs 





Phase 2.7  Design Feasibility Check


INFO:Place:834 - Only a subset of IOs are locked. Out of 37 IOs, 36 are locked


   and 1 are not locked. If you would like to print the names of these IOs,


   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 


Phase 2.7  Design Feasibility Check (Checksum:30844a5a) REAL time: 26 secs 





Phase 3.31  Local Placement Optimization


Phase 3.31  Local Placement Optimization (Checksum:bbd1c9a2) REAL time: 26 secs 





Phase 4.2  Initial Placement for Architecture Specific Features


....


Phase 4.2  Initial Placement for Architecture Specific Features


(Checksum:68ed4049) REAL time: 31 secs 





Phase 5.36  Local Placement Optimization


Phase 5.36  Local Placement Optimization (Checksum:68ed4049) REAL time: 31 secs 





Phase 6.30  Global Clock Region Assignment


Phase 6.30  Global Clock Region Assignment (Checksum:68ed4049) REAL time: 31 secs 





Phase 7.3  Local Placement Optimization


....


Phase 7.3  Local Placement Optimization (Checksum:86da60c9) REAL time: 31 secs 





Phase 8.5  Local Placement Optimization


Phase 8.5  Local Placement Optimization (Checksum:68f5e139) REAL time: 31 secs 





Phase 9.8  Global Placement


.....................


............................................................


..................................................................


.................................................................................


.............................


Phase 9.8  Global Placement (Checksum:efbc0b5c) REAL time: 1 mins 43 secs 





Phase 10.5  Local Placement Optimization


Phase 10.5  Local Placement Optimization (Checksum:efbc0b5c) REAL time: 1 mins 43 secs 





Phase 11.18  Placement Optimization


Phase 11.18  Placement Optimization (Checksum:2cdcaed6) REAL time: 2 mins 6 secs 





Phase 12.5  Local Placement Optimization


Phase 12.5  Local Placement Optimization (Checksum:2cdcaed6) REAL time: 2 mins 7 secs 





Phase 13.34  Placement Validation


Phase 13.34  Placement Validation (Checksum:caee3034) REAL time: 2 mins 7 secs 





Total REAL time to Placer completion: 2 mins 7 secs 


Total CPU  time to Placer completion: 1 mins 58 secs 


Running post-placement packing...


Writing output files...





Design Summary:


Number of errors:      0


Number of warnings:   51


Slice Logic Utilization:


  Number of Slice Registers:                 4,111 out of  18,224   22


    Number used as Flip Flops:               4,104


    Number used as Latches:                      0


    Number used as Latch-thrus:                  0


    Number used as AND/OR logics:                7


  Number of Slice LUTs:                      4,446 out of   9,112   48


    Number used as logic:                    3,789 out of   9,112   41


      Number using O6 output only:           2,819


      Number using O5 output only:              72


      Number using O5 and O6:                  898


      Number used as ROM:                        0


    Number used as Memory:                     516 out of   2,176   23


      Number used as Dual Port RAM:            152


        Number using O6 output only:            88


        Number using O5 output only:             0


        Number using O5 and O6:                 64


      Number used as Single Port RAM:            0


      Number used as Shift Register:           364


        Number using O6 output only:            51


        Number using O5 output only:             1


        Number using O5 and O6:                312


    Number used exclusively as route-thrus:    141


      Number with same-slice register load:    128


      Number with same-slice carry load:        13


      Number with other load:                    0





Slice Logic Distribution:


  Number of occupied Slices:                 1,645 out of   2,278   72


  Nummber of MUXCYs used:                      908 out of   4,556   19


  Number of LUT Flip Flop pairs used:        5,014


    Number with an unused Flip Flop:         1,610 out of   5,014   32


    Number with an unused LUT:                 568 out of   5,014   11


    Number of fully used LUT-FF pairs:       2,836 out of   5,014   56


    Number of unique control sets:             197


    Number of slice register sites lost


      to control set restrictions:             772 out of  18,224    4





  A LUT Flip Flop pair for this architecture represents one LUT paired with


  one Flip Flop within a slice.  A control set is a unique combination of


  clock, reset, set, and enable signals for a registered element.


  The Slice Logic Distribution report is not meaningful if the design is


  over-mapped for a non-slice resource or if Placement fails.





IO Utilization:


  Number of bonded IOBs:                        37 out of     232   15


    Number of LOCed IOBs:                       36 out of      37   97


    IOB Flip Flops:                              4





Specific Feature Utilization:


  Number of RAMB16BWERs:                        24 out of      32   75


  Number of RAMB8BWERs:                          7 out of      64   10


  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3


    Number used as BUFIO2s:                      1


    Number used as BUFIO2_2CLKs:                 0


  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0


  Number of BUFG/BUFGMUXs:                       3 out of      16   18


    Number used as BUFGs:                        3


    Number used as BUFGMUX:                      0


  Number of DCM/DCM_CLKGENs:                     0 out of       4    0


  Number of ILOGIC2/ISERDES2s:                   1 out of     248    1


    Number used as ILOGIC2s:                     1


    Number used as ISERDES2s:                    0


  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0


  Number of OLOGIC2/OSERDES2s:                   3 out of     248    1


    Number used as OLOGIC2s:                     3


    Number used as OSERDES2s:                    0


  Number of BSCANs:                              1 out of       4   25


  Number of BUFHs:                               0 out of     128    0


  Number of BUFPLLs:                             0 out of       8    0


  Number of BUFPLL_MCBs:                         0 out of       4    0


  Number of DSP48A1s:                           12 out of      32   37


  Number of ICAPs:                               0 out of       1    0


  Number of MCBs:                                0 out of       2    0


  Number of PCILOGICSEs:                         0 out of       2    0


  Number of PLL_ADVs:                            1 out of       2   50


  Number of PMVs:                                0 out of       1    0


  Number of STARTUPs:                            0 out of       1    0


  Number of SUSPEND_SYNCs:                       0 out of       1    0





Average Fanout of Non-Clock Nets:                3.83





Peak Memory Usage:  512 MB


Total REAL time to MAP completion:  2 mins 12 secs 


Total CPU time to MAP completion:   2 mins 2 secs 





Mapping completed.


See MAP report file "system_map.mrp" for details.








#----------------------------------------------#

# Starting program par

# par -w -ol high system_map.ncd system.ncd system.pcf 

#----------------------------------------------#

Release 14.2 - par P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <C:/Xilinx/14.2/ISE_DS/EDK/data/parBmgr.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/data/parBmgr.acd>







Constraints file: system.pcf.

Loading device for application Rf_Device from file '6slx16.nph' in environment

C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv

INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to '2100@vm05.cs.lth.se'.

INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

INFO:Security:54 - 'xc6slx16' is a WebPack part.

WARNING:Security:43 - No license file was found in the standard Xilinx license directory.

WARNING:Security:44 - Since no license file was found,

       please run the Xilinx License Configuration Manager

       (xlcm or "Manage Xilinx Licenses")

       to assist in obtaining a license.

WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue

to function, but you no longer qualify for Xilinx software updates or new releases.



----------------------------------------------------------------------



Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)





Device speed data version:  "PRODUCTION 1.22 2012-07-09".







Device Utilization Summary:



Slice Logic Utilization:

  Number of Slice Registers:                 4,111 out of  18,224   22

    Number used as Flip Flops:               4,104

    Number used as Latches:                      0

    Number used as Latch-thrus:                  0

    Number used as AND/OR logics:                7

  Number of Slice LUTs:                      4,446 out of   9,112   48

    Number used as logic:                    3,789 out of   9,112   41

      Number using O6 output only:           2,819

      Number using O5 output only:              72

      Number using O5 and O6:                  898

      Number used as ROM:                        0

    Number used as Memory:                     516 out of   2,176   23

      Number used as Dual Port RAM:            152

        Number using O6 output only:            88

        Number using O5 output only:             0

        Number using O5 and O6:                 64

      Number used as Single Port RAM:            0

      Number used as Shift Register:           364

        Number using O6 output only:            51

        Number using O5 output only:             1

        Number using O5 and O6:                312

    Number used exclusively as route-thrus:    141

      Number with same-slice register load:    128

      Number with same-slice carry load:        13

      Number with other load:                    0



Slice Logic Distribution:

  Number of occupied Slices:                 1,645 out of   2,278   72

  Nummber of MUXCYs used:                      908 out of   4,556   19

  Number of LUT Flip Flop pairs used:        5,014

    Number with an unused Flip Flop:         1,610 out of   5,014   32

    Number with an unused LUT:                 568 out of   5,014   11

    Number of fully used LUT-FF pairs:       2,836 out of   5,014   56

    Number of slice register sites lost

      to control set restrictions:               0 out of  18,224    0



  A LUT Flip Flop pair for this architecture represents one LUT paired with

  one Flip Flop within a slice.  A control set is a unique combination of

  clock, reset, set, and enable signals for a registered element.

  The Slice Logic Distribution report is not meaningful if the design is

  over-mapped for a non-slice resource or if Placement fails.



IO Utilization:

  Number of bonded IOBs:                        37 out of     232   15

    Number of LOCed IOBs:                       36 out of      37   97

    IOB Flip Flops:                              4



Specific Feature Utilization:

  Number of RAMB16BWERs:                        24 out of      32   75

  Number of RAMB8BWERs:                          7 out of      64   10

  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3

    Number used as BUFIO2s:                      1

    Number used as BUFIO2_2CLKs:                 0

  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0

  Number of BUFG/BUFGMUXs:                       3 out of      16   18

    Number used as BUFGs:                        3

    Number used as BUFGMUX:                      0

  Number of DCM/DCM_CLKGENs:                     0 out of       4    0

  Number of ILOGIC2/ISERDES2s:                   1 out of     248    1

    Number used as ILOGIC2s:                     1

    Number used as ISERDES2s:                    0

  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0

  Number of OLOGIC2/OSERDES2s:                   3 out of     248    1

    Number used as OLOGIC2s:                     3

    Number used as OSERDES2s:                    0

  Number of BSCANs:                              1 out of       4   25

  Number of BUFHs:                               0 out of     128    0

  Number of BUFPLLs:                             0 out of       8    0

  Number of BUFPLL_MCBs:                         0 out of       4    0

  Number of DSP48A1s:                           12 out of      32   37

  Number of ICAPs:                               0 out of       1    0

  Number of MCBs:                                0 out of       2    0

  Number of PCILOGICSEs:                         0 out of       2    0

  Number of PLL_ADVs:                            1 out of       2   50

  Number of PMVs:                                0 out of       1    0

  Number of STARTUPs:                            0 out of       1    0

  Number of SUSPEND_SYNCs:                       0 out of       1    0





Overall effort level (-ol):   High 

Router effort level (-rl):    High 



INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx

   Command Line Tools User Guide for information on generating a TSI report.

Starting initial Timing Analysis.  REAL time: 10 secs 

Finished initial Timing Analysis.  REAL time: 10 secs 



WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM7_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM8_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM16_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM10_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM9_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM5_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM2_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM1_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM15_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM19_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<31> has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM6_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM14_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM20_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<30> has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM12_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM11_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM17_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM3_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM13_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM18_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM4_RAMD_O has no load.  PAR

   will not attempt to route this signal.

Starting Router





Phase  1  : 31812 unrouted;      REAL time: 13 secs 



Phase  2  : 24922 unrouted;      REAL time: 14 secs 



Phase  3  : 10470 unrouted;      REAL time: 29 secs 



Phase  4  : 10470 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 30 secs 



Updating file: system.ncd with current fully routed design.



Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 



Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 



Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 



Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 



Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 



Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 46 secs 

Total REAL time to Router completion: 46 secs 

Total CPU time to Router completion: 41 secs 



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



Generating "PAR" statistics.



**************************

Generating Clock Report

**************************



+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|     clk_100_0000MHz | BUFGMUX_X3Y13| No   | 1489 |  0.543     |  1.390      |

+---------------------+--------------+------+------+------------+-------------+

|microblaze_0_debug_D |              |      |      |            |             |

|              bg_Clk |  BUFGMUX_X2Y2| No   |   60 |  0.056     |  0.909      |

+---------------------+--------------+------+------+------------+-------------+

|clock_generator_0_CL |              |      |      |            |             |

|               KOUT1 |  BUFGMUX_X2Y3| No   |    9 |  0.498     |  1.366      |

+---------------------+--------------+------+------+------------+-------------+

|microblaze_0_debug_D |              |      |      |            |             |

|           bg_Update |         Local|      |   21 |  3.507     |  4.797      |

+---------------------+--------------+------+------+------------+-------------+



* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.



* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.



Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Number of Timing Constraints that were not applied: 1



Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.



----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   

                                            |             |    Slack   | Achievable | Errors |    Score   

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |     0.109ns|     9.891ns|       0|           0

  G_PLL0_CLKOUT0 = PERIOD TIMEGRP         " | HOLD        |     0.167ns|            |       0|           0

  clock_generator_0_clock_generator_0_SIG_P |             |            |            |        |            

  LL0_CLKOUT0" TS_sys_clk_pin         HIGH  |             |            |            |        |            

  50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |     6.227ns|    15.092ns|       0|           0

  G_PLL0_CLKOUT1 = PERIOD TIMEGRP         " | HOLD        |     0.349ns|            |       0|           0

  clock_generator_0_clock_generator_0_SIG_P |             |            |            |        |            

  LL0_CLKOUT1" TS_sys_clk_pin         * 0.2 |             |            |            |        |            

  5 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.666ns|     3.334ns|       0|           0

  pin" 100 MHz HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_Reset_path" TIG | SETUP       |         N/A|     2.033ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi4lite_0_reset_resync_path" TI | MAXDELAY    |         N/A|     4.601ns|     N/A|           0

  G                                         |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_dlmb_POR_FF_I_p | SETUP       |         N/A|     1.970ns|     N/A|           0

  ath" TIG                                  |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_ilmb_POR_FF_I_p | SETUP       |         N/A|     1.901ns|     N/A|           0

  ath" TIG                                  |             |            |            |        |            

----------------------------------------------------------------------------------------------------------





Derived Constraint Report

Review Timing Report for more details on the following derived constraints.

To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"

or "Run Timing Analysis" from Timing Analyzer (timingan).

Derived Constraints for TS_sys_clk_pin

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |

|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|

|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|TS_sys_clk_pin                 |     10.000ns|      3.334ns|      9.891ns|            0|            0|            0|       325100|

| TS_clock_generator_0_clock_gen|     40.000ns|     15.092ns|          N/A|            0|            0|          620|            0|

| erator_0_SIG_PLL0_CLKOUT1     |             |             |             |             |             |             |             |

| TS_clock_generator_0_clock_gen|     10.000ns|      9.891ns|          N/A|            0|            0|       324480|            0|

| erator_0_SIG_PLL0_CLKOUT0     |             |             |             |             |             |             |             |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+



All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 

   constraint is not analyzed due to the following: No paths covered by this 

   constraint; Other constraints intersect with this constraint; or This 

   constraint was disabled by a Path Tracing Control. Please run the Timespec 

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.





Generating Pad Report.



All signals are completely routed.



WARNING:Par:283 - There are 38 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.



Total REAL time to PAR completion: 57 secs 

Total CPU time to PAR completion: 43 secs 



Peak Memory Usage:  478 MB



Placer: Placement generated during map.

Routing: Completed - No errors found.

Timing: Completed - No errors found.



Number of error messages: 0

Number of warning messages: 40

Number of info messages: 1



Writing design to file system.ncd







PAR done!







#----------------------------------------------#

# Starting program post_par_trce

# trce -e 3 -xml system.twx system.ncd system.pcf 

#----------------------------------------------#

Release 14.2 - Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.








PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>


Loading device for application Rf_Device from file '6slx16.nph' in environment


C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.


   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3


INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more


   information, see the TSI report.  Please consult the Xilinx Command Line


   Tools User Guide for information on generating a TSI report.


--------------------------------------------------------------------------------


Release 14.2 Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -e 3 -xml system.twx


system.ncd system.pcf








Design file:              system.ncd


Physical constraint file: system.pcf


Device,speed:             xc6slx16,-3 (PRODUCTION 1.22 2012-07-09)


Report level:             error report


--------------------------------------------------------------------------------





INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).


INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in


   the unconstrained paths section(s) of the report.


INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of


   this model, and for more information on accounting for different loading conditions, please see the device datasheet.








Timing summary:


---------------





Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)





Constraints cover 325113 paths, 0 nets, and 25175 connections





Design statistics:


   Minimum period:  15.092ns (Maximum frequency:  66.260MHz)








Analysis completed Tue Oct 15 17:08:41 2013


--------------------------------------------------------------------------------





Generating Report ...





Number of warnings: 0


Number of info messages: 4


Total time: 10 secs 






xflow done!

touch __xps/system_routed

xilperl C:/Xilinx/14.2/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par

"*********************************************"

"Running Bitgen.."

"*********************************************"

cd implementation & bitgen -w -f bitgen.ut system & cd ..

Release 14.2 - Bitgen P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

Loading device for application Rf_Device from file '6slx16.nph' in environment

C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3

Opened constraints file system.pcf.



Tue Oct 15 17:08:48 2013



INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER). 

   9K Block RAM initialization data, both user defined and default, requires a

   special bit stream format.  For more information, please reference Xilinx

   Answer Record 39999.

Running DRC.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM7_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM8_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM16_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM10_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM9_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM5_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM2_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM1_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM15_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM19_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<31>> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM6_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM14_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM20_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<30>> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM12_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM11_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM17_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM3_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM13_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM18_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM4_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs

   (RAMB8BWER).  9K Block RAM initialization data, both user defined and

   default, may be incorrect and should not be used.  For more information,

   please reference Xilinx Answer Record 39999.

DRC detected 0 errors and 39 warnings.  Please see the previously displayed

individual error or warning messages for more details.

INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to

'2100@vm05.cs.lth.se'.

INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

INFO:Security:54 - 'xc6slx16' is a WebPack part.

WARNING:Security:43 - No license file was found in the standard Xilinx license

directory.

WARNING:Security:44 - Since no license file was found,

       please run the Xilinx License Configuration Manager

       (xlcm or "Manage Xilinx Licenses")

       to assist in obtaining a license.

WARNING:Security:42 - Your software subscription period has lapsed. Your current

version of Xilinx tools will continue to function, but you no longer qualify for

Xilinx software updates or new releases.



Creating bit map...

Saving bit stream in "system.bit".

Bitstream generation is complete.

Done!

********************************************************************************
At Local date and time: Tue Oct 15 17:10:17 2013
 make -f system.make exporttosdk started...
make: Inget behöver göras för "exporttosdk".

Done!

********************************************************************************
At Local date and time: Tue Oct 15 17:11:04 2013
 make -f system.make exporttosdk started...
make: Inget behöver göras för "exporttosdk".

Done!

********************************************************************************
At Local date and time: Tue Oct 15 17:11:05 2013
 xsdk.exe -hwspec \\tiger\et09mo0\EDA385\BramFFT\SDK\SDK_Export\hw\system.xml started...
Xilinx Software Development Kit

Xilinx EDK 14.2 Build EDK_P.28xd

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Done!
Writing filter settings....
Done writing filter settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.filters
Done writing Tab View settings to:
	\\tiger\et09mo0\EDA385\BramFFT\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.2 Build EDK_P.28xd
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


********************************************************************************
At Local date and time: Wed Oct 16 14:49:16 2013
 make -f system.make exporttosdk started...
make: Inget behöver göras för "exporttosdk".

Done!

********************************************************************************
At Local date and time: Wed Oct 16 14:49:27 2013
 make -f system.make exporttosdk started...
make: Inget behöver göras för "exporttosdk".

Done!

********************************************************************************
At Local date and time: Wed Oct 16 14:49:28 2013
 xsdk.exe -hwspec C:\Temp\Spgram4\BramFFT\SDK\SDK_Export\hw\system.xml started...
Xilinx Software Development Kit

Xilinx EDK 14.2 Build EDK_P.28xd

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Done!
Overriding Xilinx file <TextEditor.cfg> with local file <C:/Xilinx/14.2/ISE_DS/EDK/data/TextEditor.cfg>

********************************************************************************
At Local date and time: Wed Oct 16 15:08:05 2013
 make -f system.make netlistclean started...
rm -f implementation/system.ngc

rm -f implementation/system_proc_sys_reset_0_wrapper.ngc implementation/system_microblaze_0_ilmb_wrapper.ngc implementation/system_microblaze_0_i_bram_ctrl_wrapper.ngc implementation/system_microblaze_0_dlmb_wrapper.ngc implementation/system_microblaze_0_d_bram_ctrl_wrapper.ngc implementation/system_microblaze_0_bram_block_wrapper.ngc implementation/system_microblaze_0_wrapper.ngc implementation/system_debug_module_wrapper.ngc implementation/system_clock_generator_0_wrapper.ngc implementation/system_axi4lite_0_wrapper.ngc implementation/system_rs232_uart_1_wrapper.ngc implementation/system_push_buttons_4bits_wrapper.ngc implementation/system_leds_8bits_wrapper.ngc implementation/system_dip_switches_8bits_wrapper.ngc implementation/system_fsl_to_axi_0_wrapper.ngc implementation/system_mem_to_vga_0_wrapper.ngc implementation/system_fsl_v20_0_wrapper.ngc implementation/system_fsl_v20_1_wrapper.ngc implementation/system_fsl_v20_2_wrapper.ngc implementation/system_axi_iic_0_wrapper.ngc

rm -f platgen.log

rm -f __xps/ise/_xmsgs/platgen.xmsgs

rm -f implementation/system.bmm

rm -rf implementation/cache

Done!
Writing filter settings....
Done writing filter settings to:
	C:\Temp\Spgram4\BramFFT\etc\system.filters
Done writing Tab View settings to:
	C:\Temp\Spgram4\BramFFT\etc\system.gui
Writing filter settings....
Done writing filter settings to:
	C:\Temp\Spgram4\BramFFT\etc\system.filters
Done writing Tab View settings to:
	C:\Temp\Spgram4\BramFFT\etc\system.gui

********************************************************************************
At Local date and time: Wed Oct 16 15:08:34 2013
 make -f system.make exporttosdk started...
"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.2 - platgen Xilinx EDK 14.2 Build EDK_P.28xd

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc6slx16csg324-3 -lang vhdl -intstyle default -lp

C:/Xilinx/BSP/Nexys3_AXI_BSB_Support/lib/ -msg __xps/ise/xmsgprops.lst

system.mhs 



WARNING:EDK - INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable

   is set to '2100@vm05.cs.lth.se'.

   INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

   INFO:Security:71 - If a license for part 'xc6slx16' is available, it will be

   possible to use 'XPS_TDP' instead of 'XPS'.

   WARNING:Security:43 - No license file was found in the standard Xilinx

   license directory.

   WARNING:Security:44 - Since no license file was found,

          please run the Xilinx License Configuration Manager

          (xlcm or "Manage Xilinx Licenses")

          to assist in obtaining a license.

   WARNING:Security:42 - Your software subscription period has lapsed. Your

   current version of Xilinx tools will continue to function, but you no longer

   qualify for Xilinx software updates or new releases.





Parse C:/Temp/Spgram4/BramFFT/system.mhs ...



Read MPD definitions ...



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ENDIANNESS value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 196 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ICACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 336 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_USE_FSL value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 366 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_BASEFAMILY value to spartan6 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 80 



Computing clock values...

INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_i_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:740 - Cannot determine the input clock associated with port :

   microblaze_0_d_bram_ctrl:BRAM_Clk_A. Clock DRCs will not be performed on this

   core and cores connected to it. 

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_0:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_1:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.

INFO:EDK:1039 - Did not update the value for parameter:

   fsl_v20_2:C_READ_CLOCK_PERIOD. Top-level frequency could not be propagated to

   this IP. Please make sure that you have specified the frequency of the

   top-level clock port, and that the clocks are properly connected.



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor microblaze_0

  (0000000000-0x00007fff) microblaze_0_d_bram_ctrl	microblaze_0_dlmb

  (0000000000-0x00007fff) microblaze_0_i_bram_ctrl	microblaze_0_ilmb

  (0x40000000-0x4000ffff) Push_Buttons_4Bits	axi4lite_0

  (0x40020000-0x4002ffff) LEDs_8Bits	axi4lite_0

  (0x40040000-0x4004ffff) DIP_Switches_8Bits	axi4lite_0

  (0x40600000-0x4060ffff) RS232_Uart_1	axi4lite_0

  (0x40800000-0x4080ffff) axi_iic_0	axi4lite_0

  (0x41400000-0x4140ffff) debug_module	axi4lite_0

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_ilmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: lmb_v10, INSTANCE:microblaze_0_dlmb - tool is overriding

   PARAMETER C_LMB_NUM_SLAVES value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_b\data

   \lmb_v10_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: bram_block, INSTANCE:microblaze_0_bram_block - tool is

   overriding PARAMETER C_MEMSIZE value to 0x8000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\d

   ata\bram_block_v2_1_0.mpd line 77 



Checking platform address map ...



Checking platform configuration ...

IPNAME: lmb_v10, INSTANCE: microblaze_0_ilmb - 1 master(s) : 1 slave(s) 

IPNAME: lmb_v10, INSTANCE: microblaze_0_dlmb - 1 master(s) : 1 slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi4lite_0 - 1 master(s) : 6 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_0 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_1 - 1 master(s) : 1 slave(s) 

IPNAME: fsl_v20, INSTANCE: fsl_v20_2 - 1 master(s) : 1 slave(s) 



Checking port drivers...

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_1_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   C:\Temp\Spgram4\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd

   line 21 

WARNING:EDK:4180 - PORT: FSL_M_Clk, CONNECTOR: fsl_v20_2_FSL_M_Clk - No driver

   found. Port will be driven to GND -

   C:\Temp\Spgram4\BramFFT\pcores\fsl_to_axi_v1_00_a\data\fsl_to_axi_v2_1_0.mpd

   line 26 

WARNING:EDK:4180 - PORT: FSL_S_Clk, CONNECTOR: fsl_v20_0_FSL_S_Clk - No driver

   found. Port will be driven to GND -

   C:\Temp\Spgram4\BramFFT\pcores\mem_to_vga_v1_00_a\data\mem_to_vga_v2_1_0.mpd

   line 20 

WARNING:EDK:4181 - PORT: Peripheral_Reset, CONNECTOR:

   proc_sys_reset_0_Peripheral_Reset - floating connection -

   C:\Temp\Spgram4\BramFFT\system.mhs line 40 

WARNING:EDK:4181 - PORT: FSL0_M_CLK, CONNECTOR: fsl_v20_0_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 703 

WARNING:EDK:4181 - PORT: FSL1_S_CLK, CONNECTOR: fsl_v20_2_FSL_S_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 708 

WARNING:EDK:4181 - PORT: FSL1_M_CLK, CONNECTOR: fsl_v20_1_FSL_M_Clk - floating

   connection -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 713 



Performing Clock DRCs...

INFO:EDK:4060 - INSTANCE: fsl_v20_0, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.

INFO:EDK:4060 - INSTANCE: fsl_v20_1, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.

INFO:EDK:4060 - INSTANCE: fsl_v20_2, PARAMETER: C_READ_CLOCK_PERIOD - Did not

   implement clock DRCs for the parameter. Top-level frequency could not be

   propagated to this IP. Please make sure that you have specified the frequency

   of the top-level clock port, and that the clocks are properly connected.



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_i_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: lmb_bram_if_cntlr, INSTANCE:microblaze_0_d_bram_ctrl -

   tcl is overriding PARAMETER C_MASK value to 0x40000000 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3

   _10_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 91 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_D_AXI value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 229 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_ADDR_TAG_BITS value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 334 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_DCACHE_ADDR_TAG value to 0 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 364 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 399 

INFO:EDK:4130 - IPNAME: microblaze, INSTANCE:microblaze_0 - tcl is overriding

   PARAMETER C_USE_EXT_NM_BRK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_40_a\d

   ata\microblaze_v2_1_0.mpd line 400 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi4lite_0.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi4lite_0 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 148 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...



Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

INFO: Setting timing constaints for microblaze_0_ilmb.


INFO: The microblaze_0_ilmb core has constraints automatically generated by XPS

in implementation/microblaze_0_ilmb_wrapper/microblaze_0_ilmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0_dlmb.


INFO: The microblaze_0_dlmb core has constraints automatically generated by XPS

in implementation/microblaze_0_dlmb_wrapper/microblaze_0_dlmb_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: Setting timing constaints for microblaze_0.


INFO: The microblaze_0 core has constraints automatically generated by XPS in

implementation/microblaze_0_wrapper/microblaze_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: No asynchronous clock conversions in axi_interconnect axi4lite_0.


INFO: The fsl_v20_0 core has constraints automatically generated by XPS in

implementation/fsl_v20_0_wrapper/fsl_v20_0_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: The fsl_v20_1 core has constraints automatically generated by XPS in

implementation/fsl_v20_1_wrapper/fsl_v20_1_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.





INFO: The fsl_v20_2 core has constraints automatically generated by XPS in

implementation/fsl_v20_2_wrapper/fsl_v20_2_wrapper.ucf.


It can be overridden by constraints placed in the system.ucf file.







Modify defaults ...



Creating stub ...



Processing licensed instances ...

Completion time: 0.00 seconds



Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...

IPNAME:fsl_to_axi INSTANCE:fsl_to_axi_0 - C:\Temp\Spgram4\BramFFT\system.mhs

line 201 - Copying (BBD-specified) netlist files.

IPNAME:mem_to_vga INSTANCE:mem_to_vga_0 - C:\Temp\Spgram4\BramFFT\system.mhs

line 208 - Copying (BBD-specified) netlist files.



Managing cache ...



Elaborating instances ...

IPNAME:bram_block INSTANCE:microblaze_0_bram_block -

C:\Temp\Spgram4\BramFFT\system.mhs line 75 - elaborating IP

IPNAME:clock_generator INSTANCE:clock_generator_0 -

C:\Temp\Spgram4\BramFFT\system.mhs line 122 - elaborating IP

ClkGen elaborate status: PASSED


----------------------------------------


----------------------------------------




Writing HDL for elaborated instances ...



Inserting wrapper level ...

Completion time: 0.00 seconds



Constructing platform-level connectivity ...

Completion time: 0.00 seconds



Writing (top-level) BMM ...



Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...



INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 

INSTANCE:proc_sys_reset_0 - C:\Temp\Spgram4\BramFFT\system.mhs line 29 - Running

XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_ilmb - C:\Temp\Spgram4\BramFFT\system.mhs line 43 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_i_bram_ctrl - C:\Temp\Spgram4\BramFFT\system.mhs line 50 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_dlmb - C:\Temp\Spgram4\BramFFT\system.mhs line 59 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_d_bram_ctrl - C:\Temp\Spgram4\BramFFT\system.mhs line 66 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0_bram_block - C:\Temp\Spgram4\BramFFT\system.mhs line 75 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:microblaze_0 - C:\Temp\Spgram4\BramFFT\system.mhs line 82 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:debug_module - C:\Temp\Spgram4\BramFFT\system.mhs line 109 - Running

XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:clock_generator_0 - C:\Temp\Spgram4\BramFFT\system.mhs line 122 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:axi4lite_0 - C:\Temp\Spgram4\BramFFT\system.mhs line 136 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:rs232_uart_1 - C:\Temp\Spgram4\BramFFT\system.mhs line 144 - Running

XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:push_buttons_4bits - C:\Temp\Spgram4\BramFFT\system.mhs line 159 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:leds_8bits - C:\Temp\Spgram4\BramFFT\system.mhs line 173 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:dip_switches_8bits - C:\Temp\Spgram4\BramFFT\system.mhs line 187 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_to_axi_0 - C:\Temp\Spgram4\BramFFT\system.mhs line 201 - Running

XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:mem_to_vga_0 - C:\Temp\Spgram4\BramFFT\system.mhs line 208 - Running

XST synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_v20_0 - C:\Temp\Spgram4\BramFFT\system.mhs line 218 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_v20_1 - C:\Temp\Spgram4\BramFFT\system.mhs line 225 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:fsl_v20_2 - C:\Temp\Spgram4\BramFFT\system.mhs line 232 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

INSTANCE:axi_iic_0 - C:\Temp\Spgram4\BramFFT\system.mhs line 241 - Running XST

synthesis

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Running NGCBUILD ...

IPNAME:system_microblaze_0_ilmb_wrapper INSTANCE:microblaze_0_ilmb -

C:\Temp\Spgram4\BramFFT\system.mhs line 43 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_ilmb_wrapper.ngc

../system_microblaze_0_ilmb_wrapper



Reading NGO file

"C:/Temp/Spgram4/BramFFT/implementation/microblaze_0_ilmb_wrapper/system_microbl

aze_0_ilmb_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_ilmb_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_ilmb_wrapper.blc"...



NGCBUILD done.

IPNAME:system_microblaze_0_dlmb_wrapper INSTANCE:microblaze_0_dlmb -

C:\Temp\Spgram4\BramFFT\system.mhs line 59 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_dlmb_wrapper.ngc

../system_microblaze_0_dlmb_wrapper



Reading NGO file

"C:/Temp/Spgram4/BramFFT/implementation/microblaze_0_dlmb_wrapper/system_microbl

aze_0_dlmb_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_dlmb_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_dlmb_wrapper.blc"...



NGCBUILD done.

IPNAME:system_microblaze_0_wrapper INSTANCE:microblaze_0 -

C:\Temp\Spgram4\BramFFT\system.mhs line 82 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_microblaze_0_wrapper.ngc

../system_microblaze_0_wrapper



Reading NGO file

"C:/Temp/Spgram4/BramFFT/implementation/microblaze_0_wrapper/system_microblaze_0

_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_microblaze_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_microblaze_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -

C:\Temp\Spgram4\BramFFT\system.mhs line 122 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc

../system_clock_generator_0_wrapper



Reading NGO file

"C:/Temp/Spgram4/BramFFT/implementation/clock_generator_0_wrapper/system_clock_g

enerator_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi4lite_0_wrapper INSTANCE:axi4lite_0 -

C:\Temp\Spgram4\BramFFT\system.mhs line 136 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_axi4lite_0_wrapper.ngc

../system_axi4lite_0_wrapper



Reading NGO file

"C:/Temp/Spgram4/BramFFT/implementation/axi4lite_0_wrapper/system_axi4lite_0_wra

pper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi4lite_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_axi4lite_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_to_axi_0_wrapper INSTANCE:fsl_to_axi_0 -

C:\Temp\Spgram4\BramFFT\system.mhs line 201 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_to_axi_0_wrapper.ngc

../system_fsl_to_axi_0_wrapper



Reading NGO file

"C:/Temp/Spgram4/BramFFT/implementation/fsl_to_axi_0_wrapper/system_fsl_to_axi_0

_wrapper.ngc" ...

Loading design module

"C:\Temp\Spgram4\BramFFT\implementation\fsl_to_axi_0_wrapper/xfft_v8_0.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_to_axi_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_to_axi_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_mem_to_vga_0_wrapper INSTANCE:mem_to_vga_0 -

C:\Temp\Spgram4\BramFFT\system.mhs line 208 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_mem_to_vga_0_wrapper.ngc

../system_mem_to_vga_0_wrapper



Reading NGO file

"C:/Temp/Spgram4/BramFFT/implementation/mem_to_vga_0_wrapper/system_mem_to_vga_0

_wrapper.ngc" ...

Loading design module

"C:\Temp\Spgram4\BramFFT\implementation\mem_to_vga_0_wrapper/bram.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_mem_to_vga_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_mem_to_vga_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_v20_0_wrapper INSTANCE:fsl_v20_0 -

C:\Temp\Spgram4\BramFFT\system.mhs line 218 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_v20_0_wrapper.ngc

../system_fsl_v20_0_wrapper



Reading NGO file

"C:/Temp/Spgram4/BramFFT/implementation/fsl_v20_0_wrapper/system_fsl_v20_0_wrapp

er.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_v20_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_v20_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_v20_1_wrapper INSTANCE:fsl_v20_1 -

C:\Temp\Spgram4\BramFFT\system.mhs line 225 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_v20_1_wrapper.ngc

../system_fsl_v20_1_wrapper



Reading NGO file

"C:/Temp/Spgram4/BramFFT/implementation/fsl_v20_1_wrapper/system_fsl_v20_1_wrapp

er.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_v20_1_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_v20_1_wrapper.blc"...



NGCBUILD done.

IPNAME:system_fsl_v20_2_wrapper INSTANCE:fsl_v20_2 -

C:\Temp\Spgram4\BramFFT\system.mhs line 232 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc6slx16csg324-3 -intstyle silent -i -sd .. system_fsl_v20_2_wrapper.ngc

../system_fsl_v20_2_wrapper



Reading NGO file

"C:/Temp/Spgram4/BramFFT/implementation/fsl_v20_2_wrapper/system_fsl_v20_2_wrapp

er.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_fsl_v20_2_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  2 sec

Total CPU time to NGCBUILD completion:   2 sec



Writing NGCBUILD log file "../system_fsl_v20_2_wrapper.blc"...



NGCBUILD done.

INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

   If any constraint needs to be overridden, this should be done by modifying

   the data/system.ucf file.



Rebuilding cache ...



Total run time: 198.00 seconds

"Running synthesis..."

cd synthesis & synthesis.cmd

"xst -ifn "system_xst.scr" -intstyle silent"

"Running XST synthesis ..."

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

"XST completed"

"*********************************************"

"Running Xilinx Implementation tools.."

"*********************************************"

xflow -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

Release 14.2 - Xflow P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc6slx16csg324-3 -implement xflow.opt system.ngc

 

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>



Using Flow File: C:/Temp/Spgram4/BramFFT/implementation/fpga.flw 

Using Option File(s): 

 C:/Temp/Spgram4/BramFFT/implementation/xflow.opt 



Creating Script File ... 



#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc6slx16csg324-3 -nt timestamp -bm system.bmm

"C:/Temp/Spgram4/BramFFT/implementation/system.ngc" -uc system.ucf system.ngd 

#----------------------------------------------#

Release 14.2 - ngdbuild P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>





Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p


xc6slx16csg324-3 -nt timestamp -bm system.bmm


C:/Temp/Spgram4/BramFFT/implementation/system.ngc -uc system.ucf system.ngd





Reading NGO file "C:/Temp/Spgram4/BramFFT/implementation/system.ngc" ...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_push_buttons_4bits_wrapper.ngc"..


.


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_dip_switches_8bits_wrapper.ngc"..


.


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_rs232_uart_1_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_proc_sys_reset_0_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_clock_generator_0_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_axi4lite_0_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_microblaze_0_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_fsl_v20_0_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_fsl_v20_1_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_fsl_v20_2_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_mem_to_vga_0_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_microblaze_0_i_bram_ctrl_wrapper.


ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_microblaze_0_d_bram_ctrl_wrapper.


ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_debug_module_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_fsl_to_axi_0_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_leds_8bits_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_axi_iic_0_wrapper.ngc"...


Loading design module


"C:/Temp/Spgram4/BramFFT/implementation/system_microblaze_0_bram_block_wrapper.n


gc"...


Applying constraints in


"C:/Temp/Spgram4/BramFFT/implementation/system_microblaze_0_ilmb_wrapper.ncf" to


module "microblaze_0_ilmb"...


Checking Constraint Associations...


Applying constraints in


"C:/Temp/Spgram4/BramFFT/implementation/system_microblaze_0_dlmb_wrapper.ncf" to


module "microblaze_0_dlmb"...


Checking Constraint Associations...


Applying constraints in


"C:/Temp/Spgram4/BramFFT/implementation/system_axi4lite_0_wrapper.ncf" to module


"axi4lite_0"...


Checking Constraint Associations...


Applying constraints in


"C:/Temp/Spgram4/BramFFT/implementation/system_microblaze_0_wrapper.ncf" to


module "microblaze_0"...


Checking Constraint Associations...


Gathering constraint information from source properties...


Done.





Annotating constraints to design from ucf file "system.ucf" ...


Resolving constraint associations...


Checking Constraint Associations...


WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi4lite_0/axi4lite_0\/si_converter_bank\/gen_conv_sl


   ot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_INV_0 TNM =


   FFS:axi4lite_0_reset_resync>: No instances of type FFS were found under block


   "axi4lite_0/axi4lite_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/int

erconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP axi4lite_0_reset_source = FFS


   PADS CPUS;>: CPUS "*" does not match any design objects.





WARNING:ConstraintSystem:194 - The TNM 'axi4lite_0_reset_resync', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification


   'TS_sys_clk_pin', was traced into PLL_ADV instance


   clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM


   groups and period specifications were generated at the PLL_ADV output(s): 


   CLKOUT1: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT1 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT1" TS_sys_clk_pin


   * 0.25 HIGH 50>





INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification


   'TS_sys_clk_pin', was traced into PLL_ADV instance


   clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM


   groups and period specifications were generated at the PLL_ADV output(s): 


   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0" TS_sys_clk_pin


   HIGH 50>





Done...





Processing BMM file "system.bmm" ...





Checking expanded design ...


WARNING:NgdBuild:443 - SFF primitive


   'microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Decode_I/Using_FPGA.


   Gen_Bits[27].MEM_EX_Result_Inst' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000004f


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000050


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000051


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000052


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000053


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000054


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000055


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000056


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000057


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   2' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000059


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005a


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   3' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   4' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005c


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005d


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   5' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   6' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000005f


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000060


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   7' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   8' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000062


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000063


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   9' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   a' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   c' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   d' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000065


   e' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000066


   f' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000067


   0' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000067


   1' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk00000fe


   b' has unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_0/axi_iic_0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:452 - logical net 'fsl_v20_2_FSL_M_Control' has no driver


WARNING:NgdBuild:452 - logical net


   'fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/sig0000073d' has no


   driver





Partition Implementation Status


-------------------------------





  No Partitions were found in this design.





-------------------------------





NGDBUILD Design Results Summary:


  Number of errors:     0


  Number of warnings:  80





Writing NGD file "system.ngd" ...


Total REAL time to NGDBUILD completion:  43 sec


Total CPU time to NGDBUILD completion:   43 sec





Writing NGDBUILD log file "system.bld"...





NGDBUILD done.








#----------------------------------------------#

# Starting program map

# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf 

#----------------------------------------------#

Release 14.2 - Map P.28xd (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>


Using target part "6slx16csg324-3".


vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv


INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to


'2100@vm05.cs.lth.se'.


INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.


INFO:Security:54 - 'xc6slx16' is a WebPack part.


WARNING:Security:43 - No license file was found in the standard Xilinx license


directory.


WARNING:Security:44 - Since no license file was found,


       please run the Xilinx License Configuration Manager


       (xlcm or "Manage Xilinx Licenses")


       to assist in obtaining a license.


WARNING:Security:42 - Your software subscription period has lapsed. Your current


version of Xilinx tools will continue to function, but you no longer qualify for


Xilinx software updates or new releases.


----------------------------------------------------------------------


Mapping design into LUTs...


Writing file system_map.ngm...


Running directed packing...


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

4" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175c


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000091). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

6" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175d


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000092). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

1" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000172f


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000076). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010e

8" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig0000175e


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000093). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

3" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001730


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000077). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

5" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001731


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000078). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

a" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001732


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm00000079). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

c" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001733


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000007a). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk0000108

e" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001734


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000007b). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010c

f" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001753


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008b). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010d

1" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001754


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008c). The constraint will be ignored.


WARNING:Pack:2238 - Function generator symbol


   "fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/blk000010d

3" (Output Signal =


   fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/sig00001755


   ) has an invalid use of the LUTNM constraint. There are no other function


   generator symbols with a matching LUTNM constraint value


   (LUTNM=fsl_to_axi_0/fsl_to_axi_0/FFT/blk00000001/blk00000179/blk0000017a/hlut


   nm0000008d). The constraint will be ignored.


Running delay-based LUT packing...


Updating timing models...


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report


   (.mrp).


Running timing-driven placement...


Total REAL time at the beginning of Placer: 15 secs 


Total CPU  time at the beginning of Placer: 15 secs 





Phase 1.1  Initial Placement Analysis


Phase 1.1  Initial Placement Analysis (Checksum:30844a5a) REAL time: 16 secs 





Phase 2.7  Design Feasibility Check


INFO:Place:834 - Only a subset of IOs are locked. Out of 37 IOs, 36 are locked


   and 1 are not locked. If you would like to print the names of these IOs,


   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 


Phase 2.7  Design Feasibility Check (Checksum:30844a5a) REAL time: 17 secs 





Phase 3.31  Local Placement Optimization


Phase 3.31  Local Placement Optimization (Checksum:bbd1c9a2) REAL time: 17 secs 





Phase 4.2  Initial Placement for Architecture Specific Features


....


Phase 4.2  Initial Placement for Architecture Specific Features


(Checksum:68ed4049) REAL time: 21 secs 





Phase 5.36  Local Placement Optimization


Phase 5.36  Local Placement Optimization (Checksum:68ed4049) REAL time: 21 secs 





Phase 6.30  Global Clock Region Assignment


Phase 6.30  Global Clock Region Assignment (Checksum:68ed4049) REAL time: 21 secs 





Phase 7.3  Local Placement Optimization


....


Phase 7.3  Local Placement Optimization (Checksum:86da60c9) REAL time: 21 secs 





Phase 8.5  Local Placement Optimization


Phase 8.5  Local Placement Optimization (Checksum:68f5e139) REAL time: 22 secs 





Phase 9.8  Global Placement


.......................


......................................................


...........................................................


.........................................................


...................


Phase 9.8  Global Placement (Checksum:d21644aa) REAL time: 1 mins 4 secs 





Phase 10.5  Local Placement Optimization


Phase 10.5  Local Placement Optimization (Checksum:d21644aa) REAL time: 1 mins 4 secs 





Phase 11.18  Placement Optimization


Phase 11.18  Placement Optimization (Checksum:77e2e148) REAL time: 1 mins 42 secs 





Phase 12.5  Local Placement Optimization


Phase 12.5  Local Placement Optimization (Checksum:77e2e148) REAL time: 1 mins 43 secs 





Phase 13.34  Placement Validation


Phase 13.34  Placement Validation (Checksum:a1752ba7) REAL time: 1 mins 43 secs 





Total REAL time to Placer completion: 1 mins 43 secs 


Total CPU  time to Placer completion: 1 mins 43 secs 


Running post-placement packing...


Writing output files...





Design Summary:


Number of errors:      0


Number of warnings:   51


Slice Logic Utilization:


  Number of Slice Registers:                 4,111 out of  18,224   22


    Number used as Flip Flops:               4,104


    Number used as Latches:                      0


    Number used as Latch-thrus:                  0


    Number used as AND/OR logics:                7


  Number of Slice LUTs:                      4,506 out of   9,112   49


    Number used as logic:                    3,790 out of   9,112   41


      Number using O6 output only:           2,819


      Number using O5 output only:              74


      Number using O5 and O6:                  897


      Number used as ROM:                        0


    Number used as Memory:                     516 out of   2,176   23


      Number used as Dual Port RAM:            152


        Number using O6 output only:            88


        Number using O5 output only:             0


        Number using O5 and O6:                 64


      Number used as Single Port RAM:            0


      Number used as Shift Register:           364


        Number using O6 output only:            51


        Number using O5 output only:             1


        Number using O5 and O6:                312


    Number used exclusively as route-thrus:    200


      Number with same-slice register load:    188


      Number with same-slice carry load:        12


      Number with other load:                    0





Slice Logic Distribution:


  Number of occupied Slices:                 1,634 out of   2,278   71


  Nummber of MUXCYs used:                      908 out of   4,556   19


  Number of LUT Flip Flop pairs used:        4,976


    Number with an unused Flip Flop:         1,643 out of   4,976   33


    Number with an unused LUT:                 470 out of   4,976    9


    Number of fully used LUT-FF pairs:       2,863 out of   4,976   57


    Number of unique control sets:             197


    Number of slice register sites lost


      to control set restrictions:             772 out of  18,224    4





  A LUT Flip Flop pair for this architecture represents one LUT paired with


  one Flip Flop within a slice.  A control set is a unique combination of


  clock, reset, set, and enable signals for a registered element.


  The Slice Logic Distribution report is not meaningful if the design is


  over-mapped for a non-slice resource or if Placement fails.





IO Utilization:


  Number of bonded IOBs:                        37 out of     232   15


    Number of LOCed IOBs:                       36 out of      37   97


    IOB Flip Flops:                              4





Specific Feature Utilization:


  Number of RAMB16BWERs:                        24 out of      32   75


  Number of RAMB8BWERs:                          7 out of      64   10


  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3


    Number used as BUFIO2s:                      1


    Number used as BUFIO2_2CLKs:                 0


  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0


  Number of BUFG/BUFGMUXs:                       3 out of      16   18


    Number used as BUFGs:                        3


    Number used as BUFGMUX:                      0


  Number of DCM/DCM_CLKGENs:                     0 out of       4    0


  Number of ILOGIC2/ISERDES2s:                   1 out of     248    1


    Number used as ILOGIC2s:                     1


    Number used as ISERDES2s:                    0


  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0


  Number of OLOGIC2/OSERDES2s:                   3 out of     248    1


    Number used as OLOGIC2s:                     3


    Number used as OSERDES2s:                    0


  Number of BSCANs:                              1 out of       4   25


  Number of BUFHs:                               0 out of     128    0


  Number of BUFPLLs:                             0 out of       8    0


  Number of BUFPLL_MCBs:                         0 out of       4    0


  Number of DSP48A1s:                           12 out of      32   37


  Number of ICAPs:                               0 out of       1    0


  Number of MCBs:                                0 out of       2    0


  Number of PCILOGICSEs:                         0 out of       2    0


  Number of PLL_ADVs:                            1 out of       2   50


  Number of PMVs:                                0 out of       1    0


  Number of STARTUPs:                            0 out of       1    0


  Number of SUSPEND_SYNCs:                       0 out of       1    0





Average Fanout of Non-Clock Nets:                3.83





Peak Memory Usage:  524 MB


Total REAL time to MAP completion:  1 mins 47 secs 


Total CPU time to MAP completion:   1 mins 47 secs 





Mapping completed.


See MAP report file "system_map.mrp" for details.








#----------------------------------------------#

# Starting program par

# par -w -ol high system_map.ncd system.ncd system.pcf 

#----------------------------------------------#

Release 14.2 - par P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <C:/Xilinx/14.2/ISE_DS/EDK/data/parBmgr.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/data/parBmgr.acd>







Constraints file: system.pcf.

Loading device for application Rf_Device from file '6slx16.nph' in environment

C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3

vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv

INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to '2100@vm05.cs.lth.se'.

INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

INFO:Security:54 - 'xc6slx16' is a WebPack part.

WARNING:Security:43 - No license file was found in the standard Xilinx license directory.

WARNING:Security:44 - Since no license file was found,

       please run the Xilinx License Configuration Manager

       (xlcm or "Manage Xilinx Licenses")

       to assist in obtaining a license.

WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue

to function, but you no longer qualify for Xilinx software updates or new releases.



----------------------------------------------------------------------



Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)





Device speed data version:  "PRODUCTION 1.22 2012-07-09".







Device Utilization Summary:



Slice Logic Utilization:

  Number of Slice Registers:                 4,111 out of  18,224   22

    Number used as Flip Flops:               4,104

    Number used as Latches:                      0

    Number used as Latch-thrus:                  0

    Number used as AND/OR logics:                7

  Number of Slice LUTs:                      4,506 out of   9,112   49

    Number used as logic:                    3,790 out of   9,112   41

      Number using O6 output only:           2,819

      Number using O5 output only:              74

      Number using O5 and O6:                  897

      Number used as ROM:                        0

    Number used as Memory:                     516 out of   2,176   23

      Number used as Dual Port RAM:            152

        Number using O6 output only:            88

        Number using O5 output only:             0

        Number using O5 and O6:                 64

      Number used as Single Port RAM:            0

      Number used as Shift Register:           364

        Number using O6 output only:            51

        Number using O5 output only:             1

        Number using O5 and O6:                312

    Number used exclusively as route-thrus:    200

      Number with same-slice register load:    188

      Number with same-slice carry load:        12

      Number with other load:                    0



Slice Logic Distribution:

  Number of occupied Slices:                 1,634 out of   2,278   71

  Nummber of MUXCYs used:                      908 out of   4,556   19

  Number of LUT Flip Flop pairs used:        4,976

    Number with an unused Flip Flop:         1,643 out of   4,976   33

    Number with an unused LUT:                 470 out of   4,976    9

    Number of fully used LUT-FF pairs:       2,863 out of   4,976   57

    Number of slice register sites lost

      to control set restrictions:               0 out of  18,224    0



  A LUT Flip Flop pair for this architecture represents one LUT paired with

  one Flip Flop within a slice.  A control set is a unique combination of

  clock, reset, set, and enable signals for a registered element.

  The Slice Logic Distribution report is not meaningful if the design is

  over-mapped for a non-slice resource or if Placement fails.



IO Utilization:

  Number of bonded IOBs:                        37 out of     232   15

    Number of LOCed IOBs:                       36 out of      37   97

    IOB Flip Flops:                              4



Specific Feature Utilization:

  Number of RAMB16BWERs:                        24 out of      32   75

  Number of RAMB8BWERs:                          7 out of      64   10

  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3

    Number used as BUFIO2s:                      1

    Number used as BUFIO2_2CLKs:                 0

  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0

  Number of BUFG/BUFGMUXs:                       3 out of      16   18

    Number used as BUFGs:                        3

    Number used as BUFGMUX:                      0

  Number of DCM/DCM_CLKGENs:                     0 out of       4    0

  Number of ILOGIC2/ISERDES2s:                   1 out of     248    1

    Number used as ILOGIC2s:                     1

    Number used as ISERDES2s:                    0

  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     248    0

  Number of OLOGIC2/OSERDES2s:                   3 out of     248    1

    Number used as OLOGIC2s:                     3

    Number used as OSERDES2s:                    0

  Number of BSCANs:                              1 out of       4   25

  Number of BUFHs:                               0 out of     128    0

  Number of BUFPLLs:                             0 out of       8    0

  Number of BUFPLL_MCBs:                         0 out of       4    0

  Number of DSP48A1s:                           12 out of      32   37

  Number of ICAPs:                               0 out of       1    0

  Number of MCBs:                                0 out of       2    0

  Number of PCILOGICSEs:                         0 out of       2    0

  Number of PLL_ADVs:                            1 out of       2   50

  Number of PMVs:                                0 out of       1    0

  Number of STARTUPs:                            0 out of       1    0

  Number of SUSPEND_SYNCs:                       0 out of       1    0





Overall effort level (-ol):   High 

Router effort level (-rl):    High 



INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx

   Command Line Tools User Guide for information on generating a TSI report.

Starting initial Timing Analysis.  REAL time: 9 secs 

Finished initial Timing Analysis.  REAL time: 9 secs 



WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM20_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM18_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM17_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<30> has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM19_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM2_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O has no

   load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM6_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM5_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM1_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<31> has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM7_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM11_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM8_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM12_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM9_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM10_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM16_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM4_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM15_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM3_RAMD_O has no load.  PAR

   will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM13_RAMD_O has no load. 

   PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO_I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM14_RAMD_O has no load. 

   PAR will not attempt to route this signal.

Starting Router





Phase  1  : 31775 unrouted;      REAL time: 11 secs 



Phase  2  : 24903 unrouted;      REAL time: 12 secs 



Phase  3  : 10464 unrouted;      REAL time: 26 secs 



Phase  4  : 10464 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 27 secs 



Updating file: system.ncd with current fully routed design.



Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 



Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 41 secs 

Total REAL time to Router completion: 41 secs 

Total CPU time to Router completion: 37 secs 



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



Generating "PAR" statistics.



**************************

Generating Clock Report

**************************



+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|     clk_100_0000MHz | BUFGMUX_X3Y13| No   | 1470 |  0.544     |  1.391      |

+---------------------+--------------+------+------+------------+-------------+

|microblaze_0_debug_D |              |      |      |            |             |

|              bg_Clk |  BUFGMUX_X2Y2| No   |   57 |  0.060     |  0.907      |

+---------------------+--------------+------+------+------------+-------------+

|clock_generator_0_CL |              |      |      |            |             |

|               KOUT1 |  BUFGMUX_X2Y3| No   |    9 |  0.514     |  1.366      |

+---------------------+--------------+------+------+------------+-------------+

|microblaze_0_debug_D |              |      |      |            |             |

|           bg_Update |         Local|      |   21 |  2.199     |  3.068      |

+---------------------+--------------+------+------+------------+-------------+



* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.



* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.



Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Number of Timing Constraints that were not applied: 1



Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.



----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   

                                            |             |    Slack   | Achievable | Errors |    Score   

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |     0.643ns|     9.357ns|       0|           0

  G_PLL0_CLKOUT0 = PERIOD TIMEGRP         " | HOLD        |     0.264ns|            |       0|           0

  clock_generator_0_clock_generator_0_SIG_P |             |            |            |        |            

  LL0_CLKOUT0" TS_sys_clk_pin         HIGH  |             |            |            |        |            

  50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |     5.300ns|    18.800ns|       0|           0

  G_PLL0_CLKOUT1 = PERIOD TIMEGRP         " | HOLD        |     0.440ns|            |       0|           0

  clock_generator_0_clock_generator_0_SIG_P |             |            |            |        |            

  LL0_CLKOUT1" TS_sys_clk_pin         * 0.2 |             |            |            |        |            

  5 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.666ns|     3.334ns|       0|           0

  pin" 100 MHz HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_Reset_path" TIG | SETUP       |         N/A|     2.561ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi4lite_0_reset_resync_path" TI | MAXDELAY    |         N/A|     4.553ns|     N/A|           0

  G                                         |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_dlmb_POR_FF_I_p | SETUP       |         N/A|     1.751ns|     N/A|           0

  ath" TIG                                  |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_TIG_microblaze_0_ilmb_POR_FF_I_p | SETUP       |         N/A|     2.163ns|     N/A|           0

  ath" TIG                                  |             |            |            |        |            

----------------------------------------------------------------------------------------------------------





Derived Constraint Report

Review Timing Report for more details on the following derived constraints.

To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"

or "Run Timing Analysis" from Timing Analyzer (timingan).

Derived Constraints for TS_sys_clk_pin

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |

|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|

|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|TS_sys_clk_pin                 |     10.000ns|      3.334ns|      9.357ns|            0|            0|            0|       325100|

| TS_clock_generator_0_clock_gen|     40.000ns|     18.800ns|          N/A|            0|            0|          620|            0|

| erator_0_SIG_PLL0_CLKOUT1     |             |             |             |             |             |             |             |

| TS_clock_generator_0_clock_gen|     10.000ns|      9.357ns|          N/A|            0|            0|       324480|            0|

| erator_0_SIG_PLL0_CLKOUT0     |             |             |             |             |             |             |             |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+



All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 

   constraint is not analyzed due to the following: No paths covered by this 

   constraint; Other constraints intersect with this constraint; or This 

   constraint was disabled by a Path Tracing Control. Please run the Timespec 

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.





Generating Pad Report.



All signals are completely routed.



WARNING:Par:283 - There are 38 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.



Total REAL time to PAR completion: 43 secs 

Total CPU time to PAR completion: 39 secs 



Peak Memory Usage:  477 MB



Placer: Placement generated during map.

Routing: Completed - No errors found.

Timing: Completed - No errors found.



Number of error messages: 0

Number of warning messages: 40

Number of info messages: 1



Writing design to file system.ncd







PAR done!







#----------------------------------------------#

# Starting program post_par_trce

# trce -e 3 -xml system.twx system.ncd system.pcf 

#----------------------------------------------#

Release 14.2 - Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.








PMSPEC -- Overriding Xilinx file


<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file


<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>


Loading device for application Rf_Device from file '6slx16.nph' in environment


C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.


   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3


INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more


   information, see the TSI report.  Please consult the Xilinx Command Line


   Tools User Guide for information on generating a TSI report.


--------------------------------------------------------------------------------


Release 14.2 Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -e 3 -xml system.twx


system.ncd system.pcf








Design file:              system.ncd


Physical constraint file: system.pcf


Device,speed:             xc6slx16,-3 (PRODUCTION 1.22 2012-07-09)


Report level:             error report


--------------------------------------------------------------------------------





INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).


INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in


   the unconstrained paths section(s) of the report.


INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of


   this model, and for more information on accounting for different loading conditions, please see the device datasheet.








Timing summary:


---------------





Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)





Constraints cover 325113 paths, 0 nets, and 25138 connections





Design statistics:


   Minimum period:  18.800ns (Maximum frequency:  53.191MHz)








Analysis completed Wed Oct 16 15:15:47 2013


--------------------------------------------------------------------------------





Generating Report ...





Number of warnings: 0


Number of info messages: 4


Total time: 9 secs 






xflow done!

touch __xps/system_routed

xilperl C:/Xilinx/14.2/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par

"*********************************************"

"Running Bitgen.."

"*********************************************"

cd implementation & bitgen -w -f bitgen.ut system & cd ..

Release 14.2 - Bitgen P.28xd (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file

<C:/Xilinx/14.2/ISE_DS/EDK/spartan6/data/spartan6.acd> with local file

<C:/Xilinx/14.2/ISE_DS/ISE/spartan6/data/spartan6.acd>

Loading device for application Rf_Device from file '6slx16.nph' in environment

C:\Xilinx\14.2\ISE_DS\ISE\;C:\Xilinx\14.2\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3

Opened constraints file system.pcf.



Wed Oct 16 15:15:52 2013



INFO:Bitgen:341 - This design is using one or more 9K Block RAMs (RAMB8BWER). 

   9K Block RAM initialization data, both user defined and default, requires a

   special bit stream format.  For more information, please reference Xilinx

   Answer Record 39999.

Running DRC.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM20_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[10].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[12].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[3].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[13].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[1].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[4].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM18_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM17_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[0].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[6].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<30>> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM19_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM2_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[11].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[14].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[15].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[9].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[7].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[2].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[5].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register

   _File_I/Using_LUT6.All_RAM32M[8].ram32m_i_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM6_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM5_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM1_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block_BRAM_Addr<31>> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM7_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM11_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM8_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM12_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM9_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM10_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM16_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM4_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM15_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM3_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM13_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <fsl_v20_2/fsl_v20_2/Using_FIFO.Sync_FIFO_Gen.Use_Data.Sync_FIFO_I1/Sync_FIFO

   _I.dpram_fifo_i.DPRAM_FIFO/Mram_RAM14_RAMD_O> is incomplete. The signal does

   not drive any load pins in the design.

WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs

   (RAMB8BWER).  9K Block RAM initialization data, both user defined and

   default, may be incorrect and should not be used.  For more information,

   please reference Xilinx Answer Record 39999.

DRC detected 0 errors and 39 warnings.  Please see the previously displayed

individual error or warning messages for more details.

INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to

'2100@vm05.cs.lth.se'.

INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set.

INFO:Security:54 - 'xc6slx16' is a WebPack part.

WARNING:Security:43 - No license file was found in the standard Xilinx license

directory.

WARNING:Security:44 - Since no license file was found,

       please run the Xilinx License Configuration Manager

       (xlcm or "Manage Xilinx Licenses")

       to assist in obtaining a license.

WARNING:Security:42 - Your software subscription period has lapsed. Your current

version of Xilinx tools will continue to function, but you no longer qualify for

Xilinx software updates or new releases.



Creating bit map...

Saving bit stream in "system.bit".

Bitstream generation is complete.

Done!
Xilinx Platform Studio (XPS)
Xilinx EDK 14.2 Build EDK_P.28xd
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Overriding Xilinx file <TextEditor.cfg> with local file <C:/Xilinx/14.2/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
	C:\Temp\SPgram4\BramFFT\etc\system.filters
Done writing Tab View settings to:
	C:\Temp\SPgram4\BramFFT\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.2 Build EDK_P.28xd
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


********************************************************************************
At Local date and time: Sun Oct 20 18:10:50 2013
 make -f system.make clean started...
rm -f implementation/system.ngc

rm -f implementation/system_proc_sys_reset_0_wrapper.ngc implementation/system_microblaze_0_ilmb_wrapper.ngc implementation/system_microblaze_0_i_bram_ctrl_wrapper.ngc implementation/system_microblaze_0_dlmb_wrapper.ngc implementation/system_microblaze_0_d_bram_ctrl_wrapper.ngc implementation/system_microblaze_0_bram_block_wrapper.ngc implementation/system_microblaze_0_wrapper.ngc implementation/system_debug_module_wrapper.ngc implementation/system_clock_generator_0_wrapper.ngc implementation/system_axi4lite_0_wrapper.ngc implementation/system_rs232_uart_1_wrapper.ngc implementation/system_push_buttons_4bits_wrapper.ngc implementation/system_leds_8bits_wrapper.ngc implementation/system_dip_switches_8bits_wrapper.ngc implementation/system_fsl_to_axi_0_wrapper.ngc implementation/system_mem_to_vga_0_wrapper.ngc implementation/system_fsl_v20_0_wrapper.ngc implementation/system_fsl_v20_1_wrapper.ngc implementation/system_fsl_v20_2_wrapper.ngc implementation/system_axi_iic_0_wrapper.ngc

rm -f platgen.log

rm -f __xps/ise/_xmsgs/platgen.xmsgs

rm -f implementation/system.bmm

rm -rf implementation/cache

rm -f implementation/system.bit

rm -f implementation/system.ncd

rm -f implementation/system_bd.bmm 

rm -f implementation/system_map.ncd 

rm -f implementation/download.bit 

rm -f __xps/system_bits

rm -rf implementation synthesis xst hdl

rm -rf xst.srp system.srp

rm -f __xps/ise/_xmsgs/bitinit.xmsgs

rm -rf __xps/ps7_instance.mhs

rm -rf simulation/behavioral

rm -f simgen.log

rm -f __xps/ise/_xmsgs/simgen.xmsgs

rm -f _impact.cmd

Done!
