Release 14.6 - xst P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
 
--> Reading design: fsl_to_axi.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "fsl_to_axi.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "fsl_to_axi"
Output Format                      : NGC
Target Device                      : xc6slx16-2-csg324

---- Source Options
Top Module Name                    : fsl_to_axi
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"ipcore_dir"  }

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "D:\workspace\xilinx\xps\tast6\pcores\fsl_to_axi_v1_00_a\devl\projnav\ipcore_dir\xfft_v8_0.vhd" into library work
Parsing VHDL file "D:\workspace\xilinx\xps\tast6\pcores\fsl_to_axi_v1_00_a\hdl\vhdl\fsl_to_axi.vhd" into library fsl_to_axi_v1_00_a
Parsing entity <fsl_to_axi>.
Parsing architecture <EXAMPLE> of entity <fsl_to_axi>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <fsl_to_axi> (architecture <EXAMPLE>) from library <fsl_to_axi_v1_00_a>.
Going to verilog side to elaborate module xfft_v8_0

Elaborating module <xfft_v8_0>.
Back to vhdl to continue elaboration
ERROR:HDLCompiler:410 - "D:\workspace\xilinx\xps\tast6\pcores\fsl_to_axi_v1_00_a\hdl\vhdl\fsl_to_axi.vhd" Line 111: Expression has 16 elements ; expected 8
ERROR:HDLCompiler:410 - "D:\workspace\xilinx\xps\tast6\pcores\fsl_to_axi_v1_00_a\hdl\vhdl\fsl_to_axi.vhd" Line 114: Expression has 32 elements ; expected 16
ERROR:HDLCompiler:432 - "D:\workspace\xilinx\xps\test4\pcores\fsl_to_axi_v1_00_a\devl\projnav\ipcore_dir\xfft_v8_0.v" Line 57: Formal <s_axis_config_tdata> has no actual or default value.
ERROR:HDLCompiler:432 - "D:\workspace\xilinx\xps\test4\pcores\fsl_to_axi_v1_00_a\devl\projnav\ipcore_dir\xfft_v8_0.v" Line 58: Formal <s_axis_data_tdata> has no actual or default value.
Netlist fsl_to_axi(EXAMPLE) remains a blackbox, due to errors in its contents
--> 

Total memory usage is 207660 kilobytes

Number of errors   :    4 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

