INFO:sim:172 - Generating IP...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core.
   Overriding with simulation file type 'Structural'.
Resolving generics for 'xfft_v8_0'...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core.
   Overriding with simulation file type 'Structural'.
Applying external generics to 'xfft_v8_0'...
Finished delivering C-model simulation files.
Delivering associated files for 'xfft_v8_0'...
Delivering EJava files for 'xfft_v8_0'...
Generating implementation netlist for 'xfft_v8_0'...
INFO:sim - Pre-processing HDL files for 'xfft_v8_0'...
Running synthesis for 'xfft_v8_0'
Running ngcbuild...
Writing VHO instantiation template for 'xfft_v8_0'...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core.
   Overriding with simulation file type 'Structural'.
Writing VHDL structural simulation model for 'xfft_v8_0'...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core.
   Overriding with simulation file type 'Structural'.
Delivered 3 files into directory
D:/workspace/xilinx/ise/fsl_fft2/ipcore_dir/tmp/_cg/xfft_v8_0
Delivered 1 file into directory
D:/workspace/xilinx/ise/fsl_fft2/ipcore_dir/tmp/_cg/xfft_v8_0
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'xfft_v8_0'...
Generating metadata file...
Generating ISE project file for 'xfft_v8_0'...
Generating ISE project...
XCO file found: xfft_v8_0.xco
XMDF file found: xfft_v8_0_xmdf.tcl
Adding D:/workspace/xilinx/ise/fsl_fft2/ipcore_dir/tmp/_cg/xfft_v8_0.asy -view
all -origin_type imported
Adding D:/workspace/xilinx/ise/fsl_fft2/ipcore_dir/tmp/_cg/xfft_v8_0.ngc -view
all -origin_type created
Checking file
"D:/workspace/xilinx/ise/fsl_fft2/ipcore_dir/tmp/_cg/xfft_v8_0.ngc" for project
device match ...
File "D:/workspace/xilinx/ise/fsl_fft2/ipcore_dir/tmp/_cg/xfft_v8_0.ngc" device
information matches project device.
Adding D:/workspace/xilinx/ise/fsl_fft2/ipcore_dir/tmp/_cg/xfft_v8_0.sym -view
all -origin_type imported
Adding D:/workspace/xilinx/ise/fsl_fft2/ipcore_dir/tmp/_cg/xfft_v8_0.vhd -view
all -origin_type created
INFO:HDLCompiler:1061 - Parsing VHDL file
   "D:/workspace/xilinx/ise/fsl_fft2/ipcore_dir/tmp/_cg/xfft_v8_0.vhd" into
   library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding D:/workspace/xilinx/ise/fsl_fft2/ipcore_dir/tmp/_cg/xfft_v8_0.vho -view
all -origin_type imported
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/xfft_v8_0"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Launching README viewer...
Moving files to output directory...
Finished moving files to output directory
Wrote CGP file for project 'xfft_v8_0'.
