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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:17:01 10/11/2013 
-- Design Name: 
-- Module Name:    block_ram - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity block_ram is
port (Clk : in std_logic;
        addr1 : in integer;
        addr2 : in integer;
        we : in std_logic;
        data_i : in unsigned(3 downto 0);
        data_o : out unsigned(3 downto 0)
     );
end block_ram;

architecture Behavioral of block_ram is

	constant SCREEN_WIDTH : integer := 300;
	constant SCREEN_HEIGHT : integer := 128;

type line_type is array(0 to SCREEN_WIDTH-1) of unsigned(3 downto 0);
type scr_type is array(0 to SCREEN_HEIGHT-1) of line_type;
signal ram : scr_type := (others => (others => (others => '0')));

begin

PROCESS(Clk)
BEGIN
    if(rising_edge(Clk)) then
        if(we='1') then
            ram(addr1)(addr2) <= data_i;
        end if;
        data_o <= ram(addr1)(addr2);
    end if; 
END PROCESS;

end Behavioral;

