project new C:/Temp/tupmmama/pcores/mem_to_vga_v1_00_a/devl/projnav/mem_to_vga.xise;
project set family spartan6;
project set device xc6slx16;
project set package csg324;
project set speed -2;
project set top_level_module_type HDL;
project set synthesis_tool "XST (VHDL/Verilog)";
lib_vhdl new mem_to_vga_v1_00_a;
xfile add C:/Temp/tupmmama//pcores/mem_to_vga_v1_00_a/hdl/vhdl/mem_to_vga.vhd -lib_vhdl mem_to_vga_v1_00_a;
project close;
