--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   00:43:12 09/17/2013
-- Design Name:   
-- Module Name:   C:/stuff/workspace/xilinx/fft/FFT/fsl_test.vhd
-- Project Name:  FFT
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: user_logic
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use std.textio.all;

ENTITY fsl_test IS
END fsl_test;
 
ARCHITECTURE behavior OF fsl_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT mem_to_vga
    PORT(
			FSL_Clk	: in	std_logic;
			FSL_Rst	: in	std_logic;
			FSL_S_Clk	: in	std_logic;
			FSL_S_Read	: out	std_logic;
			FSL_S_Data	: in	std_logic_vector(0 to 31);
			FSL_S_Control	: in	std_logic;
			FSL_S_Exists	: in	std_logic;
			-- DO NOT EDIT ABOVE THIS LINE ---------------------
			
			pixel_clk 	: in std_logic;
			HS          : out std_logic;
			VS          : out std_logic;
			rgb			: out std_logic_vector(7 downto 0)
		);
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal exists : std_logic := '0';
   signal d_in : std_logic_vector(0 to 31) := (2 => '1', others => '0');

 	--Outputs
   signal rd_ack : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;

	type test_signal_type is array(0 to 63) of signed(7 downto 0);
	constant testing_signal : test_signal_type := (
--			to_signed(0, 8), to_signed(1, 8), to_signed(2, 8), to_signed(3, 8),
--			to_signed(4, 8), to_signed(5, 8), to_signed(6, 8), to_signed(7, 8)
	
--			to_signed(0,8), to_signed(1,8), to_signed(2,8), to_signed(3,8),
--			to_signed(4,8), to_signed(5,8), to_signed(6,8), to_signed(7,8), 
--			to_signed(8,8), to_signed(9,8), to_signed(10,8), to_signed(11,8),
--			to_signed(12,8), to_signed(13,8), to_signed(14,8), to_signed(15,8)

--			to_signed(0, 8), to_signed(1, 8), to_signed(2, 8), to_signed(3, 8), 
--			to_signed(4, 8), to_signed(5, 8), to_signed(6, 8), to_signed(7, 8), 
--			to_signed(8, 8), to_signed(9, 8), to_signed(10, 8), to_signed(11, 8), 
--			to_signed(12, 8), to_signed(13, 8), to_signed(14, 8), to_signed(15, 8), 
--			to_signed(16, 8), to_signed(17, 8), to_signed(18, 8), to_signed(19, 8), 
--			to_signed(20, 8), to_signed(21, 8), to_signed(22, 8), to_signed(23, 8), 
--			to_signed(24, 8), to_signed(25, 8), to_signed(26, 8), to_signed(27, 8), 
--			to_signed(28, 8), to_signed(29, 8), to_signed(30, 8), to_signed(31, 8)

			to_signed(0, 8), to_signed(1, 8), to_signed(2, 8), to_signed(3, 8), 
			to_signed(4, 8), to_signed(5, 8), to_signed(6, 8), to_signed(7, 8), 
			to_signed(8, 8), to_signed(9, 8), to_signed(10, 8), to_signed(11, 8), 
			to_signed(12, 8), to_signed(13, 8), to_signed(14, 8), to_signed(15, 8), 
			to_signed(16, 8), to_signed(17, 8), to_signed(18, 8), to_signed(19, 8), 
			to_signed(20, 8), to_signed(21, 8), to_signed(22, 8), to_signed(23, 8), 
			to_signed(24, 8), to_signed(25, 8), to_signed(26, 8), to_signed(27, 8), 
			to_signed(28, 8), to_signed(29, 8), to_signed(30, 8), to_signed(31, 8), 
			to_signed(32, 8), to_signed(33, 8), to_signed(34, 8), to_signed(35, 8), 
			to_signed(36, 8), to_signed(37, 8), to_signed(38, 8), to_signed(39, 8), 
			to_signed(40, 8), to_signed(41, 8), to_signed(42, 8), to_signed(43, 8), 
			to_signed(44, 8), to_signed(45, 8), to_signed(46, 8), to_signed(47, 8), 
			to_signed(48, 8), to_signed(49, 8), to_signed(50, 8), to_signed(51, 8), 
			to_signed(52, 8), to_signed(53, 8), to_signed(54, 8), to_signed(55, 8), 
			to_signed(56, 8), to_signed(57, 8), to_signed(58, 8), to_signed(59, 8), 
			to_signed(60, 8), to_signed(61, 8), to_signed(62, 8), to_signed(63, 8)
			);

	signal index : integer := 0;
	signal nindex : integer := 0;

	signal d_holder : std_logic_vector(31 downto 0) := (others => '0');
	signal d_next		: std_logic_vector(31 downto 0) := (others => '0');
	
	type state_type is (STOP, INPUT, END_STATE);
	signal state, nstate : state_type;
	
	signal HS, VS : std_logic;
	signal rgb : std_logic_vector(7 downto 0);
	signal px_clk : std_logic;
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: mem_to_vga PORT MAP (
          FSL_Clk => clk,
          FSL_Rst => rst,
          FSL_S_exists => exists,
          FSL_S_Read => rd_ack,
          FSL_S_Data => d_in,
			 
			 FSL_S_Clk => clk,
			 FSL_S_Control => '0',
			 
			pixel_clk => px_clk,
			HS => HS,
			VS => VS,
			rgb => rgb
        );
		  
   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
	
	clk_px_process :process
   begin
		px_clk <= '1';
		wait for clk_period*2;
		px_clk <= '0';
		wait for clk_period*2;
   end process;
 
	state_mach : process (clk, rst)
	
	begin
		if rst = '1' then
			d_holder <= (others => '0');
			index <= 0;
			state <= STOP;
			
		elsif clk'event and clk = '1' then
			d_holder <= d_next;
			d_in <= X"89ABCDEF";
			index <= nindex;
			state <= nstate;
			
		end if;
	end process;
	
	process (d_holder, index, state)
	
	begin
		
		d_next <= d_holder;
		nstate <= state;
		exists <= '0';
		
		case state is
		when STOP =>
			nstate <= INPUT;
			
		when INPUT =>
			exists <= '1';
		
		when END_STATE =>
		
		when OTHERS =>
			
		end case;
		

	
	end process;

   -- Stimulus process
   stim_proc: process
   begin		
		rst <= '1';
      wait for clk_period*10;
		rst <= '0';
      wait;
   end process;
	
END;
