Release 14.2 ngdbuild P.28xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p
xc6slx16csg324-3 -nt timestamp -bm system.bmm
C:/Temp/pushbox/implementation/system.ngc -uc system.ucf system.ngd

Reading NGO file "C:/Temp/pushbox/implementation/system.ngc" ...
Loading design module
"C:/Temp/pushbox/implementation/system_push_buttons_4bits_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_rs232_uart_1_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_proc_sys_reset_0_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_clock_generator_0_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_digilent_shared_mem_bus_mux_wrapper.ngc".
..
Loading design module
"C:/Temp/pushbox/implementation/system_microblaze_0_ilmb_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_microblaze_0_dlmb_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_axi4lite_0_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_microblaze_0_intc_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_microblaze_0_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_microblaze_0_i_bram_ctrl_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_microblaze_0_d_bram_ctrl_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_debug_module_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_axi_bram_ctrl_0_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_pushbox_disp_0_wrapper.ngc"...
Loading design module "C:/Temp/pushbox/implementation/BRAM_imgs.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_axi_plbv46_bridge_0_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_keyboard_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_plb_v46_0_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_microblaze_0_bram_block_wrapper.ngc"...
Loading design module
"C:/Temp/pushbox/implementation/system_axi_bram_ctrl_0_bram_block_wrapper.ngc"..
.
Applying constraints in
"C:/Temp/pushbox/implementation/system_microblaze_0_ilmb_wrapper.ncf" to module
"microblaze_0_ilmb"...
Checking Constraint Associations...
Applying constraints in
"C:/Temp/pushbox/implementation/system_microblaze_0_dlmb_wrapper.ncf" to module
"microblaze_0_dlmb"...
Checking Constraint Associations...
Applying constraints in
"C:/Temp/pushbox/implementation/system_axi4lite_0_wrapper.ncf" to module
"axi4lite_0"...
Checking Constraint Associations...
Applying constraints in
"C:/Temp/pushbox/implementation/system_microblaze_0_intc_wrapper.ncf" to module
"microblaze_0_intc"...
Checking Constraint Associations...
Applying constraints in
"C:/Temp/pushbox/implementation/system_microblaze_0_wrapper.ncf" to module
"microblaze_0"...
Checking Constraint Associations...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "system.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:135 - Constraint <INST
   /system/EXPANDED/system/axi4lite_0/axi4lite_0\/si_converter_bank\/gen_conv_sl
   ot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_INV_0 TNM =
   FFS:axi4lite_0_reset_resync>: No instances of type FFS were found under block
   "axi4lite_0/axi4lite_0/si_converter_bank/gen_conv_slot[0].clock_conv_inst/int
   erconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).

WARNING:ConstraintSystem:58 - Constraint <TIMEGRP axi4lite_0_reset_source = FFS
   PADS CPUS;>: CPUS "*" does not match any design objects.

WARNING:ConstraintSystem:194 - The TNM 'axi4lite_0_reset_resync', does not
   directly or indirectly drive any flip-flops, latches and/or RAMs and is not
   actively used by any referencing constraint.

INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
   'TS_sys_clk_pin', was traced into PLL_ADV instance
   clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst. The following new TNM
   groups and period specifications were generated at the PLL_ADV output(s): 
   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0 =
   PERIOD "clock_generator_0_clock_generator_0_SIG_PLL0_CLKOUT0" TS_sys_clk_pin
   * 0.5 HIGH 50%>

Done...

Processing BMM file "system.bmm" ...

Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
   'microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Decode_I/Using_FPGA.
   Gen_Bits[27].MEM_EX_Result_Inst' has unconnected output pin

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   4

Total memory usage is 244384 kilobytes

Writing NGD file "system.ngd" ...
Total REAL time to NGDBUILD completion:  44 sec
Total CPU time to NGDBUILD completion:   44 sec

Writing NGDBUILD log file "system.bld"...
