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-- system_stub.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity system_stub is
  port (
    RS232_Uart_1_sout : out std_logic;
    RS232_Uart_1_sin : in std_logic;
    RESET : in std_logic;
    Push_Buttons_4Bits_TRI_I : in std_logic_vector(0 to 3);
    GCLK : in std_logic;
    pushbox_disp_0_HS_pin : out std_logic;
    pushbox_disp_0_VS_pin : out std_logic;
    pushbox_disp_0_VGA_rgb_pin : out std_logic_vector(0 to 7);
    Digilent_Shared_Mem_Bus_Mux_Mem_Addr_O_pin : out std_logic_vector(25 downto 0);
    Digilent_Shared_Mem_Bus_Mux_Mem_OEN_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_Mem_WEN_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_S_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_C_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_CEN_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_RPN_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CEN_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_ADV_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CRE_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CLK_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_Wait_I_pin : in std_logic;
    Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_UB_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_LB_O_pin : out std_logic;
    Digilent_Shared_Mem_Bus_Mux_Mem_DQ : inout std_logic_vector(16 downto 0);
    keyboard_PS2_1_DATA_pin : inout std_logic;
    keyboard_PS2_1_CLK_pin : inout std_logic
  );
end system_stub;

architecture STRUCTURE of system_stub is

  component system is
    port (
      RS232_Uart_1_sout : out std_logic;
      RS232_Uart_1_sin : in std_logic;
      RESET : in std_logic;
      Push_Buttons_4Bits_TRI_I : in std_logic_vector(0 to 3);
      GCLK : in std_logic;
      pushbox_disp_0_HS_pin : out std_logic;
      pushbox_disp_0_VS_pin : out std_logic;
      pushbox_disp_0_VGA_rgb_pin : out std_logic_vector(0 to 7);
      Digilent_Shared_Mem_Bus_Mux_Mem_Addr_O_pin : out std_logic_vector(25 downto 0);
      Digilent_Shared_Mem_Bus_Mux_Mem_OEN_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_Mem_WEN_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_S_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_C_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_CEN_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_RPN_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CEN_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_ADV_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CRE_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CLK_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_Wait_I_pin : in std_logic;
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_UB_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_LB_O_pin : out std_logic;
      Digilent_Shared_Mem_Bus_Mux_Mem_DQ : inout std_logic_vector(16 downto 0);
      keyboard_PS2_1_DATA_pin : inout std_logic;
      keyboard_PS2_1_CLK_pin : inout std_logic
    );
  end component;

  attribute BOX_TYPE : STRING;
  attribute BOX_TYPE of system : component is "user_black_box";

begin

  system_i : system
    port map (
      RS232_Uart_1_sout => RS232_Uart_1_sout,
      RS232_Uart_1_sin => RS232_Uart_1_sin,
      RESET => RESET,
      Push_Buttons_4Bits_TRI_I => Push_Buttons_4Bits_TRI_I,
      GCLK => GCLK,
      pushbox_disp_0_HS_pin => pushbox_disp_0_HS_pin,
      pushbox_disp_0_VS_pin => pushbox_disp_0_VS_pin,
      pushbox_disp_0_VGA_rgb_pin => pushbox_disp_0_VGA_rgb_pin,
      Digilent_Shared_Mem_Bus_Mux_Mem_Addr_O_pin => Digilent_Shared_Mem_Bus_Mux_Mem_Addr_O_pin,
      Digilent_Shared_Mem_Bus_Mux_Mem_OEN_O_pin => Digilent_Shared_Mem_Bus_Mux_Mem_OEN_O_pin,
      Digilent_Shared_Mem_Bus_Mux_Mem_WEN_O_pin => Digilent_Shared_Mem_Bus_Mux_Mem_WEN_O_pin,
      Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_S_O_pin => Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_S_O_pin,
      Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_C_O_pin => Digilent_Shared_Mem_Bus_Mux_QSPI_Mem_C_O_pin,
      Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_CEN_O_pin => Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_CEN_O_pin,
      Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_RPN_O_pin => Digilent_Shared_Mem_Bus_Mux_FLASH_Mem_RPN_O_pin,
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CEN_O_pin => Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CEN_O_pin,
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_ADV_O_pin => Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_ADV_O_pin,
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CRE_O_pin => Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CRE_O_pin,
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CLK_O_pin => Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_CLK_O_pin,
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_Wait_I_pin => Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_Wait_I_pin,
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_UB_O_pin => Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_UB_O_pin,
      Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_LB_O_pin => Digilent_Shared_Mem_Bus_Mux_PSRAM_Mem_LB_O_pin,
      Digilent_Shared_Mem_Bus_Mux_Mem_DQ => Digilent_Shared_Mem_Bus_Mux_Mem_DQ,
      keyboard_PS2_1_DATA_pin => keyboard_PS2_1_DATA_pin,
      keyboard_PS2_1_CLK_pin => keyboard_PS2_1_CLK_pin
    );

end architecture STRUCTURE;

