Change log for axi_bram_ctrl

13.3 - Changes in VHDL/Verilog/Netlist sources (.vhd, .v, .ngc, .edn)

 New Features:

• Support BRAM data widths up to 1024-bit.
• Updated ECC algorithm to Hsiao encoding for 32/64/128 bit data widths.

Resolved Issues:

• [<CR602979>][<CR602530>]AXI4-Lite interface is made AXI specification compliant with respect to removing combinatorial paths from input to output on the same AXI interface.
• [<CR623710>]Resolved issues when data2mem is used to pre-initialize BRAM memory and ECC is enabled and connected to BRAM Block where BRAM primitives are natively 1-bit, 16-bits or 32-bits wide. Note: These are the largest and 2 smallest possible BRAM Block sizes for a given data width and generally are not chosen. This issue does not affect memory initialized by downloading code using XMD, it only affects data2mem initialized memory in the bitstream.
• [<CR609695>]Resolved issue where AXI BRAM Controller may observe WLAST asserted and interpret it as terminating an outstanding write when WVALID was not yet asserted. Issue fixed so that WLAST is only observed when WVALID and WREADY are asserted.

• AXI BRAM Controller with ECC enabled cannot share a dual port BRAM Block with LMB BRAM Controller with ECC enabled.

13.3 - Changes in tool interface files(.mpd)

• None
  

13.3 - Changes in Tcl script files associated with core (.tcl)

• [<CR616287>]Added DRC to explicitly signal error when data width is not 32 and AXI4-Lite mode is enabled. This is an unsupported configuration.

13.3 - Changes in documentation associated with core

• [<CR594714>]Minor updates including updates to register descriptions.