Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "microblaze_0_wrapper_xst.prj"
Verilog Include Directory          : {"C:\Temp\Bomberman\pcores\" "C:\Xilinx\12.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc3s1200efg320-4
Output File Name                   : "../implementation/microblaze_0_wrapper.ngc"

---- Source Options
Top Module Name                    : microblaze_0_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation/microblaze_0_wrapper}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/microblaze_types_pkg.vhd" in Library microblaze_v7_30_b.
Package <MicroBlaze_Types> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/microblaze_types_pkg_body.vhd" in Library microblaze_v7_30_b.
Package body <MicroBlaze_Types> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/microblaze_isa_be_pkg.vhd" in Library microblaze_v7_30_b.
Package <MicroBlaze_ISA> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/carry_and.vhd" in Library microblaze_v7_30_b.
Entity <carry_and> compiled.
Entity <carry_and> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/dsp_module.vhd" in Library microblaze_v7_30_b.
Entity <dsp_module> compiled.
Entity <dsp_module> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/find_first_bit.vhd" in Library microblaze_v7_30_b.
Entity <find_first_bit> compiled.
Entity <find_first_bit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/mmu_types_pkg.vhd" in Library microblaze_v7_30_b.
Package <MMU_Types> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/carry_compare_mask.vhd" in Library microblaze_v7_30_b.
Entity <carry_compare_mask> compiled.
Entity <carry_compare_mask> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/carry_compare.vhd" in Library microblaze_v7_30_b.
Entity <carry_compare> compiled.
Entity <carry_compare> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/mmu_utlb_ram.vhd" in Library microblaze_v7_30_b.
Entity <MMU_UTLB_RAM> compiled.
Entity <MMU_UTLB_RAM> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/comparator.vhd" in Library microblaze_v7_30_b.
Entity <comparator> compiled.
Entity <comparator> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/carry_compare_const.vhd" in Library microblaze_v7_30_b.
Entity <carry_compare_const> compiled.
Entity <carry_compare_const> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/fpu_addsub.vhd" in Library microblaze_v7_30_b.
Entity <FPU_ADDSUB> compiled.
Entity <FPU_ADDSUB> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/fpu_mul.vhd" in Library microblaze_v7_30_b.
Entity <FPU_MUL> compiled.
Entity <FPU_MUL> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/fpu_div.vhd" in Library microblaze_v7_30_b.
Entity <FPU_DIV> compiled.
Entity <FPU_DIV> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/fpu_sqrt.vhd" in Library microblaze_v7_30_b.
Entity <fpu_sqrt> compiled.
Entity <fpu_sqrt> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/fpu_conv.vhd" in Library microblaze_v7_30_b.
Entity <fpu_conv> compiled.
Entity <fpu_conv> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/wb_mux_bit_gti.vhd" in Library microblaze_v7_30_b.
Entity <WB_Mux_Bit> compiled.
Entity <WB_Mux_Bit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/carry_equal.vhd" in Library microblaze_v7_30_b.
Entity <carry_equal> compiled.
Entity <carry_equal> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/alu_bit.vhd" in Library microblaze_v7_30_b.
Entity <ALU_Bit> compiled.
Entity <ALU_Bit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/ram_module.vhd" in Library microblaze_v7_30_b.
Entity <RAM_Module> compiled.
Entity <RAM_Module> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/carry_or.vhd" in Library microblaze_v7_30_b.
Entity <carry_or> compiled.
Entity <carry_or> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/cache_valid_bit_detect.vhd" in Library microblaze_v7_30_b.
Entity <cache_valid_bit_detect> compiled.
Entity <cache_valid_bit_detect> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/pc_bit.vhd" in Library microblaze_v7_30_b.
Entity <PC_Bit> compiled.
Entity <PC_Bit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/msr_reg_bit.vhd" in Library microblaze_v7_30_b.
Entity <MSR_Reg_Bit> compiled.
Entity <MSR_Reg_Bit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/result_mux_bit.vhd" in Library microblaze_v7_30_b.
Entity <Result_Mux_Bit> compiled.
Entity <Result_Mux_Bit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/shift_logic_bit.vhd" in Library microblaze_v7_30_b.
Entity <Shift_Logic_Bit> compiled.
Entity <Shift_Logic_Bit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select_bit.vhd" in Library microblaze_v7_30_b.
Entity <Operand_Select_Bit> compiled.
Entity <Operand_Select_Bit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/register_file_bit.vhd" in Library microblaze_v7_30_b.
Entity <Register_File_Bit> compiled.
Entity <Register_File_Bit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/mmu_utlb.vhd" in Library microblaze_v7_30_b.
Entity <MMU_UTLB> compiled.
Entity <MMU_UTLB> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/mmu_tlb.vhd" in Library microblaze_v7_30_b.
Entity <MMU_TLB> compiled.
Entity <MMU_TLB> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/address_hit.vhd" in Library microblaze_v7_30_b.
Entity <address_hit> compiled.
Entity <address_hit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/address_data_hit.vhd" in Library microblaze_v7_30_b.
Entity <address_data_hit> compiled.
Entity <address_data_hit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/cache_interface.vhd" in Library microblaze_v7_30_b.
Entity <Cache_Interface> compiled.
Entity <Cache_Interface> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/register_file_gti.vhd" in Library microblaze_v7_30_b.
Entity <Register_File_gti> compiled.
Entity <Register_File_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select_gti.vhd" in Library microblaze_v7_30_b.
Entity <Operand_Select_gti> compiled.
Entity <Operand_Select_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/alu.vhd" in Library microblaze_v7_30_b.
Entity <ALU> compiled.
Entity <ALU> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/shift_logic_gti.vhd" in Library microblaze_v7_30_b.
Entity <Shift_Logic_Module_gti> compiled.
Entity <Shift_Logic_Module_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/mul_unit.vhd" in Library microblaze_v7_30_b.
Entity <mul_unit> compiled.
Entity <mul_unit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/barrel_shifter_gti.vhd" in Library microblaze_v7_30_b.
Entity <Barrel_Shifter_gti> compiled.
Entity <Barrel_Shifter_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/wb_mux_gti.vhd" in Library microblaze_v7_30_b.
Entity <WB_Mux> compiled.
Entity <WB_Mux> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/zero_detect_gti.vhd" in Library microblaze_v7_30_b.
Entity <Zero_Detect_gti> compiled.
Entity <Zero_Detect_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/byte_doublet_handle_gti.vhd" in Library microblaze_v7_30_b.
Entity <Byte_Doublet_Handle_gti> compiled.
Entity <Byte_Doublet_Handle_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/data_flow_logic_gti.vhd" in Library microblaze_v7_30_b.
Entity <Data_Flow_Logic> compiled.
Entity <Data_Flow_Logic> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/msr_reg_gti.vhd" in Library microblaze_v7_30_b.
Entity <msr_reg_gti> compiled.
Entity <msr_reg_gti> (Architecture <msr_reg>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/exception_registers_gti.vhd" in Library microblaze_v7_30_b.
Entity <exception_registers_gti> compiled.
Entity <exception_registers_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/div_unit_gti.vhd" in Library microblaze_v7_30_b.
Entity <Div_unit_gti> compiled.
Entity <Div_unit_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/fpu.vhd" in Library microblaze_v7_30_b.
Entity <Fpu> compiled.
Entity <Fpu> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/pvr.vhd" in Library microblaze_v7_30_b.
Entity <PVR> compiled.
Entity <PVR> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/pc_module_gti.vhd" in Library microblaze_v7_30_b.
Entity <PC_Module_gti> compiled.
Entity <PC_Module_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/prefetch_buffer_gti.vhd" in Library microblaze_v7_30_b.
Entity <PreFetch_Buffer_gti> compiled.
Entity <PreFetch_Buffer_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/jump_logic_gti.vhd" in Library microblaze_v7_30_b.
Entity <jump_logic> compiled.
Entity <jump_logic> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/mux_bus.vhd" in Library microblaze_v7_30_b.
Entity <mux_bus> compiled.
Entity <mux_bus> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/cachehit_detect.vhd" in Library microblaze_v7_30_b.
Entity <cachehit_detect> compiled.
Entity <cachehit_detect> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/victim_cache.vhd" in Library microblaze_v7_30_b.
Entity <LRU_Module> compiled.
Entity <LRU_Module> (Architecture <LRU_Module>) compiled.
Entity <victim_cache> compiled.
Entity <victim_cache> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/stream_cache.vhd" in Library microblaze_v7_30_b.
Entity <stream_cache> compiled.
Entity <stream_cache> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/data_read_steering.vhd" in Library microblaze_v7_30_b.
Entity <Data_Read_Steering> compiled.
Entity <Data_Read_Steering> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/mux4_8.vhd" in Library microblaze_v7_30_b.
Entity <mux4_8> compiled.
Entity <mux4_8> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/register_file.vhd" in Library microblaze_v7_30_b.
Entity <Register_File> compiled.
Entity <Register_File> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select.vhd" in Library microblaze_v7_30_b.
Entity <Operand_Select> compiled.
Entity <Operand_Select> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/shift_logic.vhd" in Library microblaze_v7_30_b.
Entity <Shift_Logic_Module> compiled.
Entity <Shift_Logic_Module> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/barrel_shifter.vhd" in Library microblaze_v7_30_b.
Entity <barrel_shift> compiled.
Entity <barrel_shift> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/div_unit.vhd" in Library microblaze_v7_30_b.
Entity <Div_unit> compiled.
Entity <Div_unit> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/result_mux.vhd" in Library microblaze_v7_30_b.
Entity <Result_Mux> compiled.
Entity <Result_Mux> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/zero_detect.vhd" in Library microblaze_v7_30_b.
Entity <Zero_Detect> compiled.
Entity <Zero_Detect> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/msr_reg.vhd" in Library microblaze_v7_30_b.
Entity <MSR_Reg> compiled.
Entity <MSR_Reg> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/pc_module.vhd" in Library microblaze_v7_30_b.
Entity <PC_Module> compiled.
Entity <PC_Module> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/prefetch_buffer.vhd" in Library microblaze_v7_30_b.
Entity <PreFetch_Buffer> compiled.
Entity <PreFetch_Buffer> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/fsl_module.vhd" in Library microblaze_v7_30_b.
Entity <FSL_Module> compiled.
Entity <FSL_Module> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/interrupt_mode_converter.vhd" in Library microblaze_v7_30_b.
Entity <interrupt_mode_converter> compiled.
Entity <interrupt_mode_converter> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/decode.vhd" in Library microblaze_v7_30_b.
Entity <Decode> compiled.
Entity <Decode> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/data_flow.vhd" in Library microblaze_v7_30_b.
Entity <Data_Flow> compiled.
Entity <Data_Flow> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/byte_doublet_handle.vhd" in Library microblaze_v7_30_b.
Entity <Byte_Doublet_Handle> compiled.
Entity <Byte_Doublet_Handle> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/dplb_interface.vhd" in Library microblaze_v7_30_b.
Entity <DPLB_Interface> compiled.
Entity <DPLB_Interface> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/iplb_interface.vhd" in Library microblaze_v7_30_b.
Entity <IPLB_Interface> compiled.
Entity <IPLB_Interface> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/debug.vhd" in Library microblaze_v7_30_b.
Entity <Debug> compiled.
Entity <Debug> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/icache.vhd" in Library microblaze_v7_30_b.
Entity <Icache> compiled.
Entity <Icache> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/dcache_wb.vhd" in Library microblaze_v7_30_b.
Entity <DCache_wb> compiled.
Entity <DCache_wb> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/dcache.vhd" in Library microblaze_v7_30_b.
Entity <DCache> compiled.
Entity <DCache> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/exception_registers.vhd" in Library microblaze_v7_30_b.
Entity <exception_registers> compiled.
Entity <exception_registers> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" in Library microblaze_v7_30_b.
Entity <instr_mux> compiled.
Entity <instr_mux> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/decode_gti.vhd" in Library microblaze_v7_30_b.
Entity <Decode_gti> compiled.
Entity <Decode_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/data_flow_gti.vhd" in Library microblaze_v7_30_b.
Entity <Data_Flow_gti> compiled.
Entity <Data_Flow_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/read_data_mux_gti.vhd" in Library microblaze_v7_30_b.
Entity <read_data_mux> compiled.
Entity <read_data_mux> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/dcache_gti.vhd" in Library microblaze_v7_30_b.
Entity <DCache_gti> compiled.
Entity <DCache_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/debug_gti.vhd" in Library microblaze_v7_30_b.
Entity <Debug_gti_fix> compiled.
Entity <Debug_gti_fix> (Architecture <IMP>) compiled.
Entity <Debug_gti> compiled.
Entity <Debug_gti> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/mmu.vhd" in Library microblaze_v7_30_b.
Entity <MMU> compiled.
Entity <MMU> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/mux4.vhd" in Library microblaze_v7_30_b.
Entity <mux4> compiled.
Entity <mux4> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/gen_srlfifo.vhd" in Library microblaze_v7_30_b.
Entity <srl_fifo> compiled.
Entity <srl_fifo> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/microblaze.vhd" in Library microblaze_v7_30_b.
Entity <MicroBlaze> compiled.
WARNING:HDLParsers:3293 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/microblaze.vhd" Line 704. Constant 'C_CORE_GENERATION_INFO' C_CORE_GENERATION_INFO is not locally static.
Entity <MicroBlaze> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/hdl/microblaze_0_wrapper.vhd" in Library work.
Entity <microblaze_0_wrapper> compiled.
Entity <microblaze_0_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <microblaze_0_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <microblaze> in library <microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_ADDR_TAG_BITS = 0
	C_ALLOW_DCACHE_WR = 1
	C_ALLOW_ICACHE_WR = 1
	C_AREA_OPTIMIZED = 1
	C_BRANCH_TARGET_CACHE_SIZE = 0
	C_CACHE_BYTE_SIZE = 8192
	C_DATA_SIZE = 32
	C_DCACHE_ADDR_TAG = 0
	C_DCACHE_ALWAYS_USED = 0
	C_DCACHE_BASEADDR = "00000000000000000000000000000000"
	C_DCACHE_BYTE_SIZE = 8192
	C_DCACHE_HIGHADDR = "00111111111111111111111111111111"
	C_DCACHE_INTERFACE = 0
	C_DCACHE_LINE_LEN = 4
	C_DCACHE_USE_FSL = 1
	C_DCACHE_USE_WRITEBACK = 0
	C_DCACHE_VICTIMS = 0
	C_DEBUG_ENABLED = 1
	C_DIV_ZERO_EXCEPTION = 0
	C_DPLB_BURST_EN = 0
	C_DPLB_BUS_EXCEPTION = 0
	C_DPLB_DWIDTH = 32
	C_DPLB_NATIVE_DWIDTH = 32
	C_DPLB_P2P = 0
	C_DYNAMIC_BUS_SIZING = 1
	C_D_LMB = 1
	C_D_PLB = 1
	C_EDGE_IS_POSITIVE = 1
	C_FAMILY = "spartan3e"
	C_FPU_EXCEPTION = 0
	C_FREQ = 50000000
	C_FSL_DATA_SIZE = 32
	C_FSL_EXCEPTION = 0
	C_FSL_LINKS = 0
	C_ICACHE_ALWAYS_USED = 0
	C_ICACHE_BASEADDR = "00000000000000000000000000000000"
	C_ICACHE_HIGHADDR = "00111111111111111111111111111111"
	C_ICACHE_INTERFACE = 0
	C_ICACHE_LINE_LEN = 4
	C_ICACHE_STREAMS = 0
	C_ICACHE_USE_FSL = 1
	C_ICACHE_VICTIMS = 0
	C_ILL_OPCODE_EXCEPTION = 0
	C_INSTANCE = "microblaze_0"
	C_INTERCONNECT = 1
	C_INTERRUPT_IS_EDGE = 0
	C_IPLB_BURST_EN = 0
	C_IPLB_BUS_EXCEPTION = 0
	C_IPLB_DWIDTH = 32
	C_IPLB_NATIVE_DWIDTH = 32
	C_IPLB_P2P = 0
	C_I_LMB = 1
	C_I_PLB = 1
	C_MMU_DTLB_SIZE = 4
	C_MMU_ITLB_SIZE = 2
	C_MMU_TLB_ACCESS = 3
	C_MMU_ZONES = 16
	C_NUMBER_OF_PC_BRK = 1
	C_NUMBER_OF_RD_ADDR_BRK = 0
	C_NUMBER_OF_WR_ADDR_BRK = 0
	C_OPCODE_0x0_ILLEGAL = 0
	C_OPTIMIZATION = 0
	C_PVR = 0
	C_PVR_USER1 = "00000000"
	C_PVR_USER2 = "00000000000000000000000000000000"
	C_RESET_MSR = "00000000000000000000000000000000"
	C_SCO = 0
	C_STREAM_INTERCONNECT = 0
	C_UNALIGNED_EXCEPTIONS = 0
	C_USE_BARREL = 0
	C_USE_BRANCH_TARGET_CACHE = 0
	C_USE_DCACHE = 0
	C_USE_DIV = 0
	C_USE_EXTENDED_FSL_INSTR = 0
	C_USE_EXT_BRK = 1
	C_USE_EXT_NM_BRK = 1
	C_USE_FPU = 0
	C_USE_HW_MUL = 1
	C_USE_ICACHE = 0
	C_USE_INTERRUPT = 1
	C_USE_MMU = 0
	C_USE_MSR_INSTR = 1
	C_USE_PCMP_INSTR = 1

Analyzing hierarchy for entity <interrupt_mode_converter> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_EDGE_IS_POSITIVE = true
	C_INTERRUPT_IS_EDGE = false

Analyzing hierarchy for entity <Decode> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_ALLOW_DCACHE_WR = 1
	C_ALLOW_ICACHE_WR = 1
	C_ALLOW_LUT6 = true
	C_DATA_SIZE = 32
	C_DCACHE_USE_WRITEBACK = 0
	C_DEBUG_ENABLED = 1
	C_DETECT_DIV_OVERFLOW = 1
	C_DETECT_OPCODE_0x0 = false
	C_DIV_ZERO_EXCEPTION = 0
	C_DPLB_BUS_EXCEPTION = 0
	C_FPU_EXCEPTION = 0
	C_FSL_EXCEPTION = 0
	C_FSL_LINKS = 0
	C_ILL_OPCODE_EXCEPTION = 0
	C_IPLB_BUS_EXCEPTION = 0
	C_M_AXI_D_BUS_EXCEPTION = 0
	C_M_AXI_I_BUS_EXCEPTION = 0
	C_PVR = 0
	C_TARGET = "spartan3e"
	C_UNALIGNED_EXCEPTIONS = 0
	C_USE_BARREL = 0
	C_USE_DCACHE = 0
	C_USE_DIV = 0
	C_USE_EXTENDED_FSL_INSTR = 0
	C_USE_EXT_BRK = true
	C_USE_EXT_NM_BRK = true
	C_USE_FPU = 0
	C_USE_ICACHE = 0
	C_USE_INTERRUPT = true
	C_USE_LWX_SWX_EXCLUSIVE = false
	C_USE_LWX_SWX_INSTR = true
	C_USE_MSR_INSTR = 1
	C_USE_MUL64 = false
	C_USE_MUL_INSTR = true
	C_USE_PCMP_INSTR = true

Analyzing hierarchy for entity <Data_Flow> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_ADDR_TAG_BITS = 0
	C_ALLOW_DCACHE_WR = 1
	C_ALLOW_ICACHE_WR = 1
	C_ALLOW_LUT6 = true
	C_AREA_OPTIMIZED = 1
	C_BTC_SIZE = 0
	C_BUFFER_SIZE = 16
	C_CACHE_BYTE_SIZE = 8192
	C_DATA_SIZE = 32
	C_DCACHE_ADDR_TAG = 0
	C_DCACHE_ALWAYS_USED = 0
	C_DCACHE_BASEADDR = "00000000000000000000000000000000"
	C_DCACHE_BYTE_SIZE = 8192
	C_DCACHE_HIGHADDR = "00111111111111111111111111111111"
	C_DCACHE_INTERFACE = 0
	C_DCACHE_LINE_LEN = 4
	C_DCACHE_USE_FSL = 1
	C_DCACHE_USE_WRITEBACK = 0
	C_DCACHE_VICTIMS = 0
	C_DEBUG_ENABLED = 1
	C_DETECT_DIV_OVERFLOW = 1
	C_DIV_ZERO_EXCEPTION = 0
	C_DPLB_BUS_EXCEPTION = 0
	C_D_AXI = 0
	C_D_LMB = 1
	C_D_PLB = 1
	C_EDGE_IS_POSITIVE = 1
	C_EXCEPTION_ADDR = "00000020"
	C_EXT_BRK_ADDR = "00000018"
	C_FPU_EXCEPTION = 0
	C_FSL_EXCEPTION = 0
	C_FSL_LINKS = 0
	C_ICACHE_ALWAYS_USED = 0
	C_ICACHE_BASEADDR = "00000000000000000000000000000000"
	C_ICACHE_HIGHADDR = "00111111111111111111111111111111"
	C_ICACHE_INTERFACE = 0
	C_ICACHE_LINE_LEN = 4
	C_ICACHE_STREAMS = 0
	C_ICACHE_USE_FSL = 1
	C_ICACHE_VICTIMS = 0
	C_ILL_OPCODE_EXCEPTION = 0
	C_INTERCONNECT = 1
	C_INTERRUPT_ADDR = "00000010"
	C_INTERRUPT_IS_EDGE = 0
	C_IPLB_BUS_EXCEPTION = 0
	C_I_AXI = 0
	C_I_LMB = 1
	C_I_PLB = 1
	C_MAX_FSL_LINKS = 16
	C_MB_VERSION = "00010001"
	C_MMU_DTLB_SIZE = 4
	C_MMU_ITLB_SIZE = 2
	C_MMU_TLB_ACCESS = 3
	C_MMU_ZONES = 16
	C_M_AXI_D_BUS_EXCEPTION = 0
	C_M_AXI_I_BUS_EXCEPTION = 0
	C_NUMBER_OF_PC_BRK = 1
	C_NUMBER_OF_RD_ADDR_BRK = 0
	C_NUMBER_OF_WR_ADDR_BRK = 0
	C_OPCODE_0x0_ILLEGAL = 0
	C_PC_START_ADDR = "00000000"
	C_PVR = 0
	C_PVR_USER1 = "00000000"
	C_PVR_USER2 = "00000000000000000000000000000000"
	C_RESET_MSR = "000000000000000"
	C_STREAM_INTERCONNECT = 0
	C_TARGET = "spartan3e"
	C_UNALIGNED_EXCEPTIONS = 0
	C_USE_BARREL = 0
	C_USE_BTC = false
	C_USE_DCACHE = 0
	C_USE_DIV = 0
	C_USE_EXCEPTIONS = false
	C_USE_EXTENDED_FSL_INSTR = 0
	C_USE_FPU = 0
	C_USE_HW_MUL = true
	C_USE_ICACHE = 0
	C_USE_MMU = 0
	C_USE_MSR_INSTR = 1
	C_USE_MUL64 = false
	C_USE_PCMP_INSTR = true

Analyzing hierarchy for entity <Byte_Doublet_Handle> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_ALLOW_LUT6 = true
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <DPLB_Interface> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DELAYED_DATA_STROBE = false
	C_DPLB_WIDTH = 32
	C_OUTPUT_DFFS = true

Analyzing hierarchy for entity <IPLB_Interface> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_IPLB_DWIDTH = 32

Analyzing hierarchy for entity <Debug> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DATA_SIZE = 32
	C_DCACHE_BASEADDR = "00000000000000000000000000000000"
	C_DCACHE_HIGHADDR = "00111111111111111111111111111111"
	C_DCACHE_USE_FSL = 1
	C_DCACHE_USE_WRITEBACK = 0
	C_DIV_ZERO_EXCEPTION = 0
	C_DPLB_BUS_EXCEPTION = 0
	C_FPU_EXCEPTION = 0
	C_FSL_EXCEPTION = 0
	C_FSL_LINKS = 0
	C_ICACHE_BASEADDR = "00000000000000000000000000000000"
	C_ICACHE_HIGHADDR = "00111111111111111111111111111111"
	C_ICACHE_USE_FSL = 1
	C_ILL_OPCODE_EXCEPTION = 0
	C_INTERCONNECT = 1
	C_IPLB_BUS_EXCEPTION = 0
	C_MB_VERSION = "00010001"
	C_M_AXI_D_BUS_EXCEPTION = 0
	C_M_AXI_I_BUS_EXCEPTION = 0
	C_NUMBER_OF_PC_BRK = 1
	C_NUMBER_OF_RD_ADDR_BRK = 0
	C_NUMBER_OF_WR_ADDR_BRK = 0
	C_PVR = 0
	C_PVR_USER1 = "00000000"
	C_PVR_USER2 = "00000000000000000000000000000000"
	C_STREAM_INTERCONNECT = 0
	C_TARGET = "spartan3e"
	C_UNALIGNED_EXCEPTIONS = 0
	C_USE_BARREL = 0
	C_USE_DCACHE = 0
	C_USE_DIV = 0
	C_USE_EXTENDED_FSL_INSTR = 0
	C_USE_FPU = 0
	C_USE_HW_MUL = 1
	C_USE_ICACHE = 0
	C_USE_MSR_INSTR = 1
	C_USE_PCMP_INSTR = 1

Analyzing hierarchy for entity <instr_mux> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_ALLOW_LUT6 = true
	C_DEBUG_ENABLED = true
	C_TARGET = "spartan3e"
	C_USE_ICACHE = false
	C_USE_I_EXT = true
	C_USE_I_LMB = true

Analyzing hierarchy for entity <PreFetch_Buffer> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_FSL_ATOMIC = 0
	C_IEXT_BUS_EXCEPTION = 0
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Register_File> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DATA_SIZE = 32
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Operand_Select> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DATA_SIZE = 32
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR = "00000020"
	C_EXT_BRK_ADDR = "00000018"
	C_FSL_EXCEPTION = false
	C_INTERRUPT_ADDR = "00000010"
	C_PVR = 0
	C_TARGET = "spartan3e"
	C_USE_EXCEPTIONS = false
	C_USE_FPU_bool = false

Analyzing hierarchy for entity <ALU> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_ALLOW_LUT6 = true
	C_AREA_OPTIMIZED = 1
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Shift_Logic_Module> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DATA_SIZE = 32
	C_TARGET = "spartan3e"
	C_USE_PCMP_INSTR = true

Analyzing hierarchy for entity <mul_unit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_TARGET = "spartan3e"
	C_USE_HW_MUL = true
	C_USE_MUL64 = false

Analyzing hierarchy for entity <Result_Mux> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DATA_SIZE = 32
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Zero_Detect> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DATA_SIZE = 32
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <MSR_Reg> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DATA_SIZE = 32
	C_FSL_LINKS = 0
	C_PVR = 0
	C_RESET_MSR = "000000000000000"
	C_TARGET = "spartan3e"
	C_USE_DCACHE = false
	C_USE_DIV = false
	C_USE_EXCEPTIONS = false
	C_USE_ICACHE = false
	C_USE_MSR_INSTR = 1

Analyzing hierarchy for entity <PC_Module> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DATA_SIZE = 32
	C_PC_START_ADDR = "00000000"
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <PVR> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_ADDR_TAG_BITS = 0
	C_ALLOW_DCACHE_WR = 1
	C_ALLOW_ICACHE_WR = 1
	C_AREA_OPTIMIZED = true
	C_BTC_SIZE = 0
	C_CACHE_BYTE_SIZE = 8192
	C_DCACHE_ADDR_TAG = 0
	C_DCACHE_ALWAYS_USED = 0
	C_DCACHE_BASEADDR = "00000000000000000000000000000000"
	C_DCACHE_BYTE_SIZE = 8192
	C_DCACHE_HIGHADDR = "00111111111111111111111111111111"
	C_DCACHE_INTERFACE = 0
	C_DCACHE_LINE_LEN = 4
	C_DCACHE_USE_FSL = 1
	C_DCACHE_USE_WRITEBACK = 0
	C_DCACHE_VICTIMS = 0
	C_DEBUG_ENABLED = 1
	C_DIV_ZERO_EXCEPTION = 0
	C_DPLB_BUS_EXCEPTION = 0
	C_D_AXI = 0
	C_D_LMB = 1
	C_D_PLB = 1
	C_EDGE_IS_POSITIVE = 1
	C_FPU_EXCEPTION = 0
	C_FSL_EXCEPTION = 0
	C_FSL_LINKS = 0
	C_ICACHE_ALWAYS_USED = 0
	C_ICACHE_BASEADDR = "00000000000000000000000000000000"
	C_ICACHE_HIGHADDR = "00111111111111111111111111111111"
	C_ICACHE_INTERFACE = 0
	C_ICACHE_LINE_LEN = 4
	C_ICACHE_STREAMS = 0
	C_ICACHE_USE_FSL = 1
	C_ICACHE_VICTIMS = 0
	C_ILL_OPCODE_EXCEPTION = 0
	C_INTERCONNECT = 1
	C_INTERRUPT_IS_EDGE = 0
	C_IPLB_BUS_EXCEPTION = 0
	C_I_AXI = 0
	C_I_LMB = 1
	C_I_PLB = 1
	C_MB_VERSION = "00010001"
	C_MMU_DTLB_SIZE = 4
	C_MMU_ITLB_SIZE = 2
	C_MMU_TLB_ACCESS = 3
	C_MMU_ZONES = 16
	C_M_AXI_D_BUS_EXCEPTION = 0
	C_M_AXI_I_BUS_EXCEPTION = 0
	C_NUMBER_OF_PC_BRK = 1
	C_NUMBER_OF_RD_ADDR_BRK = 0
	C_NUMBER_OF_WR_ADDR_BRK = 0
	C_OPCODE_0x0_ILLEGAL = 0
	C_PVR = 0
	C_PVR_USER1 = "00000000"
	C_PVR_USER2 = "00000000000000000000000000000000"
	C_RESET_MSR = "000000000000000"
	C_STREAM_INTERCONNECT = 0
	C_TARGET = "spartan3e"
	C_UNALIGNED_EXCEPTIONS = 0
	C_USE_BARREL = false
	C_USE_BTC = false
	C_USE_DCACHE = 0
	C_USE_DIV = false
	C_USE_EXTENDED_FSL_INSTR = 0
	C_USE_FPU = 0
	C_USE_HW_MUL = true
	C_USE_ICACHE = 0
	C_USE_MMU = 0
	C_USE_MSR_INSTR = true
	C_USE_MUL64 = false
	C_USE_PCMP_INSTR = true

Analyzing hierarchy for entity <Data_Read_Steering> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_ALLOW_LUT6 = true
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <mux4_8> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_ALLOW_LUT6 = true
	C_BE = true
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <address_hit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_FIRST = true
	C_TARGET = "spartan3e"
	No_Bits = 32

Analyzing hierarchy for entity <Register_File_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Operand_Select_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = true
	C_ONLY_PC = false
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Operand_Select_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = false
	C_ONLY_PC = false
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Operand_Select_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '1'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = false
	C_ONLY_PC = false
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Operand_Select_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '1'
	C_INTERRUPT_ADDR_BIT = '1'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = false
	C_ONLY_PC = false
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Operand_Select_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '1'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = false
	C_ONLY_PC = false
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Operand_Select_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = false
	C_ONLY_PC = true
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Operand_Select_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = false
	C_LSB_BIT = false
	C_ONLY_PC = true
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Operand_Select_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = false
	C_LSB_BIT = false
	C_ONLY_PC = false
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <ALU_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_ALLOW_LUT6 = true
	C_LAST_BIT = false
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <ALU_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_ALLOW_LUT6 = true
	C_LAST_BIT = true
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <Shift_Logic_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <carry_equal> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_TARGET = "spartan3e"
	Size = 8

Analyzing hierarchy for entity <Result_Mux_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <MSR_Reg_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <PC_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_RESET_VALUE = '0'
	C_TARGET = "spartan3e"

Analyzing hierarchy for entity <PC_Bit> in library <Microblaze_v7_30_b> (architecture <IMP>) with generics.
	C_RESET_VALUE = '1'
	C_TARGET = "spartan3e"


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <microblaze_0_wrapper> in library <work> (Architecture <STRUCTURE>).
Entity <microblaze_0_wrapper> analyzed. Unit <microblaze_0_wrapper> generated.

Analyzing generic Entity <microblaze> in library <microblaze_v7_30_b> (Architecture <IMP>).
	C_ADDR_TAG_BITS = 0
	C_ALLOW_DCACHE_WR = 1
	C_ALLOW_ICACHE_WR = 1
	C_AREA_OPTIMIZED = 1
	C_BRANCH_TARGET_CACHE_SIZE = 0
	C_CACHE_BYTE_SIZE = 8192
	C_DATA_SIZE = 32
	C_DCACHE_ADDR_TAG = 0
	C_DCACHE_ALWAYS_USED = 0
	C_DCACHE_BASEADDR = "00000000000000000000000000000000"
	C_DCACHE_BYTE_SIZE = 8192
	C_DCACHE_HIGHADDR = "00111111111111111111111111111111"
	C_DCACHE_INTERFACE = 0
	C_DCACHE_LINE_LEN = 4
	C_DCACHE_USE_FSL = 1
	C_DCACHE_USE_WRITEBACK = 0
	C_DCACHE_VICTIMS = 0
	C_DEBUG_ENABLED = 1
	C_DIV_ZERO_EXCEPTION = 0
	C_DPLB_BURST_EN = 0
	C_DPLB_BUS_EXCEPTION = 0
	C_DPLB_DWIDTH = 32
	C_DPLB_NATIVE_DWIDTH = 32
	C_DPLB_P2P = 0
	C_DYNAMIC_BUS_SIZING = 1
	C_D_LMB = 1
	C_D_PLB = 1
	C_EDGE_IS_POSITIVE = 1
	C_FAMILY = "spartan3e"
	C_FPU_EXCEPTION = 0
	C_FREQ = 50000000
	C_FSL_DATA_SIZE = 32
	C_FSL_EXCEPTION = 0
	C_FSL_LINKS = 0
	C_ICACHE_ALWAYS_USED = 0
	C_ICACHE_BASEADDR = "00000000000000000000000000000000"
	C_ICACHE_HIGHADDR = "00111111111111111111111111111111"
	C_ICACHE_INTERFACE = 0
	C_ICACHE_LINE_LEN = 4
	C_ICACHE_STREAMS = 0
	C_ICACHE_USE_FSL = 1
	C_ICACHE_VICTIMS = 0
	C_ILL_OPCODE_EXCEPTION = 0
	C_INSTANCE = "microblaze_0"
	C_INTERCONNECT = 1
	C_INTERRUPT_IS_EDGE = 0
	C_IPLB_BURST_EN = 0
	C_IPLB_BUS_EXCEPTION = 0
	C_IPLB_DWIDTH = 32
	C_IPLB_NATIVE_DWIDTH = 32
	C_IPLB_P2P = 0
	C_I_LMB = 1
	C_I_PLB = 1
	C_MMU_DTLB_SIZE = 4
	C_MMU_ITLB_SIZE = 2
	C_MMU_TLB_ACCESS = 3
	C_MMU_ZONES = 16
	C_NUMBER_OF_PC_BRK = 1
	C_NUMBER_OF_RD_ADDR_BRK = 0
	C_NUMBER_OF_WR_ADDR_BRK = 0
	C_OPCODE_0x0_ILLEGAL = 0
	C_OPTIMIZATION = 0
	C_PVR = 0
	C_PVR_USER1 = "00000000"
	C_PVR_USER2 = "00000000000000000000000000000000"
	C_RESET_MSR = "00000000000000000000000000000000"
	C_SCO = 0
	C_STREAM_INTERCONNECT = 0
	C_UNALIGNED_EXCEPTIONS = 0
	C_USE_BARREL = 0
	C_USE_BRANCH_TARGET_CACHE = 0
	C_USE_DCACHE = 0
	C_USE_DIV = 0
	C_USE_EXTENDED_FSL_INSTR = 0
	C_USE_EXT_BRK = 1
	C_USE_EXT_NM_BRK = 1
	C_USE_FPU = 0
	C_USE_HW_MUL = 1
	C_USE_ICACHE = 0
	C_USE_INTERRUPT = 1
	C_USE_MMU = 0
	C_USE_MSR_INSTR = 1
	C_USE_PCMP_INSTR = 1
    Set property "syn_keep = TRUE" for signal <alu_Op>.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/microblaze.vhd" line 3880: Unconnected output port 'Branch_Instr' of component 'Decode'.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/microblaze.vhd" line 4106: Unconnected output port 'Op2' of component 'Data_Flow'.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/microblaze.vhd" line 4344: Unconnected output port 'WB_DPLB_Data_Strobe' of component 'DPLB_Interface'.
INFO:Xst:2679 - Register <Trace_EX_PipeRun> in unit <microblaze> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Trace_MEM_PipeRun> in unit <microblaze> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Trace_MSR_Reg<0>> in unit <microblaze> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Trace_MSR_Reg<1>> in unit <microblaze> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Trace_MSR_Reg<2>> in unit <microblaze> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Trace_MSR_Reg<3>> in unit <microblaze> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <microblaze> analyzed. Unit <microblaze> generated.

Analyzing generic Entity <interrupt_mode_converter> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_EDGE_IS_POSITIVE = true
	C_INTERRUPT_IS_EDGE = false
Entity <interrupt_mode_converter> analyzed. Unit <interrupt_mode_converter> generated.

Analyzing generic Entity <Decode> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_ALLOW_DCACHE_WR = 1
	C_ALLOW_ICACHE_WR = 1
	C_ALLOW_LUT6 = true
	C_DATA_SIZE = 32
	C_DCACHE_USE_WRITEBACK = 0
	C_DEBUG_ENABLED = 1
	C_DETECT_DIV_OVERFLOW = 1
	C_DETECT_OPCODE_0x0 = false
	C_DIV_ZERO_EXCEPTION = 0
	C_DPLB_BUS_EXCEPTION = 0
	C_FPU_EXCEPTION = 0
	C_FSL_EXCEPTION = 0
	C_FSL_LINKS = 0
	C_ILL_OPCODE_EXCEPTION = 0
	C_IPLB_BUS_EXCEPTION = 0
	C_M_AXI_D_BUS_EXCEPTION = 0
	C_M_AXI_I_BUS_EXCEPTION = 0
	C_PVR = 0
	C_TARGET = "spartan3e"
	C_UNALIGNED_EXCEPTIONS = 0
	C_USE_BARREL = 0
	C_USE_DCACHE = 0
	C_USE_DIV = 0
	C_USE_EXTENDED_FSL_INSTR = 0
	C_USE_EXT_BRK = true
	C_USE_EXT_NM_BRK = true
	C_USE_FPU = 0
	C_USE_ICACHE = 0
	C_USE_INTERRUPT = true
	C_USE_LWX_SWX_EXCLUSIVE = false
	C_USE_LWX_SWX_INSTR = true
	C_USE_MSR_INSTR = 1
	C_USE_MUL64 = false
	C_USE_MUL_INSTR = true
	C_USE_PCMP_INSTR = true
    Set user-defined property "INIT =  F800" for instance <write_Reg_I_LUT> in unit <Decode>.
    Set user-defined property "INIT =  0040" for instance <Using_FPGA.of_PipeRun_Select_LUT4> in unit <Decode>.
    Set user-defined property "INIT =  0004" for instance <Using_FPGA.of_PipeRun_without_dready_LUT4> in unit <Decode>.
    Set user-defined property "INIT =  2000" for instance <Using_FPGA.OpSel1_SPR_Select_LUT_1> in unit <Decode>.
    Set user-defined property "INIT =  0200" for instance <Using_FPGA.OpSel1_SPR_Select_LUT_2> in unit <Decode>.
    Set user-defined property "INIT =  04" for instance <Using_FPGA.OpSel1_SPR_Select_LUT_3> in unit <Decode>.
    Set user-defined property "INIT =  15" for instance <Using_FPGA.OpSel1_SPR_Select_LUT_4> in unit <Decode>.
    Set user-defined property "INIT =  8421" for instance <Using_FPGA.Res_Forward1_LUT1> in unit <Decode>.
    Set user-defined property "INIT =  8421" for instance <Using_FPGA.Res_Forward1_LUT2> in unit <Decode>.
    Set user-defined property "INIT =  90" for instance <Using_FPGA.Res_Forward1_LUT3> in unit <Decode>.
    Set user-defined property "INIT =  8000" for instance <Using_FPGA.Res_Forward1_LUT4> in unit <Decode>.
    Set user-defined property "INIT =  8421" for instance <Using_FPGA.Res_Forward2_LUT1> in unit <Decode>.
    Set user-defined property "INIT =  8421" for instance <Using_FPGA.Res_Forward2_LUT2> in unit <Decode>.
    Set user-defined property "INIT =  90" for instance <Using_FPGA.Res_Forward2_LUT3> in unit <Decode>.
    Set user-defined property "INIT =  8000" for instance <Using_FPGA.Res_Forward2_LUT4> in unit <Decode>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.ALU_OP0_FDE> in unit <Decode>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.ALU_OP1_FDE> in unit <Decode>.
    Set user-defined property "INIT =  00F0" for instance <Using_FPGA.I_correct_Carry_Select> in unit <Decode>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.ALU_Carry_FDE> in unit <Decode>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.Force1_FDRE> in unit <Decode>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.Force2_FDRE> in unit <Decode>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.Force_Val1_FDRE> in unit <Decode>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.Force_Val2_FDRSE> in unit <Decode>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.Use_Reg_Neg_S_FDRE> in unit <Decode>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.Use_Reg_Neg_DI_FDRE> in unit <Decode>.
    Set user-defined property "INIT =  1" for instance <Using_FPGA.Reg_Test_Equal_FDSE> in unit <Decode>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.Reg_Test_Equal_N_FDRE> in unit <Decode>.
    Set user-defined property "INIT =  B4" for instance <Using_FPGA.force_jump1_LUT3> in unit <Decode>.
    Set user-defined property "INIT =  B4" for instance <Using_FPGA.force_di1_LUT3> in unit <Decode>.
    Set user-defined property "INIT =  0200" for instance <Using_FPGA.force_jump2_LUT4> in unit <Decode>.
    Set user-defined property "INIT =  AABA" for instance <Using_FPGA.force_di2_LUT4> in unit <Decode>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.Ext_NM_BRK_FDRSE> in unit <Decode>.
INFO:Xst:2679 - Register <Write_ICache_I> in unit <Decode> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Write_DCache_I> in unit <Decode> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <Take_Exc_2nd_cycle> in unit <Decode> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <Decode> analyzed. Unit <Decode> generated.

Analyzing generic Entity <PreFetch_Buffer> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_FSL_ATOMIC = 0
	C_IEXT_BUS_EXCEPTION = 0
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[0].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[1].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[2].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[3].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[4].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[5].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[6].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[7].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[8].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[9].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[10].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[11].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[12].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[13].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[14].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[15].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[16].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[17].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[18].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[19].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[20].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[21].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[22].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[23].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[24].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[25].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[26].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[27].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[28].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[29].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[30].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.PreFetch_Buffers[31].SRL16E_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  1" for instance <Using_FPGA.Buffer_DFFs[1].FDS_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  1" for instance <Using_FPGA.Buffer_DFFs[2].FDS_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  1" for instance <Using_FPGA.Buffer_DFFs[3].FDS_I> in unit <PreFetch_Buffer>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.of_valid_FDR_I> in unit <PreFetch_Buffer>.
Entity <PreFetch_Buffer> analyzed. Unit <PreFetch_Buffer> generated.

Analyzing generic Entity <Data_Flow> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_ADDR_TAG_BITS = 0
	C_ALLOW_DCACHE_WR = 1
	C_ALLOW_ICACHE_WR = 1
	C_ALLOW_LUT6 = true
	C_AREA_OPTIMIZED = 1
	C_BTC_SIZE = 0
	C_BUFFER_SIZE = 16
	C_CACHE_BYTE_SIZE = 8192
	C_DATA_SIZE = 32
	C_DCACHE_ADDR_TAG = 0
	C_DCACHE_ALWAYS_USED = 0
	C_DCACHE_BASEADDR = "00000000000000000000000000000000"
	C_DCACHE_BYTE_SIZE = 8192
	C_DCACHE_HIGHADDR = "00111111111111111111111111111111"
	C_DCACHE_INTERFACE = 0
	C_DCACHE_LINE_LEN = 4
	C_DCACHE_USE_FSL = 1
	C_DCACHE_USE_WRITEBACK = 0
	C_DCACHE_VICTIMS = 0
	C_DEBUG_ENABLED = 1
	C_DETECT_DIV_OVERFLOW = 1
	C_DIV_ZERO_EXCEPTION = 0
	C_DPLB_BUS_EXCEPTION = 0
	C_D_AXI = 0
	C_D_LMB = 1
	C_D_PLB = 1
	C_EDGE_IS_POSITIVE = 1
	C_EXCEPTION_ADDR = "00000020"
	C_EXT_BRK_ADDR = "00000018"
	C_FPU_EXCEPTION = 0
	C_FSL_EXCEPTION = 0
	C_FSL_LINKS = 0
	C_ICACHE_ALWAYS_USED = 0
	C_ICACHE_BASEADDR = "00000000000000000000000000000000"
	C_ICACHE_HIGHADDR = "00111111111111111111111111111111"
	C_ICACHE_INTERFACE = 0
	C_ICACHE_LINE_LEN = 4
	C_ICACHE_STREAMS = 0
	C_ICACHE_USE_FSL = 1
	C_ICACHE_VICTIMS = 0
	C_ILL_OPCODE_EXCEPTION = 0
	C_INTERCONNECT = 1
	C_INTERRUPT_ADDR = "00000010"
	C_INTERRUPT_IS_EDGE = 0
	C_IPLB_BUS_EXCEPTION = 0
	C_I_AXI = 0
	C_I_LMB = 1
	C_I_PLB = 1
	C_MAX_FSL_LINKS = 16
	C_MB_VERSION = "00010001"
	C_MMU_DTLB_SIZE = 4
	C_MMU_ITLB_SIZE = 2
	C_MMU_TLB_ACCESS = 3
	C_MMU_ZONES = 16
	C_M_AXI_D_BUS_EXCEPTION = 0
	C_M_AXI_I_BUS_EXCEPTION = 0
	C_NUMBER_OF_PC_BRK = 1
	C_NUMBER_OF_RD_ADDR_BRK = 0
	C_NUMBER_OF_WR_ADDR_BRK = 0
	C_OPCODE_0x0_ILLEGAL = 0
	C_PC_START_ADDR = "00000000"
	C_PVR = 0
	C_PVR_USER1 = "00000000"
	C_PVR_USER2 = "00000000000000000000000000000000"
	C_RESET_MSR = "000000000000000"
	C_STREAM_INTERCONNECT = 0
	C_TARGET = "spartan3e"
	C_UNALIGNED_EXCEPTIONS = 0
	C_USE_BARREL = 0
	C_USE_BTC = false
	C_USE_DCACHE = 0
	C_USE_DIV = 0
	C_USE_EXCEPTIONS = false
	C_USE_EXTENDED_FSL_INSTR = 0
	C_USE_FPU = 0
	C_USE_HW_MUL = true
	C_USE_ICACHE = 0
	C_USE_MMU = 0
	C_USE_MSR_INSTR = 1
	C_USE_MUL64 = false
	C_USE_PCMP_INSTR = true
    Set property "syn_keep = TRUE" for signal <op2_i>.
Entity <Data_Flow> analyzed. Unit <Data_Flow> generated.

Analyzing generic Entity <Register_File> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DATA_SIZE = 32
	C_TARGET = "spartan3e"
Entity <Register_File> analyzed. Unit <Register_File> generated.

Analyzing generic Entity <Register_File_Bit> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  0000" for instance <Using_LUT4.RAM16x1D_Reg1_Low> in unit <Register_File_Bit>.
    Set user-defined property "INIT =  0000" for instance <Using_LUT4.RAM16x1D_Reg1_High> in unit <Register_File_Bit>.
    Set user-defined property "INIT =  CA" for instance <Using_LUT4.Data_Write_Mux> in unit <Register_File_Bit>.
    Set user-defined property "INIT =  CA" for instance <Using_LUT4.Reg1_Mux> in unit <Register_File_Bit>.
    Set user-defined property "INIT =  0000" for instance <Using_LUT4.RAM16x1D_Reg2_Low> in unit <Register_File_Bit>.
    Set user-defined property "INIT =  0000" for instance <Using_LUT4.RAM16x1D_Reg2_High> in unit <Register_File_Bit>.
    Set user-defined property "INIT =  CA" for instance <Using_LUT4.Reg2_Mux> in unit <Register_File_Bit>.
Entity <Register_File_Bit> analyzed. Unit <Register_File_Bit> generated.

Analyzing generic Entity <Operand_Select> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DATA_SIZE = 32
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR = "00000020"
	C_EXT_BRK_ADDR = "00000018"
	C_FSL_EXCEPTION = false
	C_INTERRUPT_ADDR = "00000010"
	C_PVR = 0
	C_TARGET = "spartan3e"
	C_USE_EXCEPTIONS = false
	C_USE_FPU_bool = false
Entity <Operand_Select> analyzed. Unit <Operand_Select> generated.

Analyzing generic Entity <Operand_Select_Bit.1> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = true
	C_ONLY_PC = false
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  CA" for instance <Op1_Mux2_1> in unit <Operand_Select_Bit.1>.
    Set user-defined property "INIT =  CAC0" for instance <Both_PC_and_MSR.Op1_Mux2_2> in unit <Operand_Select_Bit.1>.
    Set user-defined property "INIT =  0" for instance <Op1_DFF> in unit <Operand_Select_Bit.1>.
    Set user-defined property "INIT =  0" for instance <Op1_Reg_DFF> in unit <Operand_Select_Bit.1>.
    Set user-defined property "INIT =  00CA" for instance <Intr_Addr_bit_is_0.Op2_Mux2_1> in unit <Operand_Select_Bit.1>.
    Set user-defined property "INIT =  10" for instance <Lower_Part.Op2_Mux2_2> in unit <Operand_Select_Bit.1>.
    Set user-defined property "INIT =  0" for instance <LSB_DFF.Op2_DFF> in unit <Operand_Select_Bit.1>.
Entity <Operand_Select_Bit.1> analyzed. Unit <Operand_Select_Bit.1> generated.

Analyzing generic Entity <Operand_Select_Bit.2> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = false
	C_ONLY_PC = false
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  CA" for instance <Op1_Mux2_1> in unit <Operand_Select_Bit.2>.
    Set user-defined property "INIT =  CAC0" for instance <Both_PC_and_MSR.Op1_Mux2_2> in unit <Operand_Select_Bit.2>.
    Set user-defined property "INIT =  0" for instance <Op1_DFF> in unit <Operand_Select_Bit.2>.
    Set user-defined property "INIT =  0" for instance <Op1_Reg_DFF> in unit <Operand_Select_Bit.2>.
    Set user-defined property "INIT =  00CA" for instance <Intr_Addr_bit_is_0.Op2_Mux2_1> in unit <Operand_Select_Bit.2>.
    Set user-defined property "INIT =  10" for instance <Lower_Part.Op2_Mux2_2> in unit <Operand_Select_Bit.2>.
    Set user-defined property "INIT =  0" for instance <MSB_DFF.Op2_DFF> in unit <Operand_Select_Bit.2>.
Entity <Operand_Select_Bit.2> analyzed. Unit <Operand_Select_Bit.2> generated.

Analyzing generic Entity <Operand_Select_Bit.3> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '1'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = false
	C_ONLY_PC = false
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  CA" for instance <Op1_Mux2_1> in unit <Operand_Select_Bit.3>.
    Set user-defined property "INIT =  CAC0" for instance <Both_PC_and_MSR.Op1_Mux2_2> in unit <Operand_Select_Bit.3>.
    Set user-defined property "INIT =  0" for instance <Op1_DFF> in unit <Operand_Select_Bit.3>.
    Set user-defined property "INIT =  0" for instance <Op1_Reg_DFF> in unit <Operand_Select_Bit.3>.
    Set user-defined property "INIT =  00CA" for instance <Intr_Addr_bit_is_0.Op2_Mux2_1> in unit <Operand_Select_Bit.3>.
    Set user-defined property "INIT =  54" for instance <Lower_Part.Op2_Mux2_2> in unit <Operand_Select_Bit.3>.
    Set user-defined property "INIT =  0" for instance <MSB_DFF.Op2_DFF> in unit <Operand_Select_Bit.3>.
Entity <Operand_Select_Bit.3> analyzed. Unit <Operand_Select_Bit.3> generated.

Analyzing generic Entity <Operand_Select_Bit.4> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '1'
	C_INTERRUPT_ADDR_BIT = '1'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = false
	C_ONLY_PC = false
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  CA" for instance <Op1_Mux2_1> in unit <Operand_Select_Bit.4>.
    Set user-defined property "INIT =  CAC0" for instance <Both_PC_and_MSR.Op1_Mux2_2> in unit <Operand_Select_Bit.4>.
    Set user-defined property "INIT =  0" for instance <Op1_DFF> in unit <Operand_Select_Bit.4>.
    Set user-defined property "INIT =  0" for instance <Op1_Reg_DFF> in unit <Operand_Select_Bit.4>.
    Set user-defined property "INIT =  FFCA" for instance <Intr_Addr_bit_is_1.Op2_Mux2_1> in unit <Operand_Select_Bit.4>.
    Set user-defined property "INIT =  54" for instance <Lower_Part.Op2_Mux2_2> in unit <Operand_Select_Bit.4>.
    Set user-defined property "INIT =  0" for instance <MSB_DFF.Op2_DFF> in unit <Operand_Select_Bit.4>.
Entity <Operand_Select_Bit.4> analyzed. Unit <Operand_Select_Bit.4> generated.

Analyzing generic Entity <Operand_Select_Bit.5> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '1'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = false
	C_ONLY_PC = false
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  CA" for instance <Op1_Mux2_1> in unit <Operand_Select_Bit.5>.
    Set user-defined property "INIT =  CAC0" for instance <Both_PC_and_MSR.Op1_Mux2_2> in unit <Operand_Select_Bit.5>.
    Set user-defined property "INIT =  0" for instance <Op1_DFF> in unit <Operand_Select_Bit.5>.
    Set user-defined property "INIT =  0" for instance <Op1_Reg_DFF> in unit <Operand_Select_Bit.5>.
    Set user-defined property "INIT =  00CA" for instance <Intr_Addr_bit_is_0.Op2_Mux2_1> in unit <Operand_Select_Bit.5>.
    Set user-defined property "INIT =  BA" for instance <Lower_Part.Op2_Mux2_2> in unit <Operand_Select_Bit.5>.
    Set user-defined property "INIT =  0" for instance <MSB_DFF.Op2_DFF> in unit <Operand_Select_Bit.5>.
Entity <Operand_Select_Bit.5> analyzed. Unit <Operand_Select_Bit.5> generated.

Analyzing generic Entity <Operand_Select_Bit.6> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = true
	C_LSB_BIT = false
	C_ONLY_PC = true
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  CA" for instance <Op1_Mux2_1> in unit <Operand_Select_Bit.6>.
    Set user-defined property "INIT =  8" for instance <Only_PC.Op1_Mux2_2> in unit <Operand_Select_Bit.6>.
    Set user-defined property "INIT =  0" for instance <Op1_DFF> in unit <Operand_Select_Bit.6>.
    Set user-defined property "INIT =  0" for instance <Op1_Reg_DFF> in unit <Operand_Select_Bit.6>.
    Set user-defined property "INIT =  00CA" for instance <Intr_Addr_bit_is_0.Op2_Mux2_1> in unit <Operand_Select_Bit.6>.
    Set user-defined property "INIT =  10" for instance <Lower_Part.Op2_Mux2_2> in unit <Operand_Select_Bit.6>.
    Set user-defined property "INIT =  0" for instance <MSB_DFF.Op2_DFF> in unit <Operand_Select_Bit.6>.
Entity <Operand_Select_Bit.6> analyzed. Unit <Operand_Select_Bit.6> generated.

Analyzing generic Entity <Operand_Select_Bit.7> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = false
	C_LSB_BIT = false
	C_ONLY_PC = true
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  CA" for instance <Op1_Mux2_1> in unit <Operand_Select_Bit.7>.
    Set user-defined property "INIT =  8" for instance <Only_PC.Op1_Mux2_2> in unit <Operand_Select_Bit.7>.
    Set user-defined property "INIT =  0" for instance <Op1_DFF> in unit <Operand_Select_Bit.7>.
    Set user-defined property "INIT =  0" for instance <Op1_Reg_DFF> in unit <Operand_Select_Bit.7>.
    Set user-defined property "INIT =  00CA" for instance <Intr_Addr_bit_is_0.Op2_Mux2_1> in unit <Operand_Select_Bit.7>.
    Set user-defined property "INIT =  00CA" for instance <Upper_Part.Exc_Addr_Bit_Is_0.Op2_Mux2_2> in unit <Operand_Select_Bit.7>.
    Set user-defined property "INIT =  0" for instance <MSB_DFF.Op2_DFF> in unit <Operand_Select_Bit.7>.
Entity <Operand_Select_Bit.7> analyzed. Unit <Operand_Select_Bit.7> generated.

Analyzing generic Entity <Operand_Select_Bit.8> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DEBUG_ENABLED = 1
	C_EXCEPTION_ADDR_BIT = '0'
	C_EXT_BRK_ADDR_BIT = '0'
	C_INTERRUPT_ADDR_BIT = '0'
	C_LOWER_HALFWORD = false
	C_LSB_BIT = false
	C_ONLY_PC = false
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  CA" for instance <Op1_Mux2_1> in unit <Operand_Select_Bit.8>.
    Set user-defined property "INIT =  CAC0" for instance <Both_PC_and_MSR.Op1_Mux2_2> in unit <Operand_Select_Bit.8>.
    Set user-defined property "INIT =  0" for instance <Op1_DFF> in unit <Operand_Select_Bit.8>.
    Set user-defined property "INIT =  0" for instance <Op1_Reg_DFF> in unit <Operand_Select_Bit.8>.
    Set user-defined property "INIT =  00CA" for instance <Intr_Addr_bit_is_0.Op2_Mux2_1> in unit <Operand_Select_Bit.8>.
    Set user-defined property "INIT =  00CA" for instance <Upper_Part.Exc_Addr_Bit_Is_0.Op2_Mux2_2> in unit <Operand_Select_Bit.8>.
    Set user-defined property "INIT =  0" for instance <MSB_DFF.Op2_DFF> in unit <Operand_Select_Bit.8>.
Entity <Operand_Select_Bit.8> analyzed. Unit <Operand_Select_Bit.8> generated.

Analyzing generic Entity <ALU> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_ALLOW_LUT6 = true
	C_AREA_OPTIMIZED = 1
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  00" for instance <FPGA_Target.No_Carry_Decoding.alu_carry_select_LUT> in unit <ALU>.
Entity <ALU> analyzed. Unit <ALU> generated.

Analyzing generic Entity <ALU_Bit.1> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_ALLOW_LUT6 = true
	C_LAST_BIT = false
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  A678" for instance <Using_FPGA_LUT4.Not_Last_Bit.I_ALU_LUT> in unit <ALU_Bit.1>.
Entity <ALU_Bit.1> analyzed. Unit <ALU_Bit.1> generated.

Analyzing generic Entity <ALU_Bit.2> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_ALLOW_LUT6 = true
	C_LAST_BIT = true
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  A678" for instance <Using_FPGA_LUT4.Last_Bit.I_ALU_LUT_1> in unit <ALU_Bit.2>.
    Set user-defined property "INIT =  FA0A" for instance <Using_FPGA_LUT4.Last_Bit.I_ALU_LUT_2> in unit <ALU_Bit.2>.
Entity <ALU_Bit.2> analyzed. Unit <ALU_Bit.2> generated.

Analyzing generic Entity <Shift_Logic_Module> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DATA_SIZE = 32
	C_TARGET = "spartan3e"
	C_USE_PCMP_INSTR = true
    Set user-defined property "INIT =  0002" for instance <Use_PCMP_instr.Using_FPGA.pcmp_00_lut_0> in unit <Shift_Logic_Module>.
    Set user-defined property "INIT =  00FC" for instance <Use_PCMP_instr.Using_FPGA.pcmp_00_lut_1> in unit <Shift_Logic_Module>.
    Set user-defined property "INIT =  FF0C" for instance <Use_PCMP_instr.Using_FPGA.pcmp_00_lut_2> in unit <Shift_Logic_Module>.
    Set user-defined property "INIT =  8000" for instance <Use_PCMP_instr.Using_FPGA.pcmp_10_lut> in unit <Shift_Logic_Module>.
    Set user-defined property "INIT =  7FFF" for instance <Use_PCMP_instr.Using_FPGA.pcmp_11_lut> in unit <Shift_Logic_Module>.
    Set user-defined property "INIT =  E" for instance <Use_PCMP_instr.Using_FPGA.shift_logic_result_i_lut_0> in unit <Shift_Logic_Module>.
    Set user-defined property "INIT =  E" for instance <Use_PCMP_instr.Using_FPGA.shift_logic_result_i_lut_1> in unit <Shift_Logic_Module>.
    Set user-defined property "INIT =  F0EE" for instance <Use_PCMP_instr.Using_FPGA.shift_logic_result_i_lut_2> in unit <Shift_Logic_Module>.
Entity <Shift_Logic_Module> analyzed. Unit <Shift_Logic_Module> generated.

Analyzing generic Entity <Shift_Logic_Bit> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  468E" for instance <Logic_LUT> in unit <Shift_Logic_Bit>.
    Set user-defined property "INIT =  FCAA" for instance <Shift_LUT> in unit <Shift_Logic_Bit>.
Entity <Shift_Logic_Bit> analyzed. Unit <Shift_Logic_Bit> generated.

Analyzing generic Entity <carry_equal> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_TARGET = "spartan3e"
	Size = 8
Entity <carry_equal> analyzed. Unit <carry_equal> generated.

Analyzing generic Entity <mul_unit> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_TARGET = "spartan3e"
	C_USE_HW_MUL = true
	C_USE_MUL64 = false
Entity <mul_unit> analyzed. Unit <mul_unit> generated.

Analyzing generic Entity <Result_Mux> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DATA_SIZE = 32
	C_TARGET = "spartan3e"
Entity <Result_Mux> analyzed. Unit <Result_Mux> generated.

Analyzing generic Entity <Result_Mux_Bit> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  EFE0" for instance <Mul_ALU_Mux> in unit <Result_Mux_Bit>.
    Set user-defined property "INIT =  E040" for instance <Data_Shift_Mux> in unit <Result_Mux_Bit>.
    Set user-defined property "INIT =  0" for instance <EX_Result_DFF> in unit <Result_Mux_Bit>.
Entity <Result_Mux_Bit> analyzed. Unit <Result_Mux_Bit> generated.

Analyzing generic Entity <Zero_Detect> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DATA_SIZE = 32
	C_TARGET = "spartan3e"
Entity <Zero_Detect> analyzed. Unit <Zero_Detect> generated.

Analyzing generic Entity <MSR_Reg> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DATA_SIZE = 32
	C_FSL_LINKS = 0
	C_PVR = 0
	C_RESET_MSR = "000000000000000"
	C_TARGET = "spartan3e"
	C_USE_DCACHE = false
	C_USE_DIV = false
	C_USE_EXCEPTIONS = false
	C_USE_ICACHE = false
	C_USE_MSR_INSTR = 1
Entity <MSR_Reg> analyzed. Unit <MSR_Reg> generated.

Analyzing generic Entity <MSR_Reg_Bit> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  0" for instance <MSR_I> in unit <MSR_Reg_Bit>.
Entity <MSR_Reg_Bit> analyzed. Unit <MSR_Reg_Bit> generated.

Analyzing generic Entity <PC_Module> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DATA_SIZE = 32
	C_PC_START_ADDR = "00000000"
	C_TARGET = "spartan3e"
    Set property "MAX_FANOUT = 1000" for signal <normal_piperun>.
    Set user-defined property "USELOWSKEWLINES =  yes" for signal <pc_write_I>.
    Set property "MAX_FANOUT = 1000" for signal <pc_write_I>.
Entity <PC_Module> analyzed. Unit <PC_Module> generated.

Analyzing generic Entity <PC_Bit.1> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_RESET_VALUE = '0'
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  F066" for instance <SUM_I> in unit <PC_Bit.1>.
    Set user-defined property "INIT =  AACA" for instance <NewPC_Mux> in unit <PC_Bit.1>.
    Set user-defined property "INIT =  0" for instance <Reset_DFF.PC_IF_DFF> in unit <PC_Bit.1>.
    Set user-defined property "INIT =  0000" for instance <PC_OF_Buffer> in unit <PC_Bit.1>.
    Set user-defined property "INIT =  0" for instance <PC_EX_DFF> in unit <PC_Bit.1>.
Entity <PC_Bit.1> analyzed. Unit <PC_Bit.1> generated.

Analyzing generic Entity <PC_Bit.2> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_RESET_VALUE = '1'
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  F066" for instance <SUM_I> in unit <PC_Bit.2>.
    Set user-defined property "INIT =  AACA" for instance <NewPC_Mux> in unit <PC_Bit.2>.
    Set user-defined property "INIT =  1" for instance <Set_DFF.PC_IF_DFF> in unit <PC_Bit.2>.
    Set user-defined property "INIT =  0000" for instance <PC_OF_Buffer> in unit <PC_Bit.2>.
    Set user-defined property "INIT =  0" for instance <PC_EX_DFF> in unit <PC_Bit.2>.
Entity <PC_Bit.2> analyzed. Unit <PC_Bit.2> generated.

Analyzing generic Entity <PVR> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_ADDR_TAG_BITS = 0
	C_ALLOW_DCACHE_WR = 1
	C_ALLOW_ICACHE_WR = 1
	C_AREA_OPTIMIZED = true
	C_BTC_SIZE = 0
	C_CACHE_BYTE_SIZE = 8192
	C_DCACHE_ADDR_TAG = 0
	C_DCACHE_ALWAYS_USED = 0
	C_DCACHE_BASEADDR = "00000000000000000000000000000000"
	C_DCACHE_BYTE_SIZE = 8192
	C_DCACHE_HIGHADDR = "00111111111111111111111111111111"
	C_DCACHE_INTERFACE = 0
	C_DCACHE_LINE_LEN = 4
	C_DCACHE_USE_FSL = 1
	C_DCACHE_USE_WRITEBACK = 0
	C_DCACHE_VICTIMS = 0
	C_DEBUG_ENABLED = 1
	C_DIV_ZERO_EXCEPTION = 0
	C_DPLB_BUS_EXCEPTION = 0
	C_D_AXI = 0
	C_D_LMB = 1
	C_D_PLB = 1
	C_EDGE_IS_POSITIVE = 1
	C_FPU_EXCEPTION = 0
	C_FSL_EXCEPTION = 0
	C_FSL_LINKS = 0
	C_ICACHE_ALWAYS_USED = 0
	C_ICACHE_BASEADDR = "00000000000000000000000000000000"
	C_ICACHE_HIGHADDR = "00111111111111111111111111111111"
	C_ICACHE_INTERFACE = 0
	C_ICACHE_LINE_LEN = 4
	C_ICACHE_STREAMS = 0
	C_ICACHE_USE_FSL = 1
	C_ICACHE_VICTIMS = 0
	C_ILL_OPCODE_EXCEPTION = 0
	C_INTERCONNECT = 1
	C_INTERRUPT_IS_EDGE = 0
	C_IPLB_BUS_EXCEPTION = 0
	C_I_AXI = 0
	C_I_LMB = 1
	C_I_PLB = 1
	C_MB_VERSION = "00010001"
	C_MMU_DTLB_SIZE = 4
	C_MMU_ITLB_SIZE = 2
	C_MMU_TLB_ACCESS = 3
	C_MMU_ZONES = 16
	C_M_AXI_D_BUS_EXCEPTION = 0
	C_M_AXI_I_BUS_EXCEPTION = 0
	C_NUMBER_OF_PC_BRK = 1
	C_NUMBER_OF_RD_ADDR_BRK = 0
	C_NUMBER_OF_WR_ADDR_BRK = 0
	C_OPCODE_0x0_ILLEGAL = 0
	C_PVR = 0
	C_PVR_USER1 = "00000000"
	C_PVR_USER2 = "00000000000000000000000000000000"
	C_RESET_MSR = "000000000000000"
	C_STREAM_INTERCONNECT = 0
	C_TARGET = "spartan3e"
	C_UNALIGNED_EXCEPTIONS = 0
	C_USE_BARREL = false
	C_USE_BTC = false
	C_USE_DCACHE = 0
	C_USE_DIV = false
	C_USE_EXTENDED_FSL_INSTR = 0
	C_USE_FPU = 0
	C_USE_HW_MUL = true
	C_USE_ICACHE = 0
	C_USE_MMU = 0
	C_USE_MSR_INSTR = true
	C_USE_MUL64 = false
	C_USE_PCMP_INSTR = true
Entity <PVR> analyzed. Unit <PVR> generated.

Analyzing generic Entity <Byte_Doublet_Handle> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_ALLOW_LUT6 = true
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  8A8F" for instance <Using_FPGA.FPGA_LUT4_Target_BE.BYTE_0_I> in unit <Byte_Doublet_Handle>.
    Set user-defined property "INIT =  0BAB" for instance <Using_FPGA.FPGA_LUT4_Target_BE.BYTE_1_I> in unit <Byte_Doublet_Handle>.
    Set user-defined property "INIT =  454F" for instance <Using_FPGA.FPGA_LUT4_Target_BE.BYTE_2_I> in unit <Byte_Doublet_Handle>.
    Set user-defined property "INIT =  151F" for instance <Using_FPGA.FPGA_LUT4_Target_BE.BYTE_3_I> in unit <Byte_Doublet_Handle>.
    Set user-defined property "INIT =  AB" for instance <Using_FPGA.Use_Dynamic_Bus_Sizing.FPGA_LUT4_Target_ReadSel.READ_SEL_LEFT_I> in unit <Byte_Doublet_Handle>.
    Set user-defined property "INIT =  B" for instance <Using_FPGA.Use_Dynamic_Bus_Sizing.FPGA_LUT4_Target_ReadSel.READ_SEL_RIGHT_I> in unit <Byte_Doublet_Handle>.
    Set user-defined property "INIT =  E" for instance <Using_FPGA.Use_Dynamic_Bus_Sizing.FPGA_LUT4_Target_WriteSel.WRITE_MSB_SEL_LEFT_I> in unit <Byte_Doublet_Handle>.
    Set user-defined property "INIT =  A8" for instance <Using_FPGA.FPGA_LUT4_Target_ADDR.LOW_ADDR_OUT_LEFT_I> in unit <Byte_Doublet_Handle>.
    Set user-defined property "INIT =  8" for instance <Using_FPGA.FPGA_LUT4_Target_ADDR.LOW_ADDR_OUT_RIGHT_I> in unit <Byte_Doublet_Handle>.
Entity <Byte_Doublet_Handle> analyzed. Unit <Byte_Doublet_Handle> generated.

Analyzing generic Entity <Data_Read_Steering> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_ALLOW_LUT6 = true
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[0].LUT30_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[0].LUT31_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[1].LUT30_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[1].LUT31_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[2].LUT30_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[2].LUT31_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[3].LUT30_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[3].LUT31_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[4].LUT30_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[4].LUT31_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[5].LUT30_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[5].LUT31_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[6].LUT30_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[6].LUT31_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[7].LUT30_I> in unit <Data_Read_Steering>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_LOOP[7].LUT31_I> in unit <Data_Read_Steering>.
Entity <Data_Read_Steering> analyzed. Unit <Data_Read_Steering> generated.

Analyzing generic Entity <mux4_8> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_ALLOW_LUT6 = true
	C_BE = true
	C_TARGET = "spartan3e"
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[0].LUT30_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[0].LUT31_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[1].LUT30_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[1].LUT31_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[2].LUT30_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[2].LUT31_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[3].LUT30_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[3].LUT31_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[4].LUT30_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[4].LUT31_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[5].LUT30_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[5].LUT31_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[6].LUT30_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[6].LUT31_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[7].LUT30_I> in unit <mux4_8>.
    Set user-defined property "INIT =  CA" for instance <FPGA_LUT4_Target.GEN_4.GEN4_LOOP[7].LUT31_I> in unit <mux4_8>.
Entity <mux4_8> analyzed. Unit <mux4_8> generated.

Analyzing generic Entity <DPLB_Interface> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DELAYED_DATA_STROBE = false
	C_DPLB_WIDTH = 32
	C_OUTPUT_DFFS = true
Entity <DPLB_Interface> analyzed. Unit <DPLB_Interface> generated.

Analyzing generic Entity <IPLB_Interface> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_IPLB_DWIDTH = 32
Entity <IPLB_Interface> analyzed. Unit <IPLB_Interface> generated.

Analyzing generic Entity <Debug> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_DATA_SIZE = 32
	C_DCACHE_BASEADDR = "00000000000000000000000000000000"
	C_DCACHE_HIGHADDR = "00111111111111111111111111111111"
	C_DCACHE_USE_FSL = 1
	C_DCACHE_USE_WRITEBACK = 0
	C_DIV_ZERO_EXCEPTION = 0
	C_DPLB_BUS_EXCEPTION = 0
	C_FPU_EXCEPTION = 0
	C_FSL_EXCEPTION = 0
	C_FSL_LINKS = 0
	C_ICACHE_BASEADDR = "00000000000000000000000000000000"
	C_ICACHE_HIGHADDR = "00111111111111111111111111111111"
	C_ICACHE_USE_FSL = 1
	C_ILL_OPCODE_EXCEPTION = 0
	C_INTERCONNECT = 1
	C_IPLB_BUS_EXCEPTION = 0
	C_MB_VERSION = "00010001"
	C_M_AXI_D_BUS_EXCEPTION = 0
	C_M_AXI_I_BUS_EXCEPTION = 0
	C_NUMBER_OF_PC_BRK = 1
	C_NUMBER_OF_RD_ADDR_BRK = 0
	C_NUMBER_OF_WR_ADDR_BRK = 0
	C_PVR = 0
	C_PVR_USER1 = "00000000"
	C_PVR_USER2 = "00000000000000000000000000000000"
	C_STREAM_INTERCONNECT = 0
	C_TARGET = "spartan3e"
	C_UNALIGNED_EXCEPTIONS = 0
	C_USE_BARREL = 0
	C_USE_DCACHE = 0
	C_USE_DIV = 0
	C_USE_EXTENDED_FSL_INSTR = 0
	C_USE_FPU = 0
	C_USE_HW_MUL = 1
	C_USE_ICACHE = 0
	C_USE_MSR_INSTR = 1
	C_USE_PCMP_INSTR = 1
    Set user-defined property "INIT =  001D" for instance <Use_SRL16.SRL16E_1> in unit <Debug>.
    Set user-defined property "INIT =  021E" for instance <Use_SRL16.SRL16E_2> in unit <Debug>.
    Set user-defined property "INIT =  FFFF" for instance <Use_SRL16.The_Cache_Addresses[1].SRL16E_Cache_I> in unit <Debug>.
    Set user-defined property "INIT =  3FFF" for instance <Use_SRL16.The_Cache_Addresses[2].SRL16E_Cache_I> in unit <Debug>.
    Set user-defined property "INIT =  0000" for instance <Use_SRL16.The_Cache_Addresses[3].SRL16E_Cache_I> in unit <Debug>.
    Set user-defined property "INIT =  0000" for instance <Use_SRL16.The_Cache_Addresses[4].SRL16E_Cache_I> in unit <Debug>.
    Set user-defined property "INIT =  FFFF" for instance <Use_SRL16.The_Cache_Addresses[5].SRL16E_Cache_I> in unit <Debug>.
    Set user-defined property "INIT =  3FFF" for instance <Use_SRL16.The_Cache_Addresses[6].SRL16E_Cache_I> in unit <Debug>.
    Set user-defined property "INIT =  0000" for instance <Use_SRL16.The_Cache_Addresses[7].SRL16E_Cache_I> in unit <Debug>.
    Set user-defined property "INIT =  0000" for instance <Use_SRL16.The_Cache_Addresses[8].SRL16E_Cache_I> in unit <Debug>.
    Set user-defined property "INIT =  1800" for instance <Use_SRL16.SRL16E_3> in unit <Debug>.
    Set user-defined property "INIT =  1100" for instance <Use_SRL16.SRL16E_4> in unit <Debug>.
WARNING:Xst:790 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/debug.vhd" line 760: Index value(s) does not match array range, simulation mismatch.
INFO:Xst:1433 - Contents of array <status_reg> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/debug.vhd" line 1068: Index value(s) does not match array range, simulation mismatch.
INFO:Xst:1433 - Contents of array <data_read_reg> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
WARNING:Xst:821 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/debug.vhd" line 1357: Loop body will iterate zero times
    Set user-defined property "INIT =  0" for instance <Using_FPGA.Stop_CPU_FDRSE> in unit <Debug>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.Dbg_Inhibit_EX_FDRSE> in unit <Debug>.
    Set user-defined property "INIT =  0" for instance <Using_FPGA.Stop_Instr_Fetch_FDRSE> in unit <Debug>.
INFO:Xst:2679 - Register <watchpoint_hit_hold> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<1>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<2>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<3>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<4>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<5>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<6>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<7>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<8>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<9>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<10>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<11>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<12>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<13>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<14>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <pc_hit<15>> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <Debug> analyzed. Unit <Debug> generated.

Analyzing generic Entity <address_hit> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_FIRST = true
	C_TARGET = "spartan3e"
	No_Bits = 32
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.Compare[7].SRLC16E_I> in unit <address_hit>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.Compare[6].SRLC16E_I> in unit <address_hit>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.Compare[5].SRLC16E_I> in unit <address_hit>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.Compare[4].SRLC16E_I> in unit <address_hit>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.Compare[3].SRLC16E_I> in unit <address_hit>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.Compare[2].SRLC16E_I> in unit <address_hit>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.Compare[1].SRLC16E_I> in unit <address_hit>.
    Set user-defined property "INIT =  0000" for instance <Using_FPGA.Compare[0].SRLC16E_I> in unit <address_hit>.
Entity <address_hit> analyzed. Unit <address_hit> generated.

Analyzing generic Entity <instr_mux> in library <Microblaze_v7_30_b> (Architecture <IMP>).
	C_ALLOW_LUT6 = true
	C_DEBUG_ENABLED = true
	C_TARGET = "spartan3e"
	C_USE_ICACHE = false
	C_USE_I_EXT = true
	C_USE_I_LMB = true
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd" line 248: Instantiating black box module <MUXF5>.
Entity <instr_mux> analyzed. Unit <instr_mux> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...
INFO:Xst:2679 - Register <fsl_stalled_1> in unit <Debug> has a constant value of 0 during circuit operation. The register is replaced by logic.

Synthesizing Unit <interrupt_mode_converter>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/interrupt_mode_converter.vhd".
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_taken> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <interrupt_mode_converter> synthesized.


Synthesizing Unit <DPLB_Interface>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/dplb_interface.vhd".
WARNING:Xst:647 - Input <DPLB_MWrBTerm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DPLB_MRearbitrate> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DPLB_MBusy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DPLB_MRdBTerm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DPLB_MRdWdAddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MEM_DataBus_Write> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DPLB_MSSize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MEM_DataBus_Enable_BusLock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DPLB_MIRQ> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <active_access_d2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <MEM_DPLB_Exception>.
    Found 32-bit register for signal <DPLB_M_ABus>.
    Found 1-bit register for signal <DPLB_M_request>.
    Found 1-bit register for signal <DPLB_M_RNW>.
    Found 1-bit register for signal <WB_DPLB_Data_Strobe>.
    Found 32-bit register for signal <WB_DPLB_Read_Data>.
    Found 1-bit register for signal <active_access>.
    Found 1-bit register for signal <active_access_d1>.
    Found 4-bit register for signal <dplb_m_be_i>.
    Found 32-bit register for signal <dplb_m_wrdbus_i>.
    Found 1-bit register for signal <mem_access_completed>.
    Summary:
	inferred 107 D-type flip-flop(s).
Unit <DPLB_Interface> synthesized.


Synthesizing Unit <IPLB_Interface>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/iplb_interface.vhd".
WARNING:Xst:647 - Input <IPLB_MWrBTerm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IPLB_MBusy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IPLB_MSSize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IPLB_MRdBTerm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_Fetch> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IPLB_MRdWdAddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IPLB_MRearbitrate> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IPLB_MIRQ> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <IPLB_Exception>.
    Found 1-bit register for signal <IPLB_M_request>.
    Found 32-bit register for signal <IPLB_Data>.
    Found 1-bit register for signal <ib_addr_strobe_d1>.
    Found 32-bit register for signal <instr_addr>.
    Found 1-bit register for signal <mem_access_completed>.
    Summary:
	inferred  68 D-type flip-flop(s).
Unit <IPLB_Interface> synthesized.


Synthesizing Unit <PVR>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/pvr.vhd".
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MEM_Sel_SPR_PVR<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MEM_PipeRun<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MEM_PVR_Select> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WB_Sel_SPR_PVR<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <PVR> synthesized.


Synthesizing Unit <instr_mux>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/instr_mux.vhd".
WARNING:Xst:647 - Input <ICache_data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IEXT_data_strobe> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <instr_mux> synthesized.


Synthesizing Unit <PreFetch_Buffer>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/prefetch_buffer.vhd".
WARNING:Xst:646 - Signal <buffer_Addr_Carry<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 3-bit xor2 for signal <buffer_Addr_Sum>.
Unit <PreFetch_Buffer> synthesized.


Synthesizing Unit <mul_unit>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/mul_unit.vhd".
WARNING:Xst:647 - Input <EX_Mulhsu_Instr<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EX_Not_Mul_Op<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EX_Mulh_Instr<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EX_Mulhu_Instr<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <wb_prod_BD_plus_AD_plus_BC<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <wb_prod_BD<0:15>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <wb_prod_AD_plus_BC_high> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <wb_prod_AC> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <wb_mul64_result> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <wb_mul32_result> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mem_prod_BD<0:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mem_prod_BC<0:19>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mem_prod_AD_plus_BC_high_I> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mem_prod_AD_plus_BC_I<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mem_prod_AD<0:19>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mem_prod_AC> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mem_mulhu_instr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mem_mulh_instr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mem_mul64_instr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mem_PipeRun_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mem_PipeRun_and_not_mul64_op> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mem_PipeRun_and_not_mul32_op> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 17-bit adder for signal <mem_prod_AD_plus_BC_I>.
    Found 17-bit adder for signal <mem_prod_BD_plus_AD_plus_BC>.
    Found 32-bit register for signal <wb_prod_BD>.
    Found 17-bit register for signal <wb_prod_BD_plus_AD_plus_BC>.
    Summary:
	inferred  49 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <mul_unit> synthesized.


Synthesizing Unit <Zero_Detect>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/zero_detect.vhd".
Unit <Zero_Detect> synthesized.


Synthesizing Unit <Register_File_Bit>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/register_file_bit.vhd".
WARNING:Xst:647 - Input <Reg_Write<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <Register_File_Bit> synthesized.


Synthesizing Unit <Operand_Select_Bit_1>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select_bit.vhd".
WARNING:Xst:647 - Input <Use_Imm_Reg<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Reset<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sign_Imm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <exception_or_brk_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Store_PC_For_Intr_NoImm_S> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <Operand_Select_Bit_1> synthesized.


Synthesizing Unit <Operand_Select_Bit_2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select_bit.vhd".
WARNING:Xst:647 - Input <Use_Imm_Reg<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Reset<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sign_Imm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <exception_or_brk_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <Operand_Select_Bit_2> synthesized.


Synthesizing Unit <Operand_Select_Bit_3>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select_bit.vhd".
WARNING:Xst:647 - Input <Use_Imm_Reg<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Reset<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sign_Imm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <exception_or_brk_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <Operand_Select_Bit_3> synthesized.


Synthesizing Unit <Operand_Select_Bit_4>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select_bit.vhd".
WARNING:Xst:647 - Input <Use_Imm_Reg<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Reset<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sign_Imm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <exception_or_brk_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <Operand_Select_Bit_4> synthesized.


Synthesizing Unit <Operand_Select_Bit_5>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select_bit.vhd".
WARNING:Xst:647 - Input <Use_Imm_Reg<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Reset<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sign_Imm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <exception_or_brk_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <Operand_Select_Bit_5> synthesized.


Synthesizing Unit <Operand_Select_Bit_6>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select_bit.vhd".
WARNING:Xst:647 - Input <Use_Imm_Reg<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Reset<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Sign_Imm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Enable_MSR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MSR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <exception_or_brk_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <Operand_Select_Bit_6> synthesized.


Synthesizing Unit <Operand_Select_Bit_7>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select_bit.vhd".
WARNING:Xst:647 - Input <Reset<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Take_Ext_BRK<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Enable_MSR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MSR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <take_Exception_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <Operand_Select_Bit_7> synthesized.


Synthesizing Unit <Operand_Select_Bit_8>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select_bit.vhd".
WARNING:Xst:647 - Input <Reset<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Take_Ext_BRK<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <take_Exception_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <Operand_Select_Bit_8> synthesized.


Synthesizing Unit <ALU_Bit_1>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/alu_bit.vhd".
WARNING:Xst:647 - Input <EX_CMP_Op<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EX_ALU_Sel_Logic> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EX_Enable_ALU> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EX_Unsigned_Op<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <ALU_Bit_1> synthesized.


Synthesizing Unit <ALU_Bit_2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/alu_bit.vhd".
WARNING:Xst:647 - Input <EX_ALU_Sel_Logic> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EX_Enable_ALU> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit xor2 for signal <maintain_sign_n$xor0000> created at line 239.
Unit <ALU_Bit_2> synthesized.


Synthesizing Unit <Shift_Logic_Bit>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/shift_logic_bit.vhd".
Unit <Shift_Logic_Bit> synthesized.


Synthesizing Unit <carry_equal>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/carry_equal.vhd".
    Found 1-bit xor2 for signal <sel_0$xor0000>.
    Found 1-bit xor2 for signal <sel_0$xor0001>.
    Found 1-bit xor2 for signal <sel_1$xor0000>.
    Found 1-bit xor2 for signal <sel_1$xor0001>.
    Found 1-bit xor2 for signal <sel_2$xor0000>.
    Found 1-bit xor2 for signal <sel_2$xor0001>.
    Found 1-bit xor2 for signal <sel_3$xor0000>.
    Found 1-bit xor2 for signal <sel_3$xor0001>.
Unit <carry_equal> synthesized.


Synthesizing Unit <Result_Mux_Bit>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/result_mux_bit.vhd".
Unit <Result_Mux_Bit> synthesized.


Synthesizing Unit <MSR_Reg_Bit>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/msr_reg_bit.vhd".
Unit <MSR_Reg_Bit> synthesized.


Synthesizing Unit <PC_Bit_1>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/pc_bit.vhd".
Unit <PC_Bit_1> synthesized.


Synthesizing Unit <PC_Bit_2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/pc_bit.vhd".
Unit <PC_Bit_2> synthesized.


Synthesizing Unit <Data_Read_Steering>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/data_read_steering.vhd".
Unit <Data_Read_Steering> synthesized.


Synthesizing Unit <mux4_8>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/mux4_8.vhd".
Unit <mux4_8> synthesized.


Synthesizing Unit <address_hit>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/address_hit.vhd".
WARNING:Xst:646 - Signal <SRL16_MC15<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <address_hit> synthesized.


Synthesizing Unit <Decode>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/decode.vhd".
WARNING:Xst:647 - Input <Div_By_Zero> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <word_r1_r2_unalignment> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <D_Exception> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Enable_BusLock<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <word_r1_imm_unalignment> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL_Stall> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Dbg_Want_To_Break_FSL> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <halfword_unalignment> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ESR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL_Put_Succesful> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <I_Exception> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DCache_Read_Idle<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL_Get_Succesful> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ICache_Read_Idle<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EX_FSL_Control_Error> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Div_Overflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <write_load_result> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <unalignment_exc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <take_Intr_Now_s> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <take_Intr_Now_EX<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <quadlet_i<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <opsel1_SPR_Select_II> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <of_fsl_test> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <of_fsl_put> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <of_fsl_get> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <of_fsl_exceptionable> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <of_fsl_control> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <of_fsl_blocking> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <instr_exception> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <if_valid<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Illegal_Opcode_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Illegal_Opcode_EX> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <IExt_Exception_EX> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Put_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Get_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Exceptionable> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Break> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <EX_MSR_Load_FSL_C_I> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Div_Exception_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <DExt_Exception> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <Valid_Instr>.
    Found 1-bit register for signal <Interrupt_Taken>.
    Found 3-bit register for signal <FPU_Cond>.
    Found 1-bit register for signal <MSRclr_Instr<0>>.
    Found 1-bit register for signal <PCMP_Instr<0>>.
    Found 1-bit register for signal <Use_Store_Instr_Addr>.
    Found 3-bit register for signal <FPU_Op>.
    Found 1-bit register for signal <Sext8<0>>.
    Found 1-bit register for signal <Branch_Instr>.
    Found 1-bit register for signal <Not_Div_Op>.
    Found 1-bit register for signal <Shift_Carry_In>.
    Found 1-bit register for signal <Sign_Extend<0>>.
    Found 1-bit register for signal <Compare_Instr>.
    Found 1-bit register for signal <Sext16<0>>.
    Found 2-bit register for signal <Shift_Oper>.
    Found 2-bit register for signal <Logic_Oper>.
    Found 1-bit register for signal <Select_Logic<0>>.
    Found 1-bit register for signal <Unsigned_Op>.
    Found 1-bit register for signal <Not_FPU_Op>.
    Found 2-bit register for signal <Result_Sel>.
    Found 1-bit register for signal <Dbg_Clean_Stop<0>>.
    Found 1-bit register for signal <Blocked_Valid_Instr>.
    Found 1-bit register for signal <break_Pipe_i<0>>.
    Found 1-bit register for signal <bs_first<0>>.
    Found 1-bit register for signal <byte_i<0>>.
    Found 1-bit register for signal <d_AS_I>.
    Found 1-bit register for signal <div_first<0>>.
    Found 1-bit register for signal <div_started>.
    Found 1-bit register for signal <doublet_i<0>>.
    Found 1-bit register for signal <doublet_Read_i<0>>.
    Found 1-bit register for signal <enable_Interrupts_I<0>>.
    Found 1-bit register for signal <EX_delayslot_Instr_I<0>>.
    Found 1-bit register for signal <ex_not_mul_op_i<0>>.
    Found 1-bit register for signal <ex_Valid<0>>.
    Found 1-bit register for signal <ex_Valid_1st_cycle<0>>.
    Found 1-bit register for signal <fpu_first<0>>.
    Found 1-bit register for signal <fpu_started>.
    Found 1-bit register for signal <iFetch_In_Progress<0>>.
    Found 1-bit register for signal <inHibit_EX<0>>.
    Found 32-bit register for signal <instr_EX_i>.
    Found 1-bit register for signal <is_lwx_I<0>>.
    Found 1-bit register for signal <is_swx_I<0>>.
    Found 1-bit register for signal <jump2_I<0>>.
    Found 1-bit register for signal <jump2_I_1<0>>.
    Found 1-bit register for signal <load_Store_i<0>>.
    Found 1-bit register for signal <Load_Store_Instr_Addr_Stored>.
    Found 1-bit register for signal <missed_IFetch<0>>.
    Found 1-bit register for signal <msrxxx_carry>.
    Found 1-bit xor2 for signal <msrxxx_carry$xor0000> created at line 2625.
    Found 1-bit register for signal <MSRxxx_Instr_i<0>>.
    Found 1-bit register for signal <msrxxx_write_carry>.
    Found 1-bit register for signal <mtsmsr_write_i<0>>.
    Found 1-bit register for signal <mul_Executing<0>>.
    Found 1-bit register for signal <mul_Executing_delayed>.
    Found 1-bit register for signal <mul_Executing_done>.
    Found 1-bit register for signal <mul_first<0>>.
    Found 1-bit register for signal <nonvalid_IFetch_n>.
    Found 1-bit register for signal <pvr_first<0>>.
    Found 1-bit register for signal <quadlet_Read_i<0>>.
    Found 1-bit register for signal <reservation<0>>.
    Found 1-bit register for signal <reset_BIP_I<0>>.
    Found 1-bit register for signal <select_ALU_Carry<0>>.
    Found 1-bit register for signal <set_BIP_I<0>>.
    Found 1-bit register for signal <Start_Div_i>.
    Found 1-bit register for signal <Start_FPU_i>.
    Found 1-bit register for signal <swx_ready<0>>.
    Found 1-bit register for signal <take_Break<0>>.
    Found 1-bit register for signal <take_Break_2nd_cycle<0>>.
    Found 1-bit register for signal <take_intr<0>>.
    Found 1-bit register for signal <take_intr_2nd_cycle<0>>.
    Found 1-bit register for signal <take_Intr_2nd_Phase<0>>.
    Found 1-bit register for signal <take_intr_Done<0>>.
    Found 1-bit register for signal <take_NM_Break<0>>.
    Found 1-bit register for signal <take_NM_Break_2nd_cycle<0>>.
    Found 1-bit register for signal <trace_valid_instr_part1>.
    Found 1-bit register for signal <using_Imm<0>>.
    Found 1-bit register for signal <wdc_first<0>>.
    Found 1-bit register for signal <wic_first<0>>.
    Found 5-bit register for signal <write_Addr_I>.
    Found 1-bit register for signal <write_Carry_I<0>>.
    Found 1-bit register for signal <Write_DIV_result<0>>.
    Found 1-bit register for signal <Write_FPU_result<0>>.
    Found 1-bit register for signal <write_FSR_I<0>>.
    Found 1-bit register for signal <write_MSR_I<0>>.
    Found 1-bit register for signal <write_Reg<0>>.
    Found 1-bit register for signal <writing<0>>.
    Summary:
	inferred 127 D-type flip-flop(s).
Unit <Decode> synthesized.


Synthesizing Unit <Byte_Doublet_Handle>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/byte_doublet_handle.vhd".
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit xor3 for signal <Low_Addr<0>>.
    Found 1-bit xor2 for signal <Low_Addr<1>>.
    Summary:
	inferred   1 Xor(s).
Unit <Byte_Doublet_Handle> synthesized.


Synthesizing Unit <Debug>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/debug.vhd".
WARNING:Xst:647 - Input <Data_Write> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Data_Addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Write_Instr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Read_Instr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DReady> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <tdo_config_word1<12:13>> is used but never assigned. This sourceless signal will be automatically connected to value 00.
WARNING:Xst:646 - Signal <shift_datain<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <of_normal_stop> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <control_reg<6:7>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Instr_Insert_Reg_En_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <MB_Halted>.
    Found 1-bit register for signal <brki_hit>.
    Found 1-bit register for signal <brki_hit_1>.
    Found 2-bit register for signal <command_reg>.
    Found 1-bit register for signal <Command_Reg_Rst>.
    Found 1-bit register for signal <continue_from_brk>.
    Found 1-bit register for signal <continue_from_brk_TClk>.
    Found 9-bit register for signal <control_reg>.
    Found 33-bit register for signal <data_rd_reg>.
    Found 33-bit register for signal <data_read_reg>.
    Found 1-bit register for signal <dbg_stop_1>.
    Found 1-bit register for signal <dbg_stop_Detected>.
    Found 1-bit register for signal <Debug_Ready_i>.
    Found 1-bit register for signal <delay_slot_instr_i>.
    Found 1-bit register for signal <force_stop_cmd_hold>.
    Found 1-bit register for signal <force_stop_cmd_i>.
    Found 1-bit register for signal <force_stop_TClk>.
    Found 1-bit register for signal <Full_32_bit>.
    Found 1-bit register for signal <Full_32_bit_1>.
    Found 1-bit register for signal <Instr_Insert_Reg_En_Clk>.
    Found 1-bit register for signal <memory_stalled_1>.
    Found 1-bit register for signal <New_Dbg_Instr2_CLK>.
    Found 1-bit register for signal <New_Dbg_Instr2_TCK>.
    Found 1-bit register for signal <New_Dbg_Instr_CLK>.
    Found 1-bit register for signal <New_Dbg_Instr_TCK>.
    Found 32-bit register for signal <New_Instr_Reg_TCK>.
    Found 1-bit register for signal <normal_stop_cmd_hold>.
    Found 1-bit register for signal <normal_stop_cmd_i>.
    Found 1-bit register for signal <normal_stop_TClk>.
    Found 1-bit register for signal <pc_hit<0>>.
    Found 16-bit register for signal <pc_hit_1>.
    Found 1-bit register for signal <prev>.
    Found 1-bit register for signal <prev0>.
    Found 1-bit register for signal <prev1>.
    Found 1-bit register for signal <prev2>.
    Found 2-bit register for signal <prev3>.
    Found 1-bit register for signal <prev_1>.
    Found 1-bit register for signal <prev_10>.
    Found 1-bit register for signal <prev_11>.
    Found 1-bit register for signal <prev_12>.
    Found 2-bit register for signal <prev_13>.
    Found 1-bit register for signal <read_pc>.
    Found 1-bit register for signal <read_register_MSR>.
    Found 1-bit register for signal <read_register_MSR_1>.
    Found 1-bit register for signal <read_register_PC>.
    Found 1-bit register for signal <read_register_PC_1>.
    Found 8-bit up counter for signal <shift_Count>.
    Found 31-bit register for signal <shift_datain<1:31>>.
    Found 2-bit down counter for signal <single_step_count>.
    Found 1-bit register for signal <single_Step_N>.
    Found 1-bit register for signal <single_Step_TClk>.
    Found 1-bit register for signal <Start_Dbg_Exec>.
    Found 1-bit register for signal <start_single_cmd>.
    Found 1-bit register for signal <start_single_step>.
    Found 24-bit register for signal <status_reg>.
    Found 1-bit register for signal <stop_Instr_Fetch_1>.
    Found 1-bit 16-to-1 multiplexer for signal <TDO_Config_Word>.
    Found 1-bit 33-to-1 multiplexer for signal <TDO_Data_Reg>.
    Found 1-bit 24-to-1 multiplexer for signal <TDO_Status_Reg>.
    Found 1-bit register for signal <Use_Imm_Reg_1<0>>.
    Summary:
	inferred   2 Counter(s).
	inferred 229 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <Debug> synthesized.


Synthesizing Unit <Register_File>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/register_file.vhd".
WARNING:Xst:647 - Input <Reset<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <Register_File> synthesized.


Synthesizing Unit <Operand_Select>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/operand_select.vhd".
WARNING:Xst:647 - Input <MFS_Reg_Sel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EAR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EDR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BTR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ESR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit register for signal <imm_Reg>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <Operand_Select> synthesized.


Synthesizing Unit <ALU>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/alu.vhd".
WARNING:Xst:647 - Input <EX_Use_Carry<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <ex_subtract_op> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <ALU> synthesized.


Synthesizing Unit <Shift_Logic_Module>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/shift_logic.vhd".
Unit <Shift_Logic_Module> synthesized.


Synthesizing Unit <Result_Mux>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/result_mux.vhd".
WARNING:Xst:647 - Input <Reset<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Op1<0:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Op1<17:23>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Op1<25:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <Result_Mux> synthesized.


Synthesizing Unit <MSR_Reg>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/msr_reg.vhd".
WARNING:Xst:647 - Input <Op1<21>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Op2<21>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <we_Bits<22:27>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <we_Bits<31>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <set_Values_I<22:27>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <set_Values_I<31>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rst_Values_I<22:27>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rst_Values_I<31>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rst_Values<29>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <new_Value_I<22:27>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <new_Value_I<31>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <MSR_Reg> synthesized.


Synthesizing Unit <PC_Module>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/pc_module.vhd".
WARNING:Xst:646 - Signal <Carry<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <PC_Module> synthesized.


Synthesizing Unit <Data_Flow>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/data_flow.vhd".
WARNING:Xst:647 - Input <Left_Shift> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FPU_Cond> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Start_Div> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FPU_Op> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Arith_Shift> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Start_FPU> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSR_Write<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EX_FSL_Control_Error> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <start_fpu_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <not_FPU_Op_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <not_FPU_Instr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <not_Div_Op_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <not_Barrel_Op_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <hold_fpu_excep> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <fpu_excep_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <fpu_done_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <fpu_div_done> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <WB_PVR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <EX_not_Mul_Op_i<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <Data_Flow> synthesized.


Synthesizing Unit <microblaze>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/hdl/vhdl/microblaze.vhd".
WARNING:Xst:647 - Input <FSL1_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL7_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL15_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL7_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL7_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL15_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ICACHE_FSL_IN_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ICACHE_FSL_IN_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL5_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL4_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL12_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL0_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL6_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL6_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DCACHE_FSL_OUT_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL14_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL13_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DCACHE_FSL_IN_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL3_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL5_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL15_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL3_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL11_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL11_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL9_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL5_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL13_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL4_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL14_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL1_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL8_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL2_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL10_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL8_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL4_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL12_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL3_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL13_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DWait> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL6_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DCACHE_FSL_IN_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL2_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL12_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL14_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ICACHE_FSL_OUT_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL1_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL7_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL15_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL3_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL11_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL9_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DCACHE_FSL_IN_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL4_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL1_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL11_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL12_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL0_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL9_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL6_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL14_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL2_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL10_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL2_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL0_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL8_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL10_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL9_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL10_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ICACHE_FSL_IN_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL8_S_Exists> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL0_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL5_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL13_M_Full> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <write_dcache_tag<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <write_dcache_flush<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <write_dcache<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <valid_icache_access> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <valid_dcache_access> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <op1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <iWrite_Strobe_No_Dbg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <iRead_Strobe_No_Dbg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fsl_will_dbg_break> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ex_load_btr<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <daxi_exclusive_failed> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <d_exclusive> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Write_ICache<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Word_Access> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Unaligned_Exception> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SW_Instr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Not_MB_Get_Op> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MEM_Sel_FSL<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MEM_FSL_Result> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <MEM_EX_Result_Load<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Load_ESR<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Load_EDR<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Load_EAR<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Illegal_Opcode_Exception> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <IExt_Bus_Exception> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ICache_Enabled<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ICACHE_Stat> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <FSL_S_Read> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_S_Exists> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_S_Data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_S_Control> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Put_Test> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <FSL_Put_No<31:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Put_No<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Put_Inhibit> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Put_Data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Put_Control> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Put_Break> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Put_Blocking> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Put> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <FSL_M_Write> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_M_Full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <FSL_M_Data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <FSL_M_Control> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Get_Test> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <FSL_Get_No<31:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Get_No<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Get_Inhibit> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Get_Control> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Get_Break> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Get_Blocking> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Get> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FSL_Exception0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FPU_Exception0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <EX_delayslot_Instr<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <EX_MSR_Load_FSL_C> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <EDR> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
WARNING:Xst:646 - Signal <Div_Exception> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <DExt_Bus_Exception> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <DCache_Enabled<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <DCACHE_Stat> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Control_Reg_D> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Command_Reg_D> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Clr_ESR<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 5-bit register for signal <Trace_Reg_Addr>.
    Found 32-bit register for signal <Trace_Data_Write_Value>.
    Found 1-bit register for signal <Trace_Data_Write>.
    Found 1-bit register for signal <Trace_Data_Access>.
    Found 32-bit register for signal <Trace_PC>.
    Found 5-bit register for signal <Trace_Exception_Kind>.
    Found 1-bit register for signal <Trace_Delay_Slot>.
    Found 1-bit register for signal <Trace_Jump_Taken>.
    Found 1-bit register for signal <Trace_Data_Read>.
    Found 4-bit register for signal <Trace_Data_Byte_Enable>.
    Found 32-bit register for signal <Trace_Instruction>.
    Found 11-bit register for signal <Trace_MSR_Reg<4:14>>.
    Found 32-bit register for signal <Trace_Data_Address>.
    Found 1-bit register for signal <Trace_OF_PipeRun>.
    Found 1-bit register for signal <Trace_Exception_Taken>.
    Found 32-bit register for signal <Instr_Addr_Stored>.
    Found 32-bit register for signal <Instr_Addr_Stored_1>.
    Found 1-bit register for signal <mem_access>.
    Found 1-bit register for signal <reg_Write_dbg_S>.
    Found 1-bit register for signal <reset_temp>.
    Found 1-bit register for signal <sync_reset>.
    Found 1-bit register for signal <trace_reg_write_i>.
    Summary:
	inferred 229 D-type flip-flop(s).
Unit <microblaze> synthesized.


Synthesizing Unit <microblaze_0_wrapper>.
    Related source file is "C:/Temp/Bomberman/hdl/microblaze_0_wrapper.vhd".
Unit <microblaze_0_wrapper> synthesized.

WARNING:Xst:524 - All outputs of the instance <PVR_I> of the block <PVR> are unconnected in block <Data_Flow>.
   This instance will be removed from the design along with all underlying logic

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 17-bit adder                                          : 2
# Counters                                             : 2
 2-bit down counter                                    : 1
 8-bit up counter                                      : 1
# Registers                                            : 308
 1-bit register                                        : 277
 16-bit register                                       : 2
 17-bit register                                       : 1
 2-bit register                                        : 6
 3-bit register                                        : 2
 32-bit register                                       : 13
 33-bit register                                       : 1
 4-bit register                                        : 2
 5-bit register                                        : 3
 9-bit register                                        : 1
# Multiplexers                                         : 3
 1-bit 16-to-1 multiplexer                             : 1
 1-bit 24-to-1 multiplexer                             : 1
 1-bit 33-to-1 multiplexer                             : 1
# Xors                                                 : 39
 1-bit xor2                                            : 38
 1-bit xor3                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:2677 - Node <wb_prod_BD_15> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_14> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_13> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_12> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_11> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_10> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_9> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_8> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_7> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_6> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_5> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_4> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_3> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_2> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_1> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_0> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <wb_prod_BD_plus_AD_plus_BC_0> of sequential type is unconnected in block <mul_unit>.
WARNING:Xst:2677 - Node <control_reg_7> of sequential type is unconnected in block <Debug>.
WARNING:Xst:2677 - Node <control_reg_6> of sequential type is unconnected in block <Debug>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 2
 16-bit adder                                          : 1
 17-bit adder                                          : 1
# Counters                                             : 2
 2-bit down counter                                    : 1
 8-bit up counter                                      : 1
# Registers                                            : 1020
 Flip-Flops                                            : 1020
# Multiplexers                                         : 3
 1-bit 16-to-1 multiplexer                             : 1
 1-bit 24-to-1 multiplexer                             : 1
 1-bit 33-to-1 multiplexer                             : 1
# Xors                                                 : 39
 1-bit xor2                                            : 38
 1-bit xor3                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch <div_first_0> has a constant value of 0 in block <Decode>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <wdc_first_0> has a constant value of 0 in block <Decode>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <fpu_first_0> has a constant value of 0 in block <Decode>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <wic_first_0> has a constant value of 0 in block <Decode>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <pvr_first_0> has a constant value of 0 in block <Decode>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <bs_first_0> has a constant value of 0 in block <Decode>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <pc_hit_1_1> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_2> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_3> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_4> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_5> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_6> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_7> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_8> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_9> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_10> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_11> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_12> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_13> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_14> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <pc_hit_1_15> (without init value) has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_21> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_15> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_14> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_12> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_13> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_11> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_10> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_9> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_8> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_7> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_5> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_4> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_6> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_3> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_2> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_reg_1> has a constant value of 0 in block <Debug>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <Shift_Oper_0> in Unit <Decode> is equivalent to the following 2 FFs/Latches, which will be removed : <FPU_Cond_0> <instr_EX_i_25> 
INFO:Xst:2261 - The FF/Latch <FPU_Op_2> in Unit <Decode> is equivalent to the following FF/Latch, which will be removed : <instr_EX_i_24> 
INFO:Xst:2261 - The FF/Latch <FPU_Op_1> in Unit <Decode> is equivalent to the following FF/Latch, which will be removed : <instr_EX_i_23> 
INFO:Xst:2261 - The FF/Latch <FPU_Cond_2> in Unit <Decode> is equivalent to the following FF/Latch, which will be removed : <instr_EX_i_27> 
INFO:Xst:2261 - The FF/Latch <FPU_Op_0> in Unit <Decode> is equivalent to the following FF/Latch, which will be removed : <instr_EX_i_22> 
INFO:Xst:2261 - The FF/Latch <Logic_Oper_1> in Unit <Decode> is equivalent to the following FF/Latch, which will be removed : <instr_EX_i_5> 
INFO:Xst:2261 - The FF/Latch <Shift_Oper_1> in Unit <Decode> is equivalent to the following 2 FFs/Latches, which will be removed : <FPU_Cond_1> <instr_EX_i_26> 
INFO:Xst:2261 - The FF/Latch <Logic_Oper_0> in Unit <Decode> is equivalent to the following FF/Latch, which will be removed : <instr_EX_i_4> 
INFO:Xst:1901 - Instance Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_BD in unit mul_unit of type MULT18X18S has been replaced by MULT18X18SIO
INFO:Xst:1901 - Instance Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_AD in unit mul_unit of type MULT18X18S has been replaced by MULT18X18SIO
INFO:Xst:1901 - Instance Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_BC in unit mul_unit of type MULT18X18S has been replaced by MULT18X18SIO

Optimizing unit <microblaze_0_wrapper> ...

Optimizing unit <DPLB_Interface> ...

Optimizing unit <IPLB_Interface> ...

Optimizing unit <instr_mux> ...

Optimizing unit <PreFetch_Buffer> ...

Optimizing unit <mul_unit> ...

Optimizing unit <Zero_Detect> ...

Optimizing unit <Operand_Select_Bit_1> ...

Optimizing unit <Operand_Select_Bit_2> ...

Optimizing unit <Operand_Select_Bit_3> ...

Optimizing unit <Operand_Select_Bit_4> ...

Optimizing unit <Operand_Select_Bit_5> ...

Optimizing unit <Operand_Select_Bit_6> ...

Optimizing unit <Operand_Select_Bit_7> ...

Optimizing unit <Operand_Select_Bit_8> ...

Optimizing unit <carry_equal> ...

Optimizing unit <Data_Read_Steering> ...

Optimizing unit <mux4_8> ...

Optimizing unit <address_hit> ...

Optimizing unit <Decode> ...

Optimizing unit <Byte_Doublet_Handle> ...

Optimizing unit <Debug> ...

Optimizing unit <Register_File> ...

Optimizing unit <Operand_Select> ...

Optimizing unit <ALU> ...

Optimizing unit <Shift_Logic_Module> ...

Optimizing unit <Result_Mux> ...

Optimizing unit <MSR_Reg> ...

Optimizing unit <PC_Module> ...

Optimizing unit <Data_Flow> ...

Optimizing unit <microblaze> ...
WARNING:Xst:1293 - FF/Latch <microblaze_0/Area.Decode_I/Write_DIV_result_0> has a constant value of 0 in block <microblaze_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <microblaze_0/Area.Decode_I/Write_FPU_result_0> has a constant value of 0 in block <microblaze_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <microblaze_0/Trace_Exception_Kind_0> (without init value) has a constant value of 0 in block <microblaze_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <microblaze_0/Trace_MSR_Reg_14> (without init value) has a constant value of 0 in block <microblaze_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <microblaze_0/Trace_MSR_Reg_10> (without init value) has a constant value of 0 in block <microblaze_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <microblaze_0/Trace_MSR_Reg_9> (without init value) has a constant value of 0 in block <microblaze_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <microblaze_0/Trace_MSR_Reg_8> (without init value) has a constant value of 0 in block <microblaze_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <microblaze_0/Trace_MSR_Reg_7> (without init value) has a constant value of 0 in block <microblaze_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <microblaze_0/Trace_MSR_Reg_6> (without init value) has a constant value of 0 in block <microblaze_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <microblaze_0/Trace_MSR_Reg_5> (without init value) has a constant value of 0 in block <microblaze_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <microblaze_0/Trace_MSR_Reg_4> (without init value) has a constant value of 0 in block <microblaze_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <microblaze_0/Area.Implement_Debug_Logic.Debug_I/read_pc> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Implement_Debug_Logic.Debug_I/control_reg_2> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Implement_Debug_Logic.Debug_I/control_reg_1> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Decode_I/Interrupt_Taken> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Decode_I/Start_Div_i> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Decode_I/Start_FPU_i> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Decode_I/write_FSR_I_0> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Decode_I/Not_FPU_Op> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Decode_I/EX_delayslot_Instr_I_0> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Decode_I/Branch_Instr> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Decode_I/Not_Div_Op> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Decode_I/fpu_started> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Decode_I/div_started> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/IPLB_Exception> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Using_Ext_Databus.Using_D_PLB.DPLB_Interface_I1/MEM_DPLB_Exception> of sequential type is unconnected in block <microblaze_0_wrapper>.
WARNING:Xst:2677 - Node <microblaze_0/Area.Using_Ext_Databus.Using_D_PLB.DPLB_Interface_I1/WB_DPLB_Data_Strobe> of sequential type is unconnected in block <microblaze_0_wrapper>.

Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_0> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_0> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_1> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_110> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_2> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_2> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_3> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_3> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_4> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_4> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_5> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_5> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_6> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_6> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_7> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_7> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_8> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_8> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_9> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_9> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_10> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_10> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_11> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_11> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_12> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_12> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_13> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_13> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_14> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_14> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_15> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_15> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_20> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_20> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_16> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_16> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_21> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_21> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_17> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_17> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_22> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_22> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_23> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_23> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_18> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_18> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_19> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_19> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_24> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_24> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_30> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_30> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_25> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_25> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_31> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_31> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_26> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_26> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_27> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_27> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Trace_Exception_Kind_1> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Trace_Exception_Taken> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_28> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_28> 
INFO:Xst:2261 - The FF/Latch <microblaze_0/Area.Using_I_PLB.IPLB_Interface_I1/instr_addr_29> in Unit <microblaze_0_wrapper> is equivalent to the following FF/Latch, which will be removed : <microblaze_0/Instr_Addr_Stored_29> 

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 923
 Flip-Flops                                            : 923

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/microblaze_0_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 2072

Cell Usage :
# BELS                             : 1617
#      GND                         : 1
#      INV                         : 9
#      LUT1                        : 43
#      LUT2                        : 129
#      LUT2_D                      : 5
#      LUT2_L                      : 2
#      LUT3                        : 396
#      LUT3_D                      : 4
#      LUT3_L                      : 4
#      LUT4                        : 485
#      LUT4_D                      : 7
#      LUT4_L                      : 11
#      MULT_AND                    : 34
#      MUXCY                       : 52
#      MUXCY_L                     : 118
#      MUXF5                       : 200
#      MUXF6                       : 6
#      MUXF7                       : 2
#      MUXF8                       : 1
#      VCC                         : 1
#      XORCY                       : 107
# FlipFlops/Latches                : 923
#      FD                          : 217
#      FDCE                        : 6
#      FDE                         : 241
#      FDR                         : 191
#      FDRE                        : 183
#      FDRS                        : 6
#      FDRSE                       : 41
#      FDS                         : 4
#      FDSE                        : 34
# RAMS                             : 128
#      RAM16X1D                    : 128
# Shift Registers                  : 84
#      SRL16E                      : 76
#      SRLC16E                     : 8
# MULTs                            : 3
#      MULT18X18SIO                : 3
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                      754  out of   8672     8%  
 Number of Slice Flip Flops:            923  out of  17344     5%  
 Number of 4 input LUTs:               1435  out of  17344     8%  
    Number used as logic:              1095
    Number used as Shift registers:      84
    Number used as RAMs:                256
 Number of IOs:                        2072
 Number of bonded IOBs:                   0  out of    250     0%  
 Number of MULT18X18SIOs:                 3  out of     28    10%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+----------------------------------------------------------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                                                                          | Load  |
-----------------------------------+----------------------------------------------------------------------------------------------------------------+-------+
DCACHE_FSL_OUT_CLK                 | NONE(microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_BC)| 989   |
DBG_CLK                            | NONE(microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK)                                        | 138   |
DBG_UPDATE                         | NONE(microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_TClk)                                          | 11    |
-----------------------------------+----------------------------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------+
Control Signal                                                                                                                        | Buffer(FF name)                                                             | Load  |
--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------+
microblaze_0/Area.Implement_Debug_Logic.Debug_I/Command_Reg_Rst(microblaze_0/Area.Implement_Debug_Logic.Debug_I/Command_Reg_Rst:Q)    | NONE(microblaze_0/Area.Implement_Debug_Logic.Debug_I/command_reg_0)         | 2     |
microblaze_0/Area.Implement_Debug_Logic.Debug_I/continue_from_brk(microblaze_0/Area.Implement_Debug_Logic.Debug_I/continue_from_brk:Q)| NONE(microblaze_0/Area.Implement_Debug_Logic.Debug_I/continue_from_brk_TClk)| 1     |
microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_cmd(microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_cmd1:O)     | NONE(microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_TClk)       | 1     |
microblaze_0/Area.Implement_Debug_Logic.Debug_I/normal_stop_cmd(microblaze_0/Area.Implement_Debug_Logic.Debug_I/normal_stop_cmd1:O)   | NONE(microblaze_0/Area.Implement_Debug_Logic.Debug_I/normal_stop_TClk)      | 1     |
microblaze_0/Area.Implement_Debug_Logic.Debug_I/start_single_step(microblaze_0/Area.Implement_Debug_Logic.Debug_I/start_single_step:Q)| NONE(microblaze_0/Area.Implement_Debug_Logic.Debug_I/single_Step_TClk)      | 1     |
--------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.797ns (Maximum Frequency: 92.615MHz)
   Minimum input arrival time before clock: 6.919ns
   Maximum output required time after clock: 9.420ns
   Maximum combinational path delay: 3.166ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'DCACHE_FSL_OUT_CLK'
  Clock period: 10.797ns (frequency: 92.615MHz)
  Total number of paths / destination ports: 89869 / 3284
-------------------------------------------------------------------------
Delay:               10.797ns (Levels of Logic = 10)
  Source:            microblaze_0/Area.Implement_Debug_Logic.Debug_I/Using_FPGA.Dbg_Inhibit_EX_FDRSE (FF)
  Destination:       microblaze_0/Area.Data_Flow_I/Operand_Select_I/Using_FPGA.OpSelect_Bits[29].Operand_Select_Bit_I/Op1_DFF (FF)
  Source Clock:      DCACHE_FSL_OUT_CLK rising
  Destination Clock: DCACHE_FSL_OUT_CLK rising

  Data Path: microblaze_0/Area.Implement_Debug_Logic.Debug_I/Using_FPGA.Dbg_Inhibit_EX_FDRSE to microblaze_0/Area.Data_Flow_I/Operand_Select_I/Using_FPGA.OpSelect_Bits[29].Operand_Select_Bit_I/Op1_DFF
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRSE:C->Q           42   0.591   1.344  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Using_FPGA.Dbg_Inhibit_EX_FDRSE (microblaze_0/Dbg_Inhibit_EX)
     LUT2_D:I1->LO         1   0.704   0.104  microblaze_0/Area.Decode_I/Set_BIP_0_or000011 (N138)
     LUT4:I3->O            1   0.704   0.499  microblaze_0/Area.Data_Flow_I/Shift_Logic_Module_I/op1_shift_29_mux00001 (microblaze_0/Area.Data_Flow_I/Shift_Logic_Module_I/op1_shift<29>)
     LUT4:I1->O            1   0.704   0.000  microblaze_0/Area.Data_Flow_I/Shift_Logic_Module_I/Using_FPGA.Shift_Logic_Bits[29].Shift_Logic_Bit_I/Shift_LUT (microblaze_0/Area.Data_Flow_I/Shift_Logic_Module_I/Using_FPGA.Shift_Logic_Bits[29].Shift_Logic_Bit_I/shift_Res)
     MUXF5:I0->O           1   0.321   0.499  microblaze_0/Area.Data_Flow_I/Shift_Logic_Module_I/Using_FPGA.Shift_Logic_Bits[29].Shift_Logic_Bit_I/Shift_Logic_Mux (microblaze_0/Area.Data_Flow_I/Shift_Logic_Module_I/Shift_Logic_Result_ii<29>)
     LUT2_L:I1->LO         1   0.704   0.275  microblaze_0/Area.Data_Flow_I/Shift_Logic_Module_I/normal_res_0_and00001 (microblaze_0/Area.Data_Flow_I/Shift_Logic_Module_I/normal_res<0>)
     LUT2:I0->O            1   0.704   0.499  microblaze_0/Area.Data_Flow_I/Shift_Logic_Module_I/Use_PCMP_instr.Using_FPGA.shift_logic_result_i_lut_0 (microblaze_0/Area.Data_Flow_I/shift_Logic_Result<29>)
     LUT4:I1->O            1   0.704   0.000  microblaze_0/Area.Data_Flow_I/Result_Mux_I/Using_FPGA.Result_Mux_Bits[29].Result_Mux_Bit_I/Data_Shift_Mux (microblaze_0/Area.Data_Flow_I/Result_Mux_I/Using_FPGA.Result_Mux_Bits[29].Result_Mux_Bit_I/data_Shift_Res)
     MUXF5:I1->O           7   0.321   0.787  microblaze_0/Area.Data_Flow_I/Result_Mux_I/Using_FPGA.Result_Mux_Bits[29].Result_Mux_Bit_I/Result_MUXF5 (microblaze_0/Area.Data_Flow_I/ex_Result<29>)
     LUT3:I1->O            2   0.704   0.000  microblaze_0/Area.Data_Flow_I/Operand_Select_I/Using_FPGA.OpSelect_Bits[29].Operand_Select_Bit_I/Op1_Mux2_1 (microblaze_0/Area.Data_Flow_I/Operand_Select_I/Using_FPGA.OpSelect_Bits[29].Operand_Select_Bit_I/op1_Reg)
     MUXF5:I0->O           1   0.321   0.000  microblaze_0/Area.Data_Flow_I/Operand_Select_I/Using_FPGA.OpSelect_Bits[29].Operand_Select_Bit_I/Op1_MUXF5 (microblaze_0/Area.Data_Flow_I/Operand_Select_I/Using_FPGA.OpSelect_Bits[29].Operand_Select_Bit_I/op1_I)
     FDE:D                     0.308          microblaze_0/Area.Data_Flow_I/Operand_Select_I/Using_FPGA.OpSelect_Bits[29].Operand_Select_Bit_I/Op1_DFF
    ----------------------------------------
    Total                     10.797ns (6.790ns logic, 4.007ns route)
                                       (62.9% logic, 37.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'DBG_CLK'
  Clock period: 5.031ns (frequency: 198.768MHz)
  Total number of paths / destination ports: 194 / 162
-------------------------------------------------------------------------
Delay:               5.031ns (Levels of Logic = 2)
  Source:            microblaze_0/Area.Implement_Debug_Logic.Debug_I/shift_Count_2 (FF)
  Destination:       microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK (FF)
  Source Clock:      DBG_CLK rising
  Destination Clock: DBG_CLK rising

  Data Path: microblaze_0/Area.Implement_Debug_Logic.Debug_I/shift_Count_2 to microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             20   0.591   1.277  microblaze_0/Area.Implement_Debug_Logic.Debug_I/shift_Count_2 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/shift_Count_2)
     LUT3:I0->O            1   0.704   0.424  microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK_or0000_SW0 (N8)
     LUT4:I3->O            1   0.704   0.420  microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK_or0000 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK_or0000)
     FDR:R                     0.911          microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK
    ----------------------------------------
    Total                      5.031ns (2.910ns logic, 2.121ns route)
                                       (57.8% logic, 42.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'DCACHE_FSL_OUT_CLK'
  Total number of paths / destination ports: 2169 / 1048
-------------------------------------------------------------------------
Offset:              6.919ns (Levels of Logic = 8)
  Source:            DREADY (PAD)
  Destination:       microblaze_0/Area.Decode_I/Using_FPGA.Force1_FDRE (FF)
  Destination Clock: DCACHE_FSL_OUT_CLK rising

  Data Path: DREADY to microblaze_0/Area.Decode_I/Using_FPGA.Force1_FDRE
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT2:I0->O            7   0.704   0.708  microblaze_0/combined_dready1 (microblaze_0/combined_dready)
     MUXCY_L:CI->LO      201   0.059   0.000  microblaze_0/Area.Decode_I/Using_FPGA.of_PipeRun_MuxCY_1 (microblaze_0/of_PipeRun)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Decode_I/Using_FPGA.Using_Breakable_Pipe.Take_Intr_MUXCY_1 (microblaze_0/Area.Decode_I/take_Intr_Now_I)
     MUXCY_L:CI->LO        4   0.059   0.000  microblaze_0/Area.Decode_I/Using_FPGA.Using_Breakable_Pipe.Take_Intr_MUXCY_2 (microblaze_0/Area.Decode_I/take_Intr_Now_II)
     MUXCY_L:CI->LO       37   0.059   1.268  microblaze_0/Area.Decode_I/Using_FPGA.Using_Breakable_Pipe.Take_Intr_MUXCY_3 (microblaze_0/Area.Decode_I/take_Intr_Now_III)
     LUT4_D:I3->O          6   0.704   0.704  microblaze_0/Area.Decode_I/write_Carry_I_0_mux0000210 (microblaze_0/Area.Decode_I/N16)
     LUT3:I2->O            6   0.704   0.704  microblaze_0/Area.Decode_I/Reg_Test_Equal_N_i21 (microblaze_0/Area.Decode_I/force2_i)
     LUT3:I2->O            1   0.704   0.000  microblaze_0/Area.Decode_I/force_Val1_i1 (microblaze_0/Area.Decode_I/force_Val1_i)
     FDRE:D                    0.308          microblaze_0/Area.Decode_I/Using_FPGA.Force_Val1_FDRE
    ----------------------------------------
    Total                      6.919ns (3.535ns logic, 3.384ns route)
                                       (51.1% logic, 48.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'DBG_CLK'
  Total number of paths / destination ports: 97 / 61
-------------------------------------------------------------------------
Offset:              5.850ns (Levels of Logic = 4)
  Source:            DBG_REG_EN<1> (PAD)
  Destination:       microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK (FF)
  Destination Clock: DBG_CLK rising

  Data Path: DBG_REG_EN<1> to microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I0->O            2   0.704   0.622  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Command_Reg_En_cmp_eq000011 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/N7)
     LUT3:I0->O            2   0.704   0.482  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Instr_Insert_Reg_En_cmp_eq00001 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/Instr_Insert_Reg_En)
     LUT3:I2->O            1   0.704   0.424  microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK_or0000_SW0 (N8)
     LUT4:I3->O            1   0.704   0.420  microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK_or0000 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK_or0000)
     FDR:R                     0.911          microblaze_0/Area.Implement_Debug_Logic.Debug_I/New_Dbg_Instr_TCK
    ----------------------------------------
    Total                      5.850ns (3.902ns logic, 1.948ns route)
                                       (66.7% logic, 33.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'DBG_UPDATE'
  Total number of paths / destination ports: 55 / 11
-------------------------------------------------------------------------
Offset:              3.440ns (Levels of Logic = 2)
  Source:            DBG_REG_EN<3> (PAD)
  Destination:       microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_TClk (FF)
  Destination Clock: DBG_UPDATE rising

  Data Path: DBG_REG_EN<3> to microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_TClk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I0->O            2   0.704   0.482  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Control_Reg_En_cmp_eq000011 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/N8)
     LUT3:I2->O            9   0.704   0.820  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Control_Reg_En_cmp_eq00001 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/Control_Reg_En)
     FDCE:CE                   0.555          microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_TClk
    ----------------------------------------
    Total                      3.440ns (2.138ns logic, 1.302ns route)
                                       (62.2% logic, 37.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'DCACHE_FSL_OUT_CLK'
  Total number of paths / destination ports: 10260 / 395
-------------------------------------------------------------------------
Offset:              8.261ns (Levels of Logic = 33)
  Source:            microblaze_0/Area.Decode_I/PreFetch_Buffer_I/Using_FPGA.Buffer_DFFs[1].FDS_I (FF)
  Destination:       INSTR_ADDR<0> (PAD)
  Source Clock:      DCACHE_FSL_OUT_CLK rising

  Data Path: microblaze_0/Area.Decode_I/PreFetch_Buffer_I/Using_FPGA.Buffer_DFFs[1].FDS_I to INSTR_ADDR<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q             67   0.591   1.448  microblaze_0/Area.Decode_I/PreFetch_Buffer_I/Using_FPGA.Buffer_DFFs[1].FDS_I (microblaze_0/buffer_Addr<1>)
     LUT3:I0->O            1   0.704   0.595  microblaze_0/Area.Decode_I/PC_Incr_0_and00001 (microblaze_0/pc_Incr)
     LUT4:I0->O            1   0.704   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[29].PC_Bit_I/SUM_I (microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[29].PC_Bit_I/xor_Sum)
     MUXCY_L:S->LO         1   0.464   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[29].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<29>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[28].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<28>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<27>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[26].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<26>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[25].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<25>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[24].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<24>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[23].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<23>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[22].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<22>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[21].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<21>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[20].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<20>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[19].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<19>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[18].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<18>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[17].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<17>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[16].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<16>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[15].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<15>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[14].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<14>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[13].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<13>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[12].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<12>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<11>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[10].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<10>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[9].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<9>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[8].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<8>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[7].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<7>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[6].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<6>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[5].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<5>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[4].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<4>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[3].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<3>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[2].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<2>)
     MUXCY_L:CI->LO        1   0.059   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[1].PC_Bit_I/MUXCY_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Carry<1>)
     XORCY:CI->O           1   0.804   0.595  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[0].PC_Bit_I/XOR_X (microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[0].PC_Bit_I/pc_Sum)
     LUT4:I0->O            2   0.704   0.000  microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[0].PC_Bit_I/NewPC_Mux (INSTR_ADDR<0>)
    ----------------------------------------
    Total                      8.261ns (5.623ns logic, 2.638ns route)
                                       (68.1% logic, 31.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'DBG_CLK'
  Total number of paths / destination ports: 122 / 1
-------------------------------------------------------------------------
Offset:              9.420ns (Levels of Logic = 7)
  Source:            microblaze_0/Area.Implement_Debug_Logic.Debug_I/Use_SRL16.The_Cache_Addresses[7].SRL16E_Cache_I (FF)
  Destination:       DBG_TDO (PAD)
  Source Clock:      DBG_CLK rising

  Data Path: microblaze_0/Area.Implement_Debug_Logic.Debug_I/Use_SRL16.The_Cache_Addresses[7].SRL16E_Cache_I to DBG_TDO
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     SRL16E:CLK->Q         1   3.706   0.499  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Use_SRL16.The_Cache_Addresses[7].SRL16E_Cache_I (microblaze_0/Area.Implement_Debug_Logic.Debug_I/tdo_config_word1<8>)
     LUT3:I1->O            1   0.704   0.000  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Mmux_TDO_Config_Word_11 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/Mmux_TDO_Config_Word_11)
     MUXF5:I0->O           2   0.321   0.482  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Mmux_TDO_Config_Word_9_f5 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/Mmux_TDO_Config_Word_9_f5)
     LUT4:I2->O            1   0.704   0.000  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO141 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO141)
     MUXF5:I1->O           1   0.321   0.455  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO14_f5 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO14)
     LUT3:I2->O            1   0.704   0.000  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO56_G (N124)
     MUXF5:I1->O           1   0.321   0.499  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO56 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO56)
     LUT4:I1->O            0   0.704   0.000  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO158 (DBG_TDO)
    ----------------------------------------
    Total                      9.420ns (7.485ns logic, 1.935ns route)
                                       (79.5% logic, 20.5% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 12 / 6
-------------------------------------------------------------------------
Delay:               3.166ns (Levels of Logic = 3)
  Source:            DBG_REG_EN<4> (PAD)
  Destination:       DBG_TDO (PAD)

  Data Path: DBG_REG_EN<4> to DBG_TDO
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT2:I0->O            1   0.704   0.455  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO120 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO120)
     LUT4:I2->O            1   0.704   0.424  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO123 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO123)
     LUT4:I3->O            0   0.704   0.000  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO158 (DBG_TDO)
    ----------------------------------------
    Total                      3.166ns (2.287ns logic, 0.879ns route)
                                       (72.2% logic, 27.8% route)

=========================================================================


Total REAL time to Xst completion: 54.00 secs
Total CPU time to Xst completion: 53.23 secs
 
--> 

Total memory usage is 218808 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  449 (   0 filtered)
Number of infos    :   73 (   0 filtered)

