Release 12.2 Map M.63c (nt)
Xilinx Map Application Log File for Design 'top'

Design Information
------------------
Command Line   : map -intstyle ise -p xc3s1200e-fg320-4 -cm area -ir off -pr off
-c 100 -o top_map.ncd top.ngd top.pcf 
Target Device  : xc3s1200e
Target Package : fg320
Target Speed   : -4
Mapper Version : spartan3e -- $Revision: 1.52 $
Mapped Date    : Tue Oct 04 11:37:22 2011

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
   fpga_0_Micron_RAM_Mem_OEN_pin is set but the tri state is not configured. 
WARNING:PhysDesignRules:781 - PULLDOWN on an active net. PULLDOWN of comp
   fpga_0_Micron_RAM_Mem_BEN_pin<0> is set but the tri state is not configured. 
WARNING:PhysDesignRules:781 - PULLDOWN on an active net. PULLDOWN of comp
   fpga_0_Micron_RAM_Mem_BEN_pin<1> is set but the tri state is not configured. 

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Number of Slice Flip Flops:         4,152 out of  17,344   23%
  Number of 4 input LUTs:             9,658 out of  17,344   55%
Logic Distribution:
  Number of occupied Slices:          6,148 out of   8,672   70%
    Number of Slices containing only related logic:   6,148 out of   6,148 100%
    Number of Slices containing unrelated logic:          0 out of   6,148   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:       9,819 out of  17,344   56%
    Number used as logic:             9,209
    Number used as a route-thru:        161
    Number used for Dual Port RAMs:     256
      (Two LUTs used per Dual Port RAM)
    Number used as Shift registers:     193

  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

  Number of bonded IOBs:                 90 out of     250   36%
    IOB Flip Flops:                      32
  Number of RAMB16s:                     19 out of      28   67%
  Number of BUFGMUXs:                     2 out of      24    8%
  Number of DCMs:                         1 out of       8   12%
  Number of BSCANs:                       1 out of       1  100%
  Number of MULT18X18SIOs:                3 out of      28   10%

Average Fanout of Non-Clock Nets:                3.74

Peak Memory Usage:  220 MB
Total REAL time to MAP completion:  37 secs 
Total CPU time to MAP completion:   32 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "top_map.mrp" for details.
