Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "mdm_0_wrapper_xst.prj"
Verilog Include Directory          : {"C:\Temp\Bomberman\pcores\" "C:\Xilinx\12.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc3s1200efg320-4
Output File Name                   : "../implementation/mdm_0_wrapper.ngc"

---- Source Options
Top Module Name                    : mdm_0_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation/mdm_0_wrapper}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/hdl/vhdl/srl_fifo.vhd" in Library mdm_v1_00_g.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/hdl/vhdl/jtag_control.vhd" in Library mdm_v1_00_g.
Entity <JTAG_CONTROL> compiled.
Entity <JTAG_CONTROL> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect.vhd" in Library proc_common_v3_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/hdl/vhdl/mdm_core.vhd" in Library mdm_v1_00_g.
Entity <MDM_Core> compiled.
Entity <MDM_Core> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/hdl/vhdl/mdm.vhd" in Library mdm_v1_00_g.
Entity <MDM> compiled.
WARNING:HDLParsers:3534 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/hdl/vhdl/mdm.vhd" Line 549. In the function native_bscan, not all control paths contain a return statement.
Entity <MDM> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/hdl/mdm_0_wrapper.vhd" in Library work.
Entity <mdm_0_wrapper> compiled.
Entity <mdm_0_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <mdm_0_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <mdm> in library <mdm_v1_00_g> (architecture <IMP>) with generics.
	C_BASEADDR = "10000100010000000000000000000000"
	C_FAMILY = "spartan3e"
	C_HIGHADDR = "10000100010000001111111111111111"
	C_INTERCONNECT = 1
	C_JTAG_CHAIN = 2
	C_MB_DBG_PORTS = 1
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SUPPORT_BURSTS = 0
	C_UART_WIDTH = 8
	C_USE_UART = 1
	C_WRITE_FSL_PORTS = 0

Analyzing hierarchy for entity <MDM_Core> in library <mdm_v1_00_g> (architecture <IMP>) with generics.
	C_BASEADDR = "10000100010000000000000000000000"
	C_FSL_DATA_SIZE = 32
	C_HIGHADDR = "10000100010000001111111111111111"
	C_INTERCONNECT = 1
	C_MB_DBG_PORTS = 1
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SUPPORT_BURSTS = 0
	C_UART_WIDTH = 8
	C_USE_FSL = 0
	C_USE_UART = 1

Analyzing hierarchy for entity <pselect> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 16
	C_AW = 32
	C_BAR = "10000100010000000000000000000000"

Analyzing hierarchy for entity <JTAG_CONTROL> in library <mdm_v1_00_g> (architecture <IMP>) with generics.
	C_EN_WIDTH = 1
	C_FSL_DATA_SIZE = 32
	C_MB_DBG_PORTS = 1
	C_UART_WIDTH = 8
	C_USE_FSL = 0
	C_USE_UART = 1

Analyzing hierarchy for entity <SRL_FIFO> in library <mdm_v1_00_g> (architecture <IMP>) with generics.
	C_DATA_BITS = 8
	C_DEPTH = 16

WARNING:Xst:2592 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/hdl/vhdl/jtag_control.vhd" line 565: generic/parameter on instance <INIT> overrides attribute on instance. Attribute is ignored.
WARNING:Xst:2592 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/hdl/vhdl/jtag_control.vhd" line 579: generic/parameter on instance <INIT> overrides attribute on instance. Attribute is ignored.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <mdm_0_wrapper> in library <work> (Architecture <STRUCTURE>).
Entity <mdm_0_wrapper> analyzed. Unit <mdm_0_wrapper> generated.

Analyzing generic Entity <mdm> in library <mdm_v1_00_g> (Architecture <IMP>).
	C_BASEADDR = "10000100010000000000000000000000"
	C_FAMILY = "spartan3e"
	C_HIGHADDR = "10000100010000001111111111111111"
	C_INTERCONNECT = 1
	C_JTAG_CHAIN = 2
	C_MB_DBG_PORTS = 1
	C_OPB_AWIDTH = 32
	C_OPB_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SUPPORT_BURSTS = 0
	C_UART_WIDTH = 8
	C_USE_UART = 1
	C_WRITE_FSL_PORTS = 0
    Set user-defined property "PERIOD =  200 ns" for signal <update>.
    Set property "buffer_type = none" for signal <update>.
    Set property "buffer_type = none" for signal <update_i>.
    Set user-defined property "buffer_type =  none" for instance <MDM_Core_I1> in unit <mdm>.
Entity <mdm> analyzed. Unit <mdm> generated.

Analyzing generic Entity <MDM_Core> in library <mdm_v1_00_g> (Architecture <IMP>).
	C_BASEADDR = "10000100010000000000000000000000"
	C_FSL_DATA_SIZE = 32
	C_HIGHADDR = "10000100010000001111111111111111"
	C_INTERCONNECT = 1
	C_MB_DBG_PORTS = 1
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SUPPORT_BURSTS = 0
	C_UART_WIDTH = 8
	C_USE_FSL = 0
	C_USE_UART = 1
    Set user-defined property "INIT =  0" for instance <PLB_Interconnect.TX_Buffer_Empty_FDRE> in unit <MDM_Core>.
    Set user-defined property "INIT =  0" for instance <PLB_Interconnect.PLBv46_rdDBus_DFF[24].PLBv46_rdBus_FDRE> in unit <MDM_Core>.
    Set user-defined property "INIT =  0" for instance <PLB_Interconnect.PLBv46_rdDBus_DFF[25].PLBv46_rdBus_FDRE> in unit <MDM_Core>.
    Set user-defined property "INIT =  0" for instance <PLB_Interconnect.PLBv46_rdDBus_DFF[26].PLBv46_rdBus_FDRE> in unit <MDM_Core>.
    Set user-defined property "INIT =  0" for instance <PLB_Interconnect.PLBv46_rdDBus_DFF[27].PLBv46_rdBus_FDRE> in unit <MDM_Core>.
    Set user-defined property "INIT =  0" for instance <PLB_Interconnect.PLBv46_rdDBus_DFF[28].PLBv46_rdBus_FDRE> in unit <MDM_Core>.
    Set user-defined property "INIT =  0" for instance <PLB_Interconnect.PLBv46_rdDBus_DFF[29].PLBv46_rdBus_FDRE> in unit <MDM_Core>.
    Set user-defined property "INIT =  0" for instance <PLB_Interconnect.PLBv46_rdDBus_DFF[30].PLBv46_rdBus_FDRE> in unit <MDM_Core>.
    Set user-defined property "INIT =  0" for instance <PLB_Interconnect.PLBv46_rdDBus_DFF[31].PLBv46_rdBus_FDRE> in unit <MDM_Core>.
Entity <MDM_Core> analyzed. Unit <MDM_Core> generated.

Analyzing generic Entity <pselect> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 16
	C_AW = 32
	C_BAR = "10000100010000000000000000000000"
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect.vhd" line 248: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect.vhd" line 248: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect.vhd" line 248: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect.vhd" line 248: Instantiating black box module <MUXCY>.
Entity <pselect> analyzed. Unit <pselect> generated.

Analyzing generic Entity <JTAG_CONTROL> in library <mdm_v1_00_g> (Architecture <IMP>).
	C_EN_WIDTH = 1
	C_FSL_DATA_SIZE = 32
	C_MB_DBG_PORTS = 1
	C_UART_WIDTH = 8
	C_USE_FSL = 0
	C_USE_UART = 1
    Set user-defined property "INIT =  0" for instance <FDC_I> in unit <JTAG_CONTROL>.
    Set user-defined property "KEEP =  TRUE" for signal <local_sel_n>.
    Set user-defined property "INIT =  0002" for instance <Insert_Delays[0].LUT_Delay> in unit <JTAG_CONTROL>.
    Set user-defined property "KEEP =  TRUE" for signal <local_sel_n0>.
    Set user-defined property "INIT =  0002" for instance <Insert_Delays[1].LUT_Delay> in unit <JTAG_CONTROL>.
    Set user-defined property "KEEP =  TRUE" for signal <local_sel_n1>.
    Set user-defined property "INIT =  0002" for instance <Insert_Delays[2].LUT_Delay> in unit <JTAG_CONTROL>.
    Set user-defined property "KEEP =  TRUE" for signal <local_sel_n2>.
    Set user-defined property "INIT =  0002" for instance <Insert_Delays[3].LUT_Delay> in unit <JTAG_CONTROL>.
    Set user-defined property "KEEP =  TRUE" for signal <local_sel_n3>.
    Set user-defined property "INIT =  0002" for instance <Insert_Delays[4].LUT_Delay> in unit <JTAG_CONTROL>.
    Set user-defined property "INIT =  0" for instance <SYNC_FDRE> in unit <JTAG_CONTROL>.
    Set user-defined property "INIT =  0105" for instance <SRL16E_1> in unit <JTAG_CONTROL>.
    Set user-defined property "INIT =  4227" for instance <SRL16E_2> in unit <JTAG_CONTROL>.
    Set user-defined property "INIT =  4443" for instance <SRL16E_ID_1> in unit <JTAG_CONTROL>.
    Set user-defined property "INIT =  584D" for instance <SRL16E_ID_2> in unit <JTAG_CONTROL>.
    Set user-defined property "INIT =  0" for instance <Ext_BRK_FDRSE> in unit <JTAG_CONTROL>.
Entity <JTAG_CONTROL> analyzed. Unit <JTAG_CONTROL> generated.

Analyzing generic Entity <SRL_FIFO> in library <mdm_v1_00_g> (Architecture <IMP>).
	C_DATA_BITS = 8
	C_DEPTH = 16
    Set user-defined property "INIT =  0" for instance <Addr_Counters[0].FDRE_I> in unit <SRL_FIFO>.
    Set user-defined property "INIT =  0" for instance <Addr_Counters[1].FDRE_I> in unit <SRL_FIFO>.
    Set user-defined property "INIT =  0" for instance <Addr_Counters[2].FDRE_I> in unit <SRL_FIFO>.
    Set user-defined property "INIT =  0" for instance <Addr_Counters[3].FDRE_I> in unit <SRL_FIFO>.
    Set user-defined property "INIT =  0000" for instance <FIFO_RAM[0].SRL16E_I> in unit <SRL_FIFO>.
    Set user-defined property "INIT =  0000" for instance <FIFO_RAM[1].SRL16E_I> in unit <SRL_FIFO>.
    Set user-defined property "INIT =  0000" for instance <FIFO_RAM[2].SRL16E_I> in unit <SRL_FIFO>.
    Set user-defined property "INIT =  0000" for instance <FIFO_RAM[3].SRL16E_I> in unit <SRL_FIFO>.
    Set user-defined property "INIT =  0000" for instance <FIFO_RAM[4].SRL16E_I> in unit <SRL_FIFO>.
    Set user-defined property "INIT =  0000" for instance <FIFO_RAM[5].SRL16E_I> in unit <SRL_FIFO>.
    Set user-defined property "INIT =  0000" for instance <FIFO_RAM[6].SRL16E_I> in unit <SRL_FIFO>.
    Set user-defined property "INIT =  0000" for instance <FIFO_RAM[7].SRL16E_I> in unit <SRL_FIFO>.
Entity <SRL_FIFO> analyzed. Unit <SRL_FIFO> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <pselect>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect.vhd".
WARNING:Xst:647 - Input <A<16:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <lut_out<4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <pselect> synthesized.


Synthesizing Unit <SRL_FIFO>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/hdl/vhdl/srl_fifo.vhd".
    Found 1-bit register for signal <data_Exists_I>.
    Found 1-bit xor2 for signal <hsum_A_0$xor0000> created at line 139.
    Found 1-bit xor2 for signal <hsum_A_1$xor0000> created at line 139.
    Found 1-bit xor2 for signal <hsum_A_2$xor0000> created at line 139.
    Found 1-bit xor2 for signal <hsum_A_3$xor0000> created at line 139.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <SRL_FIFO> synthesized.


Synthesizing Unit <JTAG_CONTROL>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/hdl/vhdl/jtag_control.vhd".
WARNING:Xst:647 - Input <FSL0_S_Control> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FSL0_S_Data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <sync_word_shift> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sync_word> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <load_Command> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fifo_Din<31>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <New_FSL_Data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found 5-bit register for signal <command>.
    Found 5-bit register for signal <command_1>.
    Found 1-bit register for signal <Debug_Rst_i>.
    Found 1-bit register for signal <Debug_SYS_Rst_i>.
    Found 1-bit register for signal <execute>.
    Found 1-bit register for signal <execute_1>.
    Found 1-bit register for signal <execute_2>.
    Found 1-bit register for signal <Ext_NM_BRK_i>.
    Found 8-bit register for signal <fifo_Din<0:7>>.
    Found 1-bit register for signal <fifo_Read>.
    Found 1-bit register for signal <fifo_Write>.
    Found 1-bit register for signal <set_Ext_BRK>.
    Found 5-bit up counter for signal <shift_Count>.
    Found 8-bit register for signal <tdi_shifter>.
    Found 8-bit register for signal <tdo_reg>.
    Summary:
	inferred   1 Counter(s).
	inferred  43 D-type flip-flop(s).
Unit <JTAG_CONTROL> synthesized.


Synthesizing Unit <MDM_Core>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/hdl/vhdl/mdm_core.vhd".
WARNING:Xst:1305 - Output <MDM_toutSup> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <PLB_wrPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_MSize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <MDM_errAck> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <PLB_rdBurst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <MDM_xferAck> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <PLB_masterID<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_SAValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <OPB_BE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <OPB_Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_UABus> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <OPB_RNW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_busLock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <OPB_Rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrDBus<0:23>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_BE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_reqPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_lockErr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrBurst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_TAttribute> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <OPB_DBus> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <MDM_retry> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <OPB_select> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <MDM_DBus> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:647 - Input <PLB_abort> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <OPB_ABus> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_type> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <OPB_seqAddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <xfer_Ack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <opb_RNW_1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mdm_Dbus_i<0:23>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mdm_CS_3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mdm_CS_2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mdm_CS_1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <JTAG_Dec_Sel> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Dbg_TDO_I<1:7>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Dbg_TDI_I> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <Dbg_Rst_I<1:7>> is used but never assigned. This sourceless signal will be automatically connected to value 0000000.
WARNING:Xst:1781 - Signal <Dbg_Reg_En_I<1:7>> is used but never assigned. Tied to default value.
    Register <valid_access_1> equivalent to <Sl_addrAck> has been removed
    Found 1-bit register for signal <Sl_addrAck>.
    Found 2-bit register for signal <abus>.
    Found 1-bit register for signal <clear_Ext_BRK>.
    Found 32-bit register for signal <Config_Reg>.
    Found 1-bit register for signal <enable_interrupts>.
    Found 4-bit register for signal <PORT_Selector>.
    Found 4-bit register for signal <PORT_Selector_1>.
    Found 1-bit register for signal <reading>.
    Found 1-bit register for signal <reset_RX_FIFO>.
    Found 1-bit register for signal <reset_TX_FIFO>.
    Found 1-bit register for signal <sl_rdDAck_i>.
    Found 1-bit register for signal <sl_wrDAck_i>.
    Found 4-bit register for signal <TDI_Shifter>.
    Found 1-bit register for signal <valid_access_2>.
    Summary:
	inferred  23 D-type flip-flop(s).
Unit <MDM_Core> synthesized.


Synthesizing Unit <mdm>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/hdl/vhdl/mdm.vhd".
Unit <mdm> synthesized.


Synthesizing Unit <mdm_0_wrapper>.
    Related source file is "C:/Temp/Bomberman/hdl/mdm_0_wrapper.vhd".
Unit <mdm_0_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 5-bit up counter                                      : 1
# Registers                                            : 37
 1-bit register                                        : 28
 2-bit register                                        : 1
 32-bit register                                       : 1
 4-bit register                                        : 3
 5-bit register                                        : 2
 8-bit register                                        : 2
# Xors                                                 : 8
 1-bit xor2                                            : 8

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 5-bit up counter                                      : 1
# Registers                                            : 120
 Flip-Flops                                            : 120
# Xors                                                 : 8
 1-bit xor2                                            : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch <Config_Reg_31> has a constant value of 0 in block <MDM_Core>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <mdm_0_wrapper> ...

Optimizing unit <pselect> ...

Optimizing unit <SRL_FIFO> ...

Optimizing unit <JTAG_CONTROL> ...

Optimizing unit <MDM_Core> ...

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

Processing Unit <mdm_0/MDM_Core_I1> :
	Found 4-bit shift register for signal <Config_Reg_26>.
	Found 15-bit shift register for signal <Config_Reg_10>.
	Found 6-bit shift register for signal <Config_Reg_3>.
Unit <mdm_0/MDM_Core_I1> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 99
 Flip-Flops                                            : 99
# Shift Registers                                      : 3
 15-bit shift register                                 : 1
 4-bit shift register                                  : 1
 6-bit shift register                                  : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/mdm_0_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 498

Cell Usage :
# BELS                             : 151
#      GND                         : 1
#      INV                         : 5
#      LUT2                        : 18
#      LUT3                        : 34
#      LUT4                        : 67
#      MUXCY                       : 4
#      MUXCY_L                     : 6
#      MUXF5                       : 7
#      VCC                         : 1
#      XORCY                       : 8
# FlipFlops/Latches                : 119
#      FD                          : 5
#      FDC                         : 21
#      FDC_1                       : 5
#      FDCE                        : 8
#      FDE                         : 34
#      FDE_1                       : 5
#      FDP                         : 5
#      FDR                         : 12
#      FDRE                        : 20
#      FDRE_1                      : 1
#      FDRSE                       : 1
#      FDS                         : 2
# Shift Registers                  : 23
#      SRL16                       : 3
#      SRL16E                      : 20
# Clock Buffers                    : 2
#      BUFG                        : 2
# Others                           : 1
#      BSCAN_SPARTAN3              : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                       88  out of   8672     1%  
 Number of Slice Flip Flops:            119  out of  17344     0%  
 Number of 4 input LUTs:                147  out of  17344     0%  
    Number used as logic:               124
    Number used as Shift registers:      23
 Number of IOs:                         498
 Number of bonded IOBs:                   0  out of    250     0%  
 Number of GCLKs:                         2  out of     24     8%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                                  | Load  |
-----------------------------------+------------------------------------------------------------------------+-------+
mdm_0/update                       | NONE(mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/Debug_SYS_Rst_i)| 24    |
SPLB_Clk                           | NONE(mdm_0/MDM_Core_I1/abus_1)                                         | 51    |
mdm_0/drck_i                       | BUFG                                                                   | 67    |
-----------------------------------+------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+
Control Signal                                                                                                                                | Buffer(FF name)                                                                           | Load  |
----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+
mdm_0/MDM_Core_I1/Config_Reg_Acst_inv(mdm_0/MDM_Core_I1/Config_Reg_Acst_inv1_INV_0:O)                                                         | NONE(mdm_0/MDM_Core_I1/Config_Reg_0)                                                      | 23    |
mdm_0/MDM_Core_I1/SEL_inv(mdm_0/MDM_Core_I1/SEL_inv1_INV_0:O)                                                                                 | NONE(mdm_0/MDM_Core_I1/PORT_Selector_0)                                                   | 12    |
mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/data_cmd_inv(mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/data_cmd_inv1_INV_0:O)       | NONE(mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/execute)                           | 1     |
mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/local_sel_n3(mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/Insert_Delays[4].LUT_Delay:O)| NONE(mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/FDC_I)                             | 1     |
mdm_0/MDM_Core_I1/reset_RX_FIFO(mdm_0/MDM_Core_I1/reset_RX_FIFO:Q)                                                                            | NONE(mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I)| 1     |
mdm_0/MDM_Core_I1/reset_TX_FIFO(mdm_0/MDM_Core_I1/reset_TX_FIFO:Q)                                                                            | NONE(mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/Have_UARTs.TX_FIFO_I/data_Exists_I)| 1     |
----------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 9.624ns (Maximum Frequency: 103.907MHz)
   Minimum input arrival time before clock: 5.981ns
   Maximum output required time after clock: 8.074ns
   Maximum combinational path delay: 2.817ns

=========================================================================
Timing constraint: NET mdm_0/update PERIOD = 200 nS HIGH 100 nS
  Clock period: 9.624ns (frequency: 103.907MHz)
  Total number of paths / destination ports: 99 / 29
  Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
-------------------------------------------------------------------------
Slack:                  190.376ns
  Source:               mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/command_2 (FF)
  Destination:          mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/Debug_SYS_Rst_i (FF)
  Data Path Delay:      4.812ns (Levels of Logic = 2)
  Source Clock:         mdm_0/update falling at 100.000ns
  Destination Clock:    mdm_0/update rising at 200.000ns

  Data Path: mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/command_2 (FF) to mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/Debug_SYS_Rst_i (FF)
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE_1:C->Q           12   0.591   1.136  PLB_Interconnect.JTAG_CONTROL_I/command_2 (PLB_Interconnect.JTAG_CONTROL_I/command_2)
     LUT3:I0->O            3   0.704   0.535  PLB_Interconnect.JTAG_CONTROL_I/TDO31 (PLB_Interconnect.JTAG_CONTROL_I/N6)
     LUT4:I3->O            4   0.704   0.587  PLB_Interconnect.JTAG_CONTROL_I/Debug_SYS_Rst_i_and00001 (PLB_Interconnect.JTAG_CONTROL_I/Debug_SYS_Rst_i_and0000)
     FDE:CE                    0.555          PLB_Interconnect.JTAG_CONTROL_I/Debug_SYS_Rst_i
    ----------------------------------------
    Total                      4.812ns (2.554ns logic, 2.258ns route)
                                       (53.1% logic, 46.9% route)

=========================================================================


Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 14.09 secs
 
--> 

Total memory usage is 175032 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   63 (   0 filtered)
Number of infos    :    1 (   0 filtered)

