Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "lmb_bram_wrapper_xst.prj"
Verilog Include Directory          : {"C:\Temp\Bomberman\pcores\" "C:\Xilinx\12.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc3s1200efg320-4
Output File Name                   : "../implementation/lmb_bram_wrapper.ngc"

---- Source Options
Top Module Name                    : lmb_bram_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation/lmb_bram_wrapper}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" in Library lmb_bram_elaborate_v1_00_a.
Entity <lmb_bram_elaborate> compiled.
Entity <lmb_bram_elaborate> (Architecture <STRUCTURE>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/hdl/lmb_bram_wrapper.vhd" in Library work.
Entity <lmb_bram_wrapper> compiled.
Entity <lmb_bram_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <lmb_bram_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <lmb_bram_elaborate> in library <lmb_bram_elaborate_v1_00_a> (architecture <STRUCTURE>) with generics.
	C_FAMILY = "spartan3e"
	C_MEMSIZE = 32768
	C_NUM_WE = 4
	C_PORT_AWIDTH = 32
	C_PORT_DWIDTH = 32


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lmb_bram_wrapper> in library <work> (Architecture <STRUCTURE>).
    Set user-defined property "KEEP_HIERARCHY =  yes" for unit <lmb_bram_wrapper>.
    Set user-defined property "KEEP_HIERARCHY =  yes" for unit <lmb_bram_elaborate>.
Entity <lmb_bram_wrapper> analyzed. Unit <lmb_bram_wrapper> generated.

Analyzing generic Entity <lmb_bram_elaborate> in library <lmb_bram_elaborate_v1_00_a> (Architecture <STRUCTURE>).
	C_FAMILY = "spartan3e"
	C_MEMSIZE = 32768
	C_NUM_WE = 4
	C_PORT_AWIDTH = 32
	C_PORT_DWIDTH = 32
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 81: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_0> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_0> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 103: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_1> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_1> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 125: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_2> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_2> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 147: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_3> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_3> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 169: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_4> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_4> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 191: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_5> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_5> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 213: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_6> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_6> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 235: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_7> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_7> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 257: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_8> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_8> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 279: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_9> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_9> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 301: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_10> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_10> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 323: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_11> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_11> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 345: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_12> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_12> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 367: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_13> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_13> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 389: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_14> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_14> in unit <lmb_bram_elaborate>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd" line 411: Instantiating black box module <RAMB16_S2_S2>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ramb16_s2_s2_15> in unit <lmb_bram_elaborate>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ramb16_s2_s2_15> in unit <lmb_bram_elaborate>.
Entity <lmb_bram_elaborate> analyzed. Unit <lmb_bram_elaborate> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <lmb_bram_elaborate>.
    Related source file is "C:/Temp/Bomberman/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl/lmb_bram_elaborate.vhd".
WARNING:Xst:647 - Input <BRAM_Addr_A<0:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BRAM_Addr_A<30:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BRAM_Addr_B<0:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BRAM_Addr_B<30:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <lmb_bram_elaborate> synthesized.


Synthesizing Unit <lmb_bram_wrapper>.
    Related source file is "C:/Temp/Bomberman/hdl/lmb_bram_wrapper.vhd".
Unit <lmb_bram_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <lmb_bram_wrapper> ...

Optimizing unit <lmb_bram_elaborate> ...

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/lmb_bram_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 206

Cell Usage :
# RAMS                             : 16
#      RAMB16_S2_S2                : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                        0  out of   8672     0%  
 Number of IOs:                         206
 Number of bonded IOBs:                   0  out of    250     0%  
 Number of BRAMs:                        16  out of     28    57%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)        | Load  |
-----------------------------------+------------------------------+-------+
BRAM_Clk_A                         | NONE(lmb_bram/ramb16_s2_s2_0)| 16    |
BRAM_Clk_B                         | NONE(lmb_bram/ramb16_s2_s2_0)| 16    |
-----------------------------------+------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: 1.253ns
   Maximum output required time after clock: 2.800ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'BRAM_Clk_A'
  Total number of paths / destination ports: 288 / 288
-------------------------------------------------------------------------
Offset:              1.253ns (Levels of Logic = 1)
  Source:            BRAM_WEN_A<0> (PAD)
  Destination:       lmb_bram/ramb16_s2_s2_0 (RAM)
  Destination Clock: BRAM_Clk_A rising

  Data Path: BRAM_WEN_A<0> to lmb_bram/ramb16_s2_s2_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     begin scope: 'lmb_bram'
     RAMB16_S2_S2:WEA          1.253          ramb16_s2_s2_0
    ----------------------------------------
    Total                      1.253ns (1.253ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'BRAM_Clk_B'
  Total number of paths / destination ports: 288 / 288
-------------------------------------------------------------------------
Offset:              1.253ns (Levels of Logic = 1)
  Source:            BRAM_WEN_B<0> (PAD)
  Destination:       lmb_bram/ramb16_s2_s2_0 (RAM)
  Destination Clock: BRAM_Clk_B rising

  Data Path: BRAM_WEN_B<0> to lmb_bram/ramb16_s2_s2_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     begin scope: 'lmb_bram'
     RAMB16_S2_S2:WEB          1.253          ramb16_s2_s2_0
    ----------------------------------------
    Total                      1.253ns (1.253ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'BRAM_Clk_B'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              2.800ns (Levels of Logic = 1)
  Source:            lmb_bram/ramb16_s2_s2_0 (RAM)
  Destination:       BRAM_Din_B<0> (PAD)
  Source Clock:      BRAM_Clk_B rising

  Data Path: lmb_bram/ramb16_s2_s2_0 to BRAM_Din_B<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S2_S2:CLKB->DOB1    0   2.800   0.000  ramb16_s2_s2_0 (BRAM_Din_B<0>)
     end scope: 'lmb_bram'
    ----------------------------------------
    Total                      2.800ns (2.800ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'BRAM_Clk_A'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              2.800ns (Levels of Logic = 1)
  Source:            lmb_bram/ramb16_s2_s2_0 (RAM)
  Destination:       BRAM_Din_A<0> (PAD)
  Source Clock:      BRAM_Clk_A rising

  Data Path: lmb_bram/ramb16_s2_s2_0 to BRAM_Din_A<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16_S2_S2:CLKA->DOA1    0   2.800   0.000  ramb16_s2_s2_0 (BRAM_Din_A<0>)
     end scope: 'lmb_bram'
    ----------------------------------------
    Total                      2.800ns (2.800ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 6.13 secs
 
--> 

Total memory usage is 138168 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   20 (   0 filtered)
Number of infos    :    1 (   0 filtered)

