------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.            **
-- **                                                                       **
-- ** Xilinx, Inc.                                                          **
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-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
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-- ** FOR A PARTICULAR PURPOSE.                                             **
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-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename:          user_logic.vhd
-- Version:           1.00.a
-- Description:       User logic.
-- Date:              Mon Sep 12 15:41:52 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard:     VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
--   active low signals:                    "*_n"
--   clock signals:                         "clk", "clk_div#", "clk_#x"
--   reset signals:                         "rst", "rst_n"
--   generics:                              "C_*"
--   user defined types:                    "*_TYPE"
--   state machine next state:              "*_ns"
--   state machine current state:           "*_cs"
--   combinatorial signals:                 "*_com"
--   pipelined or register delay signals:   "*_d#"
--   counter signals:                       "*cnt*"
--   clock enable signals:                  "*_ce"
--   internal version of output port:       "*_i"
--   device pins:                           "*_pin"
--   ports:                                 "- Names begin with Uppercase"
--   processes:                             "*_PROCESS"
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;

-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here
library graph_acc_v1_00_a;
use graph_acc_v1_00_a.vga_controller_640_60;
use graph_acc_v1_00_a.BRAM_bomb;
use graph_acc_v1_00_a.BRAM_p1;
use graph_acc_v1_00_a.BRAM_p2;
use graph_acc_v1_00_a.BRAM_stone;
use graph_acc_v1_00_a.BRAM_brick;
use graph_acc_v1_00_a.BRAM_fire_end;
use graph_acc_v1_00_a.BRAM_fire_line;
use graph_acc_v1_00_a.BRAM_fire_centre;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_SLV_DWIDTH                 -- Slave interface data bus width
--   C_NUM_REG                    -- Number of software accessible registers
--
-- Definition of Ports:
--   Bus2IP_Clk                   -- Bus to IP clock
--   Bus2IP_Reset                 -- Bus to IP reset
--   Bus2IP_Data                  -- Bus to IP data bus
--   Bus2IP_BE                    -- Bus to IP byte enables
--   Bus2IP_RdCE                  -- Bus to IP read chip enable
--   Bus2IP_WrCE                  -- Bus to IP write chip enable
--   IP2Bus_Data                  -- IP to Bus data bus
--   IP2Bus_RdAck                 -- IP to Bus read transfer acknowledgement
--   IP2Bus_WrAck                 -- IP to Bus write transfer acknowledgement
--   IP2Bus_Error                 -- IP to Bus error response
------------------------------------------------------------------------------

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_SLV_DWIDTH                   : integer              := 32;
    C_NUM_REG                      : integer              := 4
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
	HS					: out std_logic;
	VS					: out std_logic;
	VGA_rgb				: out std_logic_vector(0 to 7);
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Reset                   : in  std_logic;
    Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
    Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
    IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
    IP2Bus_RdAck                   : out std_logic;
    IP2Bus_WrAck                   : out std_logic;
    IP2Bus_Error                   : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );

  attribute SIGIS : string;
  attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
  attribute SIGIS of Bus2IP_Reset  : signal is "RST";

end entity user_logic;


------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

	component vga_controller_640_60 is
	port(
   		rst         : in std_logic;
   		pixel_clk   : in std_logic;

   		HS          : out std_logic;
   		VS          : out std_logic;
   		hcount      : out std_logic_vector(10 downto 0);
   		vcount      : out std_logic_vector(10 downto 0);
   		blank       : out std_logic);

	end component;
	
	component BRAM_bomb is
	port (clka: IN std_logic;
			addra: IN std_logic_VECTOR(9 downto 0);
			douta: OUT std_logic_VECTOR(7 downto 0));
	end component;

	component BRAM_p1 is
	port (clka: IN std_logic;
			addra: IN std_logic_VECTOR(9 downto 0);
			douta: OUT std_logic_VECTOR(7 downto 0));
	end component;

	component BRAM_p2 is
	port (clka: IN std_logic;
			addra: IN std_logic_VECTOR(9 downto 0);
			douta: OUT std_logic_VECTOR(7 downto 0));
	end component;

	component BRAM_stone is
	port (clka: IN std_logic;
			addra: IN std_logic_VECTOR(9 downto 0);
			douta: OUT std_logic_VECTOR(7 downto 0));
	end component;

	component BRAM_brick is
	port (clka: IN std_logic;
			addra: IN std_logic_VECTOR(9 downto 0);
			douta: OUT std_logic_VECTOR(7 downto 0));
	end component;

	component BRAM_fire_end is
	port (clka: IN std_logic;
			addra: IN std_logic_VECTOR(9 downto 0);
			douta: OUT std_logic_VECTOR(7 downto 0));
	end component;
	
	component BRAM_fire_line is
	port (clka: IN std_logic;
			addra: IN std_logic_VECTOR(9 downto 0);
			douta: OUT std_logic_VECTOR(7 downto 0));
	end component;

	component BRAM_fire_centre is
	port (clka: IN std_logic;
			addra: IN std_logic_VECTOR(9 downto 0);
			douta: OUT std_logic_VECTOR(7 downto 0));
	end component;

--	component clock_gen is
--		port ( 	 clkin_in 			     	: in  std_logic;
--				 rst_in 				: in  std_logic;          
--				 clkdv_out 			    	: out std_logic;
--				 clkin_ibufg_out 			: out std_logic;
--				 clk0_out 			    	: out std_logic;
--				 locked_out 		    	: out std_logic);
--	end component;

  --USER signal declarations added here, as needed for user logic

----------------------------------------
-- Memory Signals
----------------------------------------
signal bram_square_addr : std_logic_vector(9 downto 0);
signal bram_p1_addr : std_logic_vector(9 downto 0);
signal bram_p2_addr : std_logic_vector(9 downto 0);

signal bram_bomb_dout : std_logic_vector(7 downto 0);
signal bram_p1_dout : std_logic_vector(7 downto 0);
signal bram_p2_dout : std_logic_vector(7 downto 0);
signal bram_stone_dout : std_logic_vector(7 downto 0);
signal bram_brick_dout : std_logic_vector(7 downto 0);
signal bram_fire_end_dout : std_logic_vector(7 downto 0);
signal bram_fire_line_dout : std_logic_vector(7 downto 0);
signal bram_fire_centre_dout : std_logic_vector(7 downto 0);

signal pixel_clk : std_logic;
signal clk_locked : std_logic;
signal hcount,vcount : std_logic_vector(10 downto 0);
signal blank : std_logic;
signal clock_dev_1, clock_dev_2 : std_logic;
signal VGA_out,VGA_keep : std_logic_vector(0 to 7);
subtype element is std_logic_vector(3 downto 0);
type board is array(integer range 0 to 15,integer range 0 to 15) of element;
signal gameboard,gb_keep : board;
signal p1h,p2h,p1h_keep,p2h_keep : std_logic_vector(9 downto 0);
signal p1v,p2v,p1v_keep,p2v_keep : std_logic_vector(8 downto 0);

  ------------------------------------------
  -- Signals for user logic slave model s/w accessible register example
  ------------------------------------------
  signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg1                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg2                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg3                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_reg_write_sel              : std_logic_vector(0 to 3);
  signal slv_reg_read_sel               : std_logic_vector(0 to 3);
  signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
  signal slv_read_ack                   : std_logic;
  signal slv_write_ack                  : std_logic;

begin

Bomb : BRAM_bomb
	port map (
		clka	=> Bus2IP_Clk,
		addra => bram_square_addr,
		douta =>bram_bomb_dout);
  
p1 : BRAM_p1
	port map (
		clka	=> Bus2IP_Clk,
		addra => bram_square_addr,
		douta => bram_p1_dout);

p2 : BRAM_p2
	port map (
		clka	=> Bus2IP_Clk,
		addra => bram_square_addr,
		douta => bram_p2_dout);
		
stone : BRAM_stone
	port map (
		clka	=> Bus2IP_Clk,
		addra => bram_square_addr,
		douta => bram_stone_dout);
		
brick : BRAM_brick
	port map (
		clka	=> Bus2IP_Clk,
		addra => bram_square_addr,
		douta => bram_brick_dout);

fire_end : BRAM_fire_end
	port map (
		clka	=> Bus2IP_Clk,
		addra => bram_square_addr,
		douta => bram_fire_end_dout);

fire_line : BRAM_fire_line
	port map (
		clka	=> Bus2IP_Clk,
		addra => bram_square_addr,
		douta => bram_fire_line_dout);
		
fire_centre : BRAM_fire_centre
	port map (
		clka	=> Bus2IP_Clk,
		addra => bram_square_addr,
		douta => bram_fire_centre_dout);

VGA_ctrl : vga_controller_640_60
	port map(
		rst         => Bus2IP_Reset,
   	pixel_clk   => Bus2IP_Clk,
		HS          => HS,
		VS          => VS,
		hcount      => hcount,
   	vcount      => vcount,
   	blank			=> blank);
		
--Inst_clkgen : clock_gen
--	port map (  clkin_in 			=> Bus2IP_Clk,
--			rst_in 			=> '0',			-- Don't touch! active high reset
--			clkdv_out 		=> pixel_clk,		-- Divided 50MHz input clock
--			clkin_ibufg_out => open,
--			clk0_out 			=> open,
--			locked_out 		=> clk_locked	-- Clock stable signal, active high
--			);

--USER logic implementation added here
memory_access : process(vcount,hcount)
begin
	bram_square_addr <= vcount(4 downto 0) & hcount(5 downto 1);
	bram_p1_addr <= (vcount(4 downto 0) - p1v(4 downto 0)) & (hcount(5 downto 1) - p1h(4 downto 0));
	bram_p2_addr <= (vcount(4 downto 0) - p2v(4 downto 0)) & (hcount(5 downto 1) - p2h(4 downto 0));
end process;


rendering_comb : process(vcount,hcount,VGA_keep,gameboard)
	begin
	VGA_out <= VGA_keep;
 	if (vcount(8 downto 5) > "0001" AND vcount(8 downto 5) < "1101") then
		if (hcount(10 downto 6) > "00010" AND hcount(10 downto 6) < "10000") then
			if ((p1h >= hcount(10 downto 1)) AND (p1h < (hcount(10 downto 1) + 32)) AND (p1v >= vcount(9 downto 0)) AND (p1v < (vcount(9 downto 0) + 32))) then
				if (bram_p1_dout /= "00000010") then
					VGA_out <= bram_p1_dout;
				else
					case (gameboard(conv_integer(vcount(8 downto 5)),conv_integer(hcount(9 downto 6)))) is
					when "0001" => VGA_out <= "00010000";
					when "0010" =>	VGA_out <= bram_stone_dout;
					when "0011" => VGA_out <= bram_brick_dout;
					when "0100" => VGA_out <= bram_bomb_dout;
					when "0101" => VGA_out <= bram_fire_centre_dout;
					when "0110" => VGA_out <= bram_fire_line_dout;
					when "0111" => VGA_out <= bram_fire_line_dout;
					when "1000" => VGA_out <= bram_fire_end_dout;
					when "1001" => VGA_out <= bram_fire_end_dout;
					when "1010" => VGA_out <= bram_fire_end_dout;
					when "1011" => VGA_out <= bram_fire_end_dout;
					when "1100" =>
						if (bram_fire_line_dout = "00000010") then
							VGA_out <= bram_brick_dout;
						else
							VGA_out <= bram_fire_end_dout;
						end if;
					when "1101" =>
						if (bram_fire_line_dout = "00000010") then
							VGA_out <= bram_brick_dout;
						else
							VGA_out <= bram_fire_end_dout;
						end if;
					when "1110" =>
						if (bram_fire_line_dout = "00000010") then
							VGA_out <= bram_brick_dout;
						else
							VGA_out <= bram_fire_end_dout;
						end if;
					when "1111" =>
						if (bram_fire_line_dout = "00000010") then
							VGA_out <= bram_brick_dout;
						else
							VGA_out <= bram_fire_end_dout;
						end if;
					when others => VGA_out <= "10010010";
					end case;
				end if;
			else
				if ((p2h >= hcount(10 downto 1)) AND (p2h < (hcount(10 downto 1) + 32)) AND (p2v >= vcount(9 downto 0)) AND (p2v < (vcount(9 downto 0) + 32))) then
				if (bram_p2_dout /= "00000010") then
					VGA_out <= bram_p2_dout;
					else
						case (gameboard(conv_integer(vcount(8 downto 5)),conv_integer(hcount(9 downto 6)))) is
						when "0001" => VGA_out <= "00010000";
						when "0010" =>	VGA_out <= bram_stone_dout;
						when "0011" => VGA_out <= bram_brick_dout;
						when "0100" => VGA_out <= bram_bomb_dout;
						when "0101" => VGA_out <= bram_fire_centre_dout;
						when "0110" => VGA_out <= bram_fire_line_dout;
						when "0111" => VGA_out <= bram_fire_end_dout;
						when others => VGA_out <= "10010010";
						end case;
					end if;
				else
					--sending board info
					case (gameboard(conv_integer(vcount(8 downto 5)),conv_integer(hcount(9 downto 6)))) is
					when "0001" => VGA_out <= "00010000";
					when "0010" =>	VGA_out <= bram_stone_dout;
					when "0011" => VGA_out <= bram_brick_dout;
					when "0100" => VGA_out <= bram_bomb_dout;
					when "0101" => VGA_out <= bram_fire_centre_dout;
					when "0110" => VGA_out <= bram_fire_line_dout;
					when "0111" => VGA_out <= bram_fire_end_dout;
					when others => VGA_out <= "10010010";
					end case;
				end if;
			end if;
		else
			VGA_out <= "00100101";
		end if;
	else
		VGA_out <= "00100101";
	end if;
end process rendering_comb;

 pixel_in: process(Bus2IP_Clk,blank)--hcount,vcount,NC,CS)
    begin
		if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
			VGA_keep <= VGA_out;
			gb_keep <= gameboard;
			p1h_keep <= p1h;
			p2h_keep <= p2h;
			p1v_keep <= p1v;
			p2v_keep <= p2v;
			if (blank = '0') then
			  VGA_rgb <= VGA_out;
			else
			  VGA_rgb <= "00000000";
			end if;      
		end if;
      
    end process pixel_in;

cpu_input : process(slv_reg0)
	begin
	gameboard <= gb_keep;
	p1h <= p1h_keep;
	p2h <= p2h_keep;
	p1v <= p1v_keep;
	p2v <= p2v_keep;
	if slv_reg0(0) = '1' then
		if slv_reg0(1) = '1' then
			p1h <= slv_reg0(10 to 19);-- "0011000000";
			p1v <= slv_reg0(23 to 31);-- "001100000";
		else
			p2h <= slv_reg0(10 to 19);-- "0011000000";
			p2v <= slv_reg0(23 to 31);-- "001100000";
		end if;
	else
		--board info 1
		gameboard(conv_integer(slv_reg0(20 to 23)),conv_integer(slv_reg0(24 to 27))) <= slv_reg0(28 to 31);
		--board info 2
		if (slv_reg0(1) = '1') then
			gameboard(conv_integer(slv_reg0(8 to 11)),conv_integer(slv_reg0(12 to 15))) <= slv_reg0(16 to 19);
		end if;
	end if;
end process cpu_input;

  ------------------------------------------
  -- Example code to read/write user logic slave model s/w accessible registers
  -- 
  -- Note:
  -- The example code presented here is to show you one way of reading/writing
  -- software accessible registers implemented in the user logic slave model.
  -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  -- to one software accessible register by the top level template. For example,
  -- if you have four 32 bit software accessible registers in the user logic,
  -- you are basically operating on the following memory mapped registers:
  -- 
  --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
  --                     "1000"   C_BASEADDR + 0x0
  --                     "0100"   C_BASEADDR + 0x4
  --                     "0010"   C_BASEADDR + 0x8
  --                     "0001"   C_BASEADDR + 0xC
  -- 
  ------------------------------------------
  slv_reg_write_sel <= Bus2IP_WrCE(0 to 3);
  slv_reg_read_sel  <= Bus2IP_RdCE(0 to 3);
  slv_write_ack     <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3);
  slv_read_ack      <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3);

  -- implement slave model software accessible register(s)
 
slv_reg_write : process (Bus2IP_Clk) is
begin
	if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
      if Bus2IP_Reset = '1' then
        slv_reg0 <= (others => '0');
        slv_reg1 <= (others => '0');
        slv_reg2 <= (others => '0');
        slv_reg3 <= (others => '0');
      else
			if slv_reg_write_sel = "1000" AND Bus2IP_BE = "1111" then
				slv_reg0 <= Bus2IP_Data;
			end if;
		end if;
	end if;

end process slv_reg_write;
  
--  SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
--  begin
--
--    if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
--      if Bus2IP_Reset = '1' then
--        slv_reg0 <= (others => '0');
--        slv_reg1 <= (others => '0');
--        slv_reg2 <= (others => '0');
--        slv_reg3 <= (others => '0');
--      else
--        case slv_reg_write_sel is
--          when "1000" =>
--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
--              end if;
--            end loop;
--          when "0100" =>
--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
--              end if;
--            end loop;
--          when "0010" =>
--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
--              end if;
--            end loop;
--          when "0001" =>
--            for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--              if ( Bus2IP_BE(byte_index) = '1' ) then
--                slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
--              end if;
--            end loop;
--          when others => null;
--        end case;
--      end if;
--    end if;
--
--  end process SLAVE_REG_WRITE_PROC;

  -- implement slave model software accessible register(s) read mux
  SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3 ) is
  begin

    case slv_reg_read_sel is
      when "1000" => slv_ip2bus_data <= slv_reg0;
      when "0100" => slv_ip2bus_data <= slv_reg1;
      when "0010" => slv_ip2bus_data <= slv_reg1 + slv_reg0;
      when "0001" => slv_ip2bus_data <= slv_reg1 - slv_reg0;
      when others => slv_ip2bus_data <= (others => '0');
    end case;

  end process SLAVE_REG_READ_PROC;

  ------------------------------------------
  -- Example code to drive IP to Bus signals
  ------------------------------------------
  IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
                  (others => '0');

  IP2Bus_WrAck <= slv_write_ack;
  IP2Bus_RdAck <= slv_read_ack;
  IP2Bus_Error <= '0';

end IMP;
