Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "xps_ps2_0_wrapper_xst.prj"
Verilog Include Directory          : {"C:\Temp\Bomberman\pcores\" "C:\Xilinx\12.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc3s1200efg320-4
Output File Name                   : "../implementation/xps_ps2_0_wrapper.ngc"

---- Source Options
Top Module Name                    : xps_ps2_0_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation/xps_ps2_0_wrapper}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/inferred_lut4.vhd" in Library proc_common_v3_00_a.
Entity <inferred_lut4> compiled.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/muxf_struct_f.vhd" in Library proc_common_v3_00_a.
Entity <muxf_struct> compiled.
Entity <muxf_struct> (Architecture <imp>) compiled.
Entity <muxf_struct_f> compiled.
Entity <muxf_struct_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_bit> compiled.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/cntr_incr_decr_addn_f.vhd" in Library proc_common_v3_00_a.
Entity <cntr_incr_decr_addn_f> compiled.
Entity <cntr_incr_decr_addn_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_f> compiled.
Entity <dynshreg_f> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_adder_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder_bit> compiled.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter> compiled.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_occ_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter> compiled.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <counter_bit> compiled.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy_f.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy_f> compiled.
Entity <or_muxcy_f> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu_f> compiled.
Entity <srl_fifo_rbu_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family.vhd" in Library proc_common_v3_00_a.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_occ_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter_top> compiled.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_top> compiled.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_adder.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder> compiled.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter.vhd" in Library proc_common_v3_00_a.
Entity <Counter> compiled.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/coregen_comp_defs.vhd" in Library proc_common_v3_00_a.
Package <coregen_comp_defs> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/common_types_pkg.vhd" in Library proc_common_v3_00_a.
Package <Common_Types> compiled.
WARNING:HDLParsers:3534 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/common_types_pkg.vhd" Line 223. In the function Get_RLOC_Name, not all control paths contain a return statement.
Package body <Common_Types> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/conv_funs_pkg.vhd" in Library proc_common_v3_00_a.
Package <conv_funs_pkg> compiled.
Package body <conv_funs_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/async_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <async_fifo_fg> compiled.
Entity <async_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/sync_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <sync_fifo_fg> compiled.
Entity <sync_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/blk_mem_gen_wrapper.vhd" in Library proc_common_v3_00_a.
Entity <blk_mem_gen_wrapper> compiled.
Entity <blk_mem_gen_wrapper> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/addsub.vhd" in Library proc_common_v3_00_a.
Entity <addsub> compiled.
Entity <addsub> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/direct_path_cntr.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr> compiled.
Entity <direct_path_cntr> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/direct_path_cntr_ai.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr_ai> compiled.
Entity <direct_path_cntr_ai> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/down_counter.vhd" in Library proc_common_v3_00_a.
Entity <down_counter> compiled.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/eval_timer.vhd" in Library proc_common_v3_00_a.
Entity <eval_timer> compiled.
Entity <eval_timer> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_steer.vhd" in Library proc_common_v3_00_a.
Entity <IPIF_Steer> compiled.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_steer128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_steer128> compiled.
Entity <ipif_steer128> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_mirror128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_mirror128> compiled.
Entity <ipif_mirror128> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg> compiled.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg2.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg2> compiled.
Entity <ld_arith_reg2> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/mux_onehot.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_bits.vhd" in Library proc_common_v3_00_a.
Entity <or_bits> compiled.
Entity <or_bits> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate.vhd" in Library proc_common_v3_00_a.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_dpram_select.vhd" in Library proc_common_v3_00_a.
Entity <pf_dpram_select> compiled.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect.vhd" in Library proc_common_v3_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_mask.vhd" in Library proc_common_v3_00_a.
Entity <pselect_mask> compiled.
Entity <pselect_mask> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl16_fifo.vhd" in Library proc_common_v3_00_a.
Entity <srl16_fifo> compiled.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo.vhd" in Library proc_common_v3_00_a.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo2.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo2> compiled.
Entity <srl_fifo2> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo3.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo3> compiled.
Entity <srl_fifo3> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu> compiled.
Entity <srl_fifo_rbu> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/valid_be.vhd" in Library proc_common_v3_00_a.
Entity <valid_be> compiled.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_with_enable_f.vhd" in Library proc_common_v3_00_a.
Entity <or_with_enable_f> compiled.
Entity <or_with_enable_f> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_i_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_i_f> compiled.
Entity <dynshreg_i_f> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/mux_onehot_f.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot_f> compiled.
Entity <mux_onehot_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_f> compiled.
Entity <srl_fifo_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/compare_vectors_f.vhd" in Library proc_common_v3_00_a.
Entity <compare_vectors_f> compiled.
Entity <compare_vectors_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate_f.vhd" in Library proc_common_v3_00_a.
Entity <or_gate_f> compiled.
Entity <or_gate_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/soft_reset.vhd" in Library proc_common_v3_00_a.
Entity <soft_reset> compiled.
Entity <soft_reset> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2_counter.vhd" in Library xps_ps2_v1_01_b.
Entity <ps2_counter> compiled.
Entity <ps2_counter> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2_reg.vhd" in Library xps_ps2_v1_01_b.
Entity <ps2_reg> compiled.
Entity <ps2_reg> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2_sie.vhd" in Library xps_ps2_v1_01_b.
Entity <ps2_sie> compiled.
Entity <ps2_sie> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2.vhd" in Library xps_ps2_v1_01_b.
Entity <ps2> compiled.
Entity <ps2> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/xps_ps2.vhd" in Library xps_ps2_v1_01_b.
Entity <xps_ps2> compiled.
Entity <xps_ps2> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/hdl/xps_ps2_0_wrapper.vhd" in Library work.
Entity <xps_ps2_0_wrapper> compiled.
Entity <xps_ps2_0_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <xps_ps2_0_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <xps_ps2> in library <xps_ps2_v1_01_b> (architecture <imp>) with generics.
	C_BASEADDR = "10000110101000000000000000000000"
	C_FAMILY = "spartan3e"
	C_HIGHADDR = "10000110101000001111111111111111"
	C_IS_DUAL = 0
	C_SPLB_AWIDTH = 32
	C_SPLB_CLK_FREQ_HZ = 50000000
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SUPPORT_BURSTS = 0
WARNING:Xst:821 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/xps_ps2.vhd" line 336: Loop body will iterate zero times
WARNING:Xst:821 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/xps_ps2.vhd" line 363: Loop body will iterate zero times

Analyzing hierarchy for entity <plbv46_slave_single> in library <plbv46_slave_single_v1_01_a> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000110101000000000000000000000",
	                          "0000000000000000000000000000000010000110101000000000000001001111")
	C_ARD_NUM_CE_ARRAY = (20)
	C_BUS2CORE_CLK_RATIO = 1
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SIPIF_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <ps2> in library <xps_ps2_v1_01_b> (architecture <IMP>) with generics.
	C_FAMILY = "spartan3e"
	C_SPLB_AWIDTH = 32
	C_SPLB_CLK_FREQ_HZ = 50000000
	C_SPLB_DWIDTH = 32

Analyzing hierarchy for entity <plb_slave_attachment> in library <plbv46_slave_single_v1_01_a> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000110101000000000000000000000",
	                          "0000000000000000000000000000000010000110101000000000000001001111")
	C_ARD_NUM_CE_ARRAY = (20)
	C_BUS2CORE_CLK_RATIO = 1
	C_DPHASE_TIMEOUT = 128
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <ps2_reg> in library <xps_ps2_v1_01_b> (architecture <imp>) with generics.
	C_FAMILY = "spartan3e"
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32

Analyzing hierarchy for entity <ps2_sie> in library <xps_ps2_v1_01_b> (architecture <IMP>) with generics.
	C_FAMILY = "spartan3e"
	C_SPLB_AWIDTH = 32
	C_SPLB_CLK_FREQ_HZ = 50000000
	C_SPLB_DWIDTH = 32

Analyzing hierarchy for entity <interrupt_control> in library <interrupt_control_v2_01_a> (architecture <implementation>) with generics.
	C_INCLUDE_DEV_ISC = false
	C_INCLUDE_DEV_PENCODER = false
	C_IPIF_DWIDTH = 32
	C_IP_INTR_MODE_ARRAY = (5,5,5,5,5,5)
	C_NUM_CE = 16
	C_NUM_IPIF_IRPT_SRC = 1

Analyzing hierarchy for entity <plb_address_decoder> in library <plbv46_slave_single_v1_01_a> (architecture <IMP>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000110101000000000000000000000",
	                          "0000000000000000000000000000000010000110101000000000000001001111")
	C_ARD_NUM_CE_ARRAY = (20)
	C_BUS_AWIDTH = 32
	C_FAMILY = "nofamily"
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <counter_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_FAMILY = "nofamily"
	C_NUM_BITS = 8

Analyzing hierarchy for entity <ps2_counter> in library <xps_ps2_v1_01_b> (architecture <IMP>) with generics.
	C_COUNT = 5000

Analyzing hierarchy for entity <ps2_counter> in library <xps_ps2_v1_01_b> (architecture <IMP>) with generics.
	C_COUNT = 2500

Analyzing hierarchy for entity <ps2_counter> in library <xps_ps2_v1_01_b> (architecture <IMP>) with generics.
	C_COUNT = 750000

Analyzing hierarchy for entity <ps2_counter> in library <xps_ps2_v1_01_b> (architecture <IMP>) with generics.
	C_COUNT = 10000

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 25
	C_AW = 32
	C_BAR = "10000110101000000000000000000000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "00000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "00001"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "00010"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "00011"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "00100"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "00101"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "00110"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "00111"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "01000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "01001"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "01010"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "01011"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "01100"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "01101"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "01110"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "01111"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "10000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "10001"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "10010"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 5
	C_AW = 5
	C_BAR = "10011"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <or_gate128> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 1
	C_USE_LUT_OR = false

Analyzing hierarchy for entity <or_muxcy> in library <proc_common_v3_00_a> (architecture <implementation>) with generics.
	C_NUM_BITS = 1


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <xps_ps2_0_wrapper> in library <work> (Architecture <STRUCTURE>).
WARNING:Xst:37 - Detected unknown constraint/property "IP_GROUP". This constraint/property is not supported by the current software release and will be ignored.
    Set property "MAX_FANOUT = 10000" for signal <SPLB_Clk> in unit <xps_ps2>.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
    Set property "MAX_FANOUT = 10000" for signal <SPLB_Rst> in unit <xps_ps2>.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "IP_GROUP". This constraint/property is not supported by the current software release and will be ignored.
Entity <xps_ps2_0_wrapper> analyzed. Unit <xps_ps2_0_wrapper> generated.

Analyzing generic Entity <xps_ps2> in library <xps_ps2_v1_01_b> (Architecture <imp>).
	C_BASEADDR = "10000110101000000000000000000000"
	C_FAMILY = "spartan3e"
	C_HIGHADDR = "10000110101000001111111111111111"
	C_IS_DUAL = 0
	C_SPLB_AWIDTH = 32
	C_SPLB_CLK_FREQ_HZ = 50000000
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SUPPORT_BURSTS = 0
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:821 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/xps_ps2.vhd" line 336: Loop body will iterate zero times
WARNING:Xst:821 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/xps_ps2.vhd" line 363: Loop body will iterate zero times
Entity <xps_ps2> analyzed. Unit <xps_ps2> generated.

Analyzing generic Entity <plbv46_slave_single> in library <plbv46_slave_single_v1_01_a> (Architecture <implementation>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000110101000000000000000000000",
	                          "0000000000000000000000000000000010000110101000000000000001001111")
	C_ARD_NUM_CE_ARRAY = (20)
	C_BUS2CORE_CLK_RATIO = 1
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SIPIF_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
Entity <plbv46_slave_single> analyzed. Unit <plbv46_slave_single> generated.

Analyzing generic Entity <plb_slave_attachment> in library <plbv46_slave_single_v1_01_a> (Architecture <implementation>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000110101000000000000000000000",
	                          "0000000000000000000000000000000010000110101000000000000001001111")
	C_ARD_NUM_CE_ARRAY = (20)
	C_BUS2CORE_CLK_RATIO = 1
	C_DPHASE_TIMEOUT = 128
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" line 1201: Unconnected output port 'Count_Out' of component 'counter_f'.
Entity <plb_slave_attachment> analyzed. Unit <plb_slave_attachment> generated.

Analyzing generic Entity <plb_address_decoder> in library <plbv46_slave_single_v1_01_a> (Architecture <IMP>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000110101000000000000000000000",
	                          "0000000000000000000000000000000010000110101000000000000001001111")
	C_ARD_NUM_CE_ARRAY = (20)
	C_BUS_AWIDTH = 32
	C_FAMILY = "nofamily"
	C_SPLB_P2P = 0
Entity <plb_address_decoder> analyzed. Unit <plb_address_decoder> generated.

Analyzing generic Entity <pselect_f.1> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 25
	C_AW = 32
	C_BAR = "10000110101000000000000000000000"
	C_FAMILY = "nofamily"
Entity <pselect_f.1> analyzed. Unit <pselect_f.1> generated.

Analyzing generic Entity <pselect_f.2> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "00000"
	C_FAMILY = "nofamily"
Entity <pselect_f.2> analyzed. Unit <pselect_f.2> generated.

Analyzing generic Entity <pselect_f.3> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "00001"
	C_FAMILY = "nofamily"
Entity <pselect_f.3> analyzed. Unit <pselect_f.3> generated.

Analyzing generic Entity <pselect_f.4> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "00010"
	C_FAMILY = "nofamily"
Entity <pselect_f.4> analyzed. Unit <pselect_f.4> generated.

Analyzing generic Entity <pselect_f.5> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "00011"
	C_FAMILY = "nofamily"
Entity <pselect_f.5> analyzed. Unit <pselect_f.5> generated.

Analyzing generic Entity <pselect_f.6> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "00100"
	C_FAMILY = "nofamily"
Entity <pselect_f.6> analyzed. Unit <pselect_f.6> generated.

Analyzing generic Entity <pselect_f.7> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "00101"
	C_FAMILY = "nofamily"
Entity <pselect_f.7> analyzed. Unit <pselect_f.7> generated.

Analyzing generic Entity <pselect_f.8> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "00110"
	C_FAMILY = "nofamily"
Entity <pselect_f.8> analyzed. Unit <pselect_f.8> generated.

Analyzing generic Entity <pselect_f.9> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "00111"
	C_FAMILY = "nofamily"
Entity <pselect_f.9> analyzed. Unit <pselect_f.9> generated.

Analyzing generic Entity <pselect_f.10> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "01000"
	C_FAMILY = "nofamily"
Entity <pselect_f.10> analyzed. Unit <pselect_f.10> generated.

Analyzing generic Entity <pselect_f.11> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "01001"
	C_FAMILY = "nofamily"
Entity <pselect_f.11> analyzed. Unit <pselect_f.11> generated.

Analyzing generic Entity <pselect_f.12> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "01010"
	C_FAMILY = "nofamily"
Entity <pselect_f.12> analyzed. Unit <pselect_f.12> generated.

Analyzing generic Entity <pselect_f.13> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "01011"
	C_FAMILY = "nofamily"
Entity <pselect_f.13> analyzed. Unit <pselect_f.13> generated.

Analyzing generic Entity <pselect_f.14> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "01100"
	C_FAMILY = "nofamily"
Entity <pselect_f.14> analyzed. Unit <pselect_f.14> generated.

Analyzing generic Entity <pselect_f.15> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "01101"
	C_FAMILY = "nofamily"
Entity <pselect_f.15> analyzed. Unit <pselect_f.15> generated.

Analyzing generic Entity <pselect_f.16> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "01110"
	C_FAMILY = "nofamily"
Entity <pselect_f.16> analyzed. Unit <pselect_f.16> generated.

Analyzing generic Entity <pselect_f.17> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "01111"
	C_FAMILY = "nofamily"
Entity <pselect_f.17> analyzed. Unit <pselect_f.17> generated.

Analyzing generic Entity <pselect_f.18> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "10000"
	C_FAMILY = "nofamily"
Entity <pselect_f.18> analyzed. Unit <pselect_f.18> generated.

Analyzing generic Entity <pselect_f.19> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "10001"
	C_FAMILY = "nofamily"
Entity <pselect_f.19> analyzed. Unit <pselect_f.19> generated.

Analyzing generic Entity <pselect_f.20> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "10010"
	C_FAMILY = "nofamily"
Entity <pselect_f.20> analyzed. Unit <pselect_f.20> generated.

Analyzing generic Entity <pselect_f.21> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 5
	C_AW = 5
	C_BAR = "10011"
	C_FAMILY = "nofamily"
Entity <pselect_f.21> analyzed. Unit <pselect_f.21> generated.

Analyzing generic Entity <or_gate128> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 1
	C_USE_LUT_OR = false
Entity <or_gate128> analyzed. Unit <or_gate128> generated.

Analyzing generic Entity <or_muxcy> in library <proc_common_v3_00_a> (Architecture <implementation>).
	C_NUM_BITS = 1
Entity <or_muxcy> analyzed. Unit <or_muxcy> generated.

Analyzing generic Entity <counter_f> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_FAMILY = "nofamily"
	C_NUM_BITS = 8
Entity <counter_f> analyzed. Unit <counter_f> generated.

Analyzing generic Entity <ps2> in library <xps_ps2_v1_01_b> (Architecture <IMP>).
	C_FAMILY = "spartan3e"
	C_SPLB_AWIDTH = 32
	C_SPLB_CLK_FREQ_HZ = 50000000
	C_SPLB_DWIDTH = 32
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2.vhd" line 282: Unconnected output port 'Intr2Bus_Retry' of component 'interrupt_control'.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2.vhd" line 282: Unconnected output port 'Intr2Bus_ToutSup' of component 'interrupt_control'.
Entity <ps2> analyzed. Unit <ps2> generated.

Analyzing generic Entity <ps2_reg> in library <xps_ps2_v1_01_b> (Architecture <imp>).
	C_FAMILY = "spartan3e"
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
INFO:Xst:2679 - Register <rx_reg<0>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<1>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<2>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<3>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<4>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<5>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<6>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<7>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<8>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<9>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<10>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<11>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<12>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<13>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<14>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<15>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<16>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<17>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<18>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<19>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<20>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<21>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<22>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <rx_reg<23>> in unit <ps2_reg> has a constant value of 0 during circuit operation. The register is replaced by logic.
Entity <ps2_reg> analyzed. Unit <ps2_reg> generated.

Analyzing generic Entity <ps2_sie> in library <xps_ps2_v1_01_b> (Architecture <IMP>).
	C_FAMILY = "spartan3e"
	C_SPLB_AWIDTH = 32
	C_SPLB_CLK_FREQ_HZ = 50000000
	C_SPLB_DWIDTH = 32
Entity <ps2_sie> analyzed. Unit <ps2_sie> generated.

Analyzing generic Entity <ps2_counter.1> in library <xps_ps2_v1_01_b> (Architecture <IMP>).
	C_COUNT = 5000
Entity <ps2_counter.1> analyzed. Unit <ps2_counter.1> generated.

Analyzing generic Entity <ps2_counter.2> in library <xps_ps2_v1_01_b> (Architecture <IMP>).
	C_COUNT = 2500
Entity <ps2_counter.2> analyzed. Unit <ps2_counter.2> generated.

Analyzing generic Entity <ps2_counter.3> in library <xps_ps2_v1_01_b> (Architecture <IMP>).
	C_COUNT = 750000
Entity <ps2_counter.3> analyzed. Unit <ps2_counter.3> generated.

Analyzing generic Entity <ps2_counter.4> in library <xps_ps2_v1_01_b> (Architecture <IMP>).
	C_COUNT = 10000
Entity <ps2_counter.4> analyzed. Unit <ps2_counter.4> generated.

Analyzing generic Entity <interrupt_control> in library <interrupt_control_v2_01_a> (Architecture <implementation>).
	C_INCLUDE_DEV_ISC = false
	C_INCLUDE_DEV_PENCODER = false
	C_IPIF_DWIDTH = 32
	C_IP_INTR_MODE_ARRAY = (5,5,5,5,5,5)
	C_NUM_CE = 16
	C_NUM_IPIF_IRPT_SRC = 1
Entity <interrupt_control> analyzed. Unit <interrupt_control> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <counter_f>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd".
    Found 9-bit register for signal <icount_out>.
    Found 9-bit subtractor for signal <icount_out$sub0000> created at line 297.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <counter_f> synthesized.


Synthesizing Unit <pselect_f_1>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
WARNING:Xst:647 - Input <A<25:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <pselect_f_1> synthesized.


Synthesizing Unit <pselect_f_2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_2> synthesized.


Synthesizing Unit <pselect_f_3>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_3> synthesized.


Synthesizing Unit <pselect_f_4>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_4> synthesized.


Synthesizing Unit <pselect_f_5>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_5> synthesized.


Synthesizing Unit <pselect_f_6>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_6> synthesized.


Synthesizing Unit <pselect_f_7>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_7> synthesized.


Synthesizing Unit <pselect_f_8>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_8> synthesized.


Synthesizing Unit <pselect_f_9>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_9> synthesized.


Synthesizing Unit <pselect_f_10>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_10> synthesized.


Synthesizing Unit <pselect_f_11>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_11> synthesized.


Synthesizing Unit <pselect_f_12>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_12> synthesized.


Synthesizing Unit <pselect_f_13>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_13> synthesized.


Synthesizing Unit <pselect_f_14>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_14> synthesized.


Synthesizing Unit <pselect_f_15>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_15> synthesized.


Synthesizing Unit <pselect_f_16>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_16> synthesized.


Synthesizing Unit <pselect_f_17>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_17> synthesized.


Synthesizing Unit <pselect_f_18>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_18> synthesized.


Synthesizing Unit <pselect_f_19>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_19> synthesized.


Synthesizing Unit <pselect_f_20>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_20> synthesized.


Synthesizing Unit <pselect_f_21>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_21> synthesized.


Synthesizing Unit <or_muxcy>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd".
Unit <or_muxcy> synthesized.


Synthesizing Unit <ps2_reg>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2_reg.vhd".
WARNING:Xst:647 - Input <Bus2IP_RNW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_Addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <tx_reg<0:23>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2bus_wrack_i_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2bus_rdack_i_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2bus_err_i_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Register <ip2bus_wrack_i<1>> equivalent to <ip2bus_err_i<1>> has been removed
    Register <ip2bus_wrack_i<2>> equivalent to <ip2bus_err_i<2>> has been removed
    Register <ip2bus_rdack_i<3>> equivalent to <ip2bus_err_i<3>> has been removed
    Found 32-bit register for signal <IP2Bus_Data>.
    Found 4-bit register for signal <bus2ip_rdce_d1>.
    Found 4-bit register for signal <bus2ip_wrce_d1>.
    Found 32-bit 4-to-1 multiplexer for signal <IP2Bus_Data$mux0000>.
    Found 4-bit register for signal <ip2bus_err_i>.
    Found 3-bit register for signal <ip2bus_rdack_i<0:2>>.
    Found 1-bit register for signal <ip2bus_wrack_i<0>>.
    Found 1-bit register for signal <ip2bus_wrack_i<3>>.
    Found 1-bit register for signal <rx_full_i>.
    Found 8-bit register for signal <rx_reg<24:31>>.
    Found 1-bit register for signal <srst_i>.
    Found 1-bit register for signal <tx_full_i>.
    Found 32-bit register for signal <tx_reg>.
    Summary:
	inferred  92 D-type flip-flop(s).
	inferred  32 Multiplexer(s).
Unit <ps2_reg> synthesized.


Synthesizing Unit <interrupt_control>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd".
WARNING:Xst:647 - Input <Bus2IP_Data<1:25>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_BE<1:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_RdCE<0:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_RdCE<9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_RdCE<11:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_WrCE<0:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_WrCE<9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_WrCE<11:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <trans_reg_irpts> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <trans_lvl_irpts<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ipif_priority_encode_value> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ipif_pri_encode_present> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ipif_irpt_status_value> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ipif_irpt_status_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ipif_irpt_pending_value> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ipif_irpt_enable_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ipif_interrupt_or> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <Intr2Bus_WrAck>.
    Found 1-bit register for signal <Intr2Bus_RdAck>.
    Found 6-bit register for signal <ip_irpt_enable_reg>.
    Found 6-bit register for signal <ip_irpt_status_reg>.
    Found 1-bit xor2 for signal <ip_irpt_status_reg_0$xor0000> created at line 733.
    Found 1-bit xor2 for signal <ip_irpt_status_reg_1$xor0000> created at line 733.
    Found 1-bit xor2 for signal <ip_irpt_status_reg_2$xor0000> created at line 733.
    Found 1-bit xor2 for signal <ip_irpt_status_reg_3$xor0000> created at line 733.
    Found 1-bit xor2 for signal <ip_irpt_status_reg_4$xor0000> created at line 733.
    Found 1-bit xor2 for signal <ip_irpt_status_reg_5$xor0000> created at line 733.
    Found 1-bit register for signal <ipif_glbl_irpt_enable_reg>.
    Found 1-bit register for signal <irpt_dly1>.
    Found 1-bit register for signal <irpt_dly10>.
    Found 1-bit register for signal <irpt_dly11>.
    Found 1-bit register for signal <irpt_dly12>.
    Found 1-bit register for signal <irpt_dly13>.
    Found 1-bit register for signal <irpt_dly14>.
    Found 1-bit register for signal <irpt_dly2>.
    Found 1-bit register for signal <irpt_dly20>.
    Found 1-bit register for signal <irpt_dly21>.
    Found 1-bit register for signal <irpt_dly22>.
    Found 1-bit register for signal <irpt_dly23>.
    Found 1-bit register for signal <irpt_dly24>.
    Found 1-bit register for signal <irpt_rdack_d1>.
    Found 1-bit register for signal <irpt_wrack_d1>.
    Summary:
	inferred  29 D-type flip-flop(s).
Unit <interrupt_control> synthesized.


Synthesizing Unit <ps2_counter_1>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2_counter.vhd".
    Found 1-bit register for signal <Count_Done>.
    Found 1-bit register for signal <Count_Almost_Done>.
    Found 14-bit up counter for signal <tmp>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <ps2_counter_1> synthesized.


Synthesizing Unit <ps2_counter_2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2_counter.vhd".
    Found 1-bit register for signal <Count_Done>.
    Found 1-bit register for signal <Count_Almost_Done>.
    Found 13-bit up counter for signal <tmp>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <ps2_counter_2> synthesized.


Synthesizing Unit <ps2_counter_3>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2_counter.vhd".
    Found 1-bit register for signal <Count_Done>.
    Found 1-bit register for signal <Count_Almost_Done>.
    Found 21-bit up counter for signal <tmp>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <ps2_counter_3> synthesized.


Synthesizing Unit <ps2_counter_4>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2_counter.vhd".
    Found 1-bit register for signal <Count_Done>.
    Found 1-bit register for signal <Count_Almost_Done>.
    Found 15-bit up counter for signal <tmp>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <ps2_counter_4> synthesized.


Synthesizing Unit <or_gate128>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <or_gate128> synthesized.


Synthesizing Unit <ps2_sie>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2_sie.vhd".
WARNING:Xst:1780 - Signal <wdt_tout> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ps2_data_t_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ps2_data_o_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ps2_clk_t_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ps2_clk_o_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <clk_is_low> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <clk_is_high> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <almost_done_wdt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <almost_done_50us> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <almost_done_15ms> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Register <RX_FULL_set> equivalent to <rx_full_cs> has been removed
    Found finite state machine <FSM_0> for signal <clk_cntrl_sm_cs>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 16                                             |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | Clk                       (rising_edge)        |
    | Reset              | Rst                       (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | clk_pull_up                                    |
    | Power Up State     | clk_pull_up                                    |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <tx_state_machine_cs>.
    Using one-hot encoding for signal <rx_state_machine_cs>.
    Found 8-bit register for signal <RX_DATA>.
    Found 1-bit register for signal <RX_ERR_set>.
    Found 1-bit register for signal <PS2_DATA_O>.
    Found 1-bit register for signal <PS2_DATA_T>.
    Found 1-bit register for signal <RX_OVF_set>.
    Found 1-bit register for signal <TX_Full_Clr>.
    Found 1-bit register for signal <TX_ACKF_set>.
    Found 1-bit register for signal <WDT_TOUT_set>.
    Found 1-bit register for signal <PS2_CLK_O>.
    Found 1-bit register for signal <PS2_CLK_T>.
    Found 1-bit register for signal <TX_NOACK_set>.
    Found 1-bit register for signal <ps2_clk_i_d1>.
    Found 1-bit register for signal <ps2_clk_i_int>.
    Found 1-bit register for signal <ps2_clk_o_rx_cs>.
    Found 1-bit register for signal <ps2_clk_o_tx_cs>.
    Found 1-bit register for signal <ps2_clk_t_rx_cs>.
    Found 1-bit register for signal <ps2_clk_t_tx_cs>.
    Found 1-bit register for signal <ps2_data_i_d1>.
    Found 1-bit register for signal <ps2_data_i_int>.
    Found 1-bit register for signal <ps2_data_o_tx_cs>.
    Found 1-bit register for signal <ps2_data_t_tx_cs>.
    Found 11-bit register for signal <rx_cs>.
    Found 1-bit register for signal <rx_full_cs>.
    Found 1-bit xor9 for signal <rx_parity_odd>.
    Found 15-bit register for signal <rx_state_machine_cs>.
    Found 1-bit register for signal <start_15ms_cntr_cs>.
    Found 1-bit xor8 for signal <tx_parity_bit$xor0000> created at line 168.
    Found 15-bit register for signal <tx_state_machine_cs>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  71 D-type flip-flop(s).
	inferred   2 Xor(s).
Unit <ps2_sie> synthesized.


Synthesizing Unit <ps2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/ps2.vhd".
Unit <ps2> synthesized.


Synthesizing Unit <plb_address_decoder>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_address_decoder.vhd".
WARNING:Xst:647 - Input <Bus_RNW_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Address_In_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Address_Valid_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <cs_s_h_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cs_ce_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr_out_s_h<5:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr_match_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 7-bit register for signal <addr_out_s_h>.
    Found 1-bit register for signal <cs_out_i<0>>.
    Found 1-bit register for signal <cs_out_s_h<0>>.
    Found 1-bit register for signal <decode_hit_reg>.
    Found 20-bit register for signal <rdce_out_i>.
    Found 1-bit register for signal <rnw_s_h>.
    Found 20-bit register for signal <wrce_out_i>.
    Summary:
	inferred  51 D-type flip-flop(s).
Unit <plb_address_decoder> synthesized.


Synthesizing Unit <plb_slave_attachment>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd".
WARNING:Xst:647 - Input <PLB_UABus> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <valid_plb_type> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <valid_plb_size> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <start_data_phase> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wrdack_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wrcomp_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wait_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_rddack_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_rdcomp_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_data_ack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <set_sl_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd_ce_ld_enable> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_rd_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_rd_busy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_rd_ce> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Register <sl_rdcomp_i> equivalent to <rd_clear_sl_busy> has been removed
    Register <sl_rddack_i> equivalent to <rd_clear_sl_busy> has been removed
    Register <sl_addrack_i> equivalent to <set_sl_busy> has been removed
    Register <sl_wrdack_i> equivalent to <sl_wrcomp_i> has been removed
    Register <wr_clear_sl_busy> equivalent to <sl_wrcomp_i> has been removed
    Found 1-bit register for signal <addr_cntl_cs<0>>.
    Found 1-bit register for signal <addr_cycle_flush>.
    Found 32-bit register for signal <bus2ip_addr_i>.
    Found 4-bit register for signal <bus2ip_be_i>.
    Found 1-bit register for signal <bus2ip_rnw_i>.
    Found 1-bit register for signal <data_timeout>.
    Found 1-bit register for signal <master_id<31>>.
    Found 32-bit register for signal <plb_abus_reg>.
    Found 4-bit register for signal <plb_be_reg>.
    Found 1-bit register for signal <plb_masterid_reg<0>>.
    Found 1-bit register for signal <plb_pavalid_reg>.
    Found 1-bit register for signal <plb_rnw_reg>.
    Found 4-bit register for signal <plb_size_reg>.
    Found 3-bit register for signal <plb_type_reg>.
    Found 32-bit register for signal <plb_wrdbus_reg>.
    Found 1-bit register for signal <rd_clear_sl_busy>.
    Found 1-bit register for signal <set_sl_busy>.
    Found 1-bit register for signal <sl_busy>.
    Found 2-bit register for signal <sl_mbusy_i>.
    Found 2-bit register for signal <sl_mrderr_i>.
    Found 2-bit register for signal <sl_mwrerr_i>.
    Found 32-bit register for signal <sl_rddbus_i>.
    Found 1-bit register for signal <sl_rearbitrate_i>.
    Found 1-bit register for signal <sl_wrcomp_i>.
    Summary:
	inferred 162 D-type flip-flop(s).
Unit <plb_slave_attachment> synthesized.


Synthesizing Unit <plbv46_slave_single>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plbv46_slave_single.vhd".
WARNING:Xst:647 - Input <PLB_wrPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_MSize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdBurst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_SAValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_busLock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_reqPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_lockErr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrBurst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_TAttribute> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_abort> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <plbv46_slave_single> synthesized.


Synthesizing Unit <xps_ps2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/hdl/vhdl/xps_ps2.vhd".
WARNING:Xst:647 - Input <PS2_2_CLK_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <PS2_2_CLK_O> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <PS2_2_CLK_T> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <PS2_2_DATA_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <PS2_2_DATA_O> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <PS2_2_DATA_T> is never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <ip2bus_wrack_2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2bus_rdack_2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2bus_error_2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2bus_data_2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <intr_or_rdce> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <intr2bus_wrack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <intr2bus_rdack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <intr2bus_error> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <intr2bus_data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Bus2IP_Data_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <xps_ps2> synthesized.


Synthesizing Unit <xps_ps2_0_wrapper>.
    Related source file is "C:/Temp/Bomberman/hdl/xps_ps2_0_wrapper.vhd".
Unit <xps_ps2_0_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 9-bit subtractor                                      : 1
# Counters                                             : 4
 13-bit up counter                                     : 1
 14-bit up counter                                     : 1
 15-bit up counter                                     : 1
 21-bit up counter                                     : 1
# Registers                                            : 155
 1-bit register                                        : 136
 11-bit register                                       : 1
 15-bit register                                       : 2
 3-bit register                                        : 1
 32-bit register                                       : 6
 4-bit register                                        : 5
 6-bit register                                        : 1
 7-bit register                                        : 1
 8-bit register                                        : 1
 9-bit register                                        : 1
# Multiplexers                                         : 1
 32-bit 4-to-1 multiplexer                             : 1
# Xors                                                 : 8
 1-bit xor2                                            : 6
 1-bit xor8                                            : 1
 1-bit xor9                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <xps_ps2_0/PS2_1_I/PS2_SIE_I/clk_cntrl_sm_cs/FSM> on signal <clk_cntrl_sm_cs[1:2]> with user encoding.
-------------------------
 State       | Encoding
-------------------------
 clk_pull_up | 00
 clk_high    | 01
 clk_low     | 10
 clk_inhibit | 11
-------------------------
WARNING:Xst:2677 - Node <tx_reg_23> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_22> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_21> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_20> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_19> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_18> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_17> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_16> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_15> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_14> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_13> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_12> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_11> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_10> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_9> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_8> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_7> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_6> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_5> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_4> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_3> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_2> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_1> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <tx_reg_0> of sequential type is unconnected in block <ps2_reg>.
WARNING:Xst:2677 - Node <rx_cs_10> of sequential type is unconnected in block <ps2_sie>.
WARNING:Xst:2677 - Node <rx_cs_0> of sequential type is unconnected in block <ps2_sie>.
WARNING:Xst:2677 - Node <addr_out_s_h_6> of sequential type is unconnected in block <plb_address_decoder>.
WARNING:Xst:2677 - Node <addr_out_s_h_5> of sequential type is unconnected in block <plb_address_decoder>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# Adders/Subtractors                                   : 1
 9-bit subtractor                                      : 1
# Counters                                             : 4
 13-bit up counter                                     : 1
 14-bit up counter                                     : 1
 15-bit up counter                                     : 1
 21-bit up counter                                     : 1
# Registers                                            : 394
 Flip-Flops                                            : 394
# Multiplexers                                         : 1
 32-bit 4-to-1 multiplexer                             : 1
# Xors                                                 : 8
 1-bit xor2                                            : 6
 1-bit xor8                                            : 1
 1-bit xor9                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch <addr_cntl_cs_0> in Unit <plb_slave_attachment> is equivalent to the following FF/Latch, which will be removed : <addr_cycle_flush> 
WARNING:Xst:1710 - FF/Latch <IP2Bus_Data_0> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_1> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_2> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_3> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_4> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_5> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_6> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_7> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_8> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_9> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_10> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_11> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_12> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_13> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_14> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_15> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_16> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_17> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_18> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_19> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_20> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_21> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_22> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IP2Bus_Data_23> (without init value) has a constant value of 0 in block <ps2_reg>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <xps_ps2_0_wrapper> ...

Optimizing unit <counter_f> ...

Optimizing unit <ps2_reg> ...

Optimizing unit <interrupt_control> ...

Optimizing unit <ps2_counter_1> ...

Optimizing unit <ps2_counter_2> ...

Optimizing unit <ps2_counter_3> ...

Optimizing unit <ps2_counter_4> ...

Optimizing unit <ps2_sie> ...

Optimizing unit <plb_address_decoder> ...

Optimizing unit <ps2> ...

Optimizing unit <plb_slave_attachment> ...
WARNING:Xst:1710 - FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_23> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_22> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_21> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_20> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_19> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_18> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_17> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_16> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_15> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_14> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_13> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_12> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_11> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_10> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_9> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_8> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_7> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_6> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_5> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_4> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_3> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_2> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_1> (without init value) has a constant value of 0 in block <xps_ps2_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <xps_ps2_0/PS2_1_I/PS2_SIE_I/COUNTER_50us_I/Count_Almost_Done> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PS2_1_I/PS2_SIE_I/COUNTER_15ms_I/Count_Almost_Done> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PS2_1_I/PS2_SIE_I/COUNTER_WDT_I/Count_Almost_Done> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_4> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_5> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_6> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_7> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_8> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_9> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_10> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_13> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_15> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_16> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_17> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_18> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_19> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_0> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_1> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_2> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_3> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_4> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_5> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_6> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_7> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_8> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_9> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_10> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_11> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_12> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_13> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_14> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_15> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_16> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_17> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_18> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_19> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_20> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_21> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_22> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_23> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_24> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_25> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_26> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_27> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_28> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_29> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_30> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_31> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/plb_abus_reg_30> of sequential type is unconnected in block <xps_ps2_0_wrapper>.
WARNING:Xst:2677 - Node <xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/plb_abus_reg_31> of sequential type is unconnected in block <xps_ps2_0_wrapper>.

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 361
 Flip-Flops                                            : 361

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/xps_ps2_0_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 215

Cell Usage :
# BELS                             : 578
#      GND                         : 1
#      INV                         : 5
#      LUT1                        : 59
#      LUT2                        : 59
#      LUT2_D                      : 4
#      LUT2_L                      : 8
#      LUT3                        : 42
#      LUT3_D                      : 9
#      LUT3_L                      : 14
#      LUT4                        : 193
#      LUT4_D                      : 11
#      LUT4_L                      : 23
#      MUXCY                       : 81
#      MUXF5                       : 5
#      VCC                         : 1
#      XORCY                       : 63
# FlipFlops/Latches                : 361
#      FD                          : 32
#      FDR                         : 181
#      FDRE                        : 92
#      FDRS                        : 15
#      FDRSE                       : 5
#      FDS                         : 29
#      FDSE                        : 7
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                      283  out of   8672     3%  
 Number of Slice Flip Flops:            361  out of  17344     2%  
 Number of 4 input LUTs:                427  out of  17344     2%  
 Number of IOs:                         215
 Number of bonded IOBs:                   0  out of    250     0%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+-----------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                         | Load  |
-----------------------------------+-----------------------------------------------+-------+
SPLB_Clk                           | NONE(xps_ps2_0/PS2_1_I/PS2_SIE_I/TX_NOACK_set)| 361   |
-----------------------------------+-----------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.298ns (Maximum Frequency: 137.024MHz)
   Minimum input arrival time before clock: 3.679ns
   Maximum output required time after clock: 3.120ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'SPLB_Clk'
  Clock period: 7.298ns (frequency: 137.024MHz)
  Total number of paths / destination ports: 4985 / 633
-------------------------------------------------------------------------
Delay:               7.298ns (Levels of Logic = 4)
  Source:            xps_ps2_0/PS2_1_I/PS2_SIE_I/ps2_clk_t_tx_cs (FF)
  Destination:       xps_ps2_0/PS2_1_I/PS2_SIE_I/COUNTER_WDT_I/tmp_0 (FF)
  Source Clock:      SPLB_Clk rising
  Destination Clock: SPLB_Clk rising

  Data Path: xps_ps2_0/PS2_1_I/PS2_SIE_I/ps2_clk_t_tx_cs to xps_ps2_0/PS2_1_I/PS2_SIE_I/COUNTER_WDT_I/tmp_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDSE:C->Q             4   0.591   0.762  xps_ps2_0/PS2_1_I/PS2_SIE_I/ps2_clk_t_tx_cs (xps_ps2_0/PS2_1_I/PS2_SIE_I/ps2_clk_t_tx_cs)
     LUT2:I0->O            6   0.704   0.673  xps_ps2_0/PS2_1_I/PS2_SIE_I/ps2_clk_t_int1 (xps_ps2_0/PS2_1_I/PS2_SIE_I/ps2_clk_t_int)
     LUT4_L:I3->LO         1   0.704   0.104  xps_ps2_0/PS2_1_I/PS2_SIE_I/clk_fall1_1 (xps_ps2_0/PS2_1_I/PS2_SIE_I/clk_fall1)
     LUT4:I3->O            1   0.704   0.424  xps_ps2_0/PS2_1_I/PS2_SIE_I/clr_wdt_cntr54 (xps_ps2_0/PS2_1_I/PS2_SIE_I/clr_wdt_cntr54)
     LUT4:I3->O           15   0.704   1.017  xps_ps2_0/PS2_1_I/PS2_SIE_I/clr_wdt_cntr88 (xps_ps2_0/PS2_1_I/PS2_SIE_I/clr_wdt_cntr)
     FDR:R                     0.911          xps_ps2_0/PS2_1_I/PS2_SIE_I/COUNTER_WDT_I/tmp_14
    ----------------------------------------
    Total                      7.298ns (4.318ns logic, 2.980ns route)
                                       (59.2% logic, 40.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SPLB_Clk'
  Total number of paths / destination ports: 262 / 262
-------------------------------------------------------------------------
Offset:              3.679ns (Levels of Logic = 2)
  Source:            SPLB_Rst (PAD)
  Destination:       xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0 (FF)
  Destination Clock: SPLB_Clk rising

  Data Path: SPLB_Rst to xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT2_L:I1->LO         1   0.704   0.179  xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/data_ack1_SW1 (N134)
     LUT4:I1->O           20   0.704   1.102  xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_clr1 (xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_clr)
     FDRE:R                    0.911          xps_ps2_0/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0
    ----------------------------------------
    Total                      3.679ns (2.398ns logic, 1.281ns route)
                                       (65.2% logic, 34.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'SPLB_Clk'
  Total number of paths / destination ports: 38 / 26
-------------------------------------------------------------------------
Offset:              3.120ns (Levels of Logic = 2)
  Source:            xps_ps2_0/PS2_1_I/INTERRUPT_CONTROL_I/ip_irpt_enable_reg_3 (FF)
  Destination:       IP2INTC_Irpt_1 (PAD)
  Source Clock:      SPLB_Clk rising

  Data Path: xps_ps2_0/PS2_1_I/INTERRUPT_CONTROL_I/ip_irpt_enable_reg_3 to IP2INTC_Irpt_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   0.591   0.622  xps_ps2_0/PS2_1_I/INTERRUPT_CONTROL_I/ip_irpt_enable_reg_3 (xps_ps2_0/PS2_1_I/INTERRUPT_CONTROL_I/ip_irpt_enable_reg_3)
     LUT4:I0->O            1   0.704   0.499  xps_ps2_0/PS2_1_I/INTERRUPT_CONTROL_I/ipif_interrupt4 (xps_ps2_0/PS2_1_I/INTERRUPT_CONTROL_I/ipif_interrupt4)
     LUT4:I1->O            0   0.704   0.000  xps_ps2_0/PS2_1_I/INTERRUPT_CONTROL_I/ipif_interrupt35 (IP2INTC_Irpt_1)
    ----------------------------------------
    Total                      3.120ns (1.999ns logic, 1.121ns route)
                                       (64.1% logic, 35.9% route)

=========================================================================


Total REAL time to Xst completion: 40.00 secs
Total CPU time to Xst completion: 40.17 secs
 
--> 

Total memory usage is 306296 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  232 (   0 filtered)
Number of infos    :   26 (   0 filtered)

