Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "my_timer_0_wrapper_xst.prj"
Verilog Include Directory          : {"C:\Temp\Bomberman\pcores\" "C:\Xilinx\12.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc3s1200efg320-4
Output File Name                   : "../implementation/my_timer_0_wrapper.ngc"

---- Source Options
Top Module Name                    : my_timer_0_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation/my_timer_0_wrapper}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/pcores/my_timer_v1_00_a/hdl/vhdl/user_logic.vhd" in Library my_timer_v1_00_a.
Entity <user_logic> compiled.
Entity <user_logic> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" in Library my_timer_v1_00_a.
Entity <my_timer> compiled.
Entity <my_timer> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/hdl/my_timer_0_wrapper.vhd" in Library work.
Entity <my_timer_0_wrapper> compiled.
Entity <my_timer_0_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <my_timer_0_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <my_timer> in library <my_timer_v1_00_a> (architecture <IMP>) with generics.
	C_BASEADDR = "11000000101000000000000000000000"
	C_FAMILY = "spartan3e"
	C_HIGHADDR = "11000000101000001111111111111111"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SPLB_AWIDTH = 32
	C_SPLB_CLK_PERIOD_PS = 20000
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SMALLEST_MASTER = 32
	C_SPLB_SUPPORT_BURSTS = 0

Analyzing hierarchy for entity <plbv46_slave_single> in library <plbv46_slave_single_v1_01_a> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000000101000000000000000000000",
	                          "0000000000000000000000000000000011000000101000000000000011111111",
	                          "0000000000000000000000000000000011000000101000000000000100000000",
	                          "0000000000000000000000000000000011000000101000000000000111111111")
	C_ARD_NUM_CE_ARRAY = (2,16)
	C_BUS2CORE_CLK_RATIO = 1
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SIPIF_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <interrupt_control> in library <interrupt_control_v2_01_a> (architecture <implementation>) with generics.
	C_INCLUDE_DEV_ISC = true
	C_INCLUDE_DEV_PENCODER = true
	C_IPIF_DWIDTH = 32
	C_IP_INTR_MODE_ARRAY = (1)
	C_NUM_CE = 16
	C_NUM_IPIF_IRPT_SRC = 4

Analyzing hierarchy for entity <user_logic> in library <my_timer_v1_00_a> (architecture <IMP>) with generics.
	C_NUM_INTR = 1
	C_NUM_REG = 2
	C_SLV_DWIDTH = 32

Analyzing hierarchy for entity <plb_slave_attachment> in library <plbv46_slave_single_v1_01_a> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000000101000000000000000000000",
	                          "0000000000000000000000000000000011000000101000000000000011111111",
	                          "0000000000000000000000000000000011000000101000000000000100000000",
	                          "0000000000000000000000000000000011000000101000000000000111111111")
	C_ARD_NUM_CE_ARRAY = (2,16)
	C_BUS2CORE_CLK_RATIO = 1
	C_DPHASE_TIMEOUT = 128
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <plb_address_decoder> in library <plbv46_slave_single_v1_01_a> (architecture <IMP>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000000101000000000000000000000",
	                          "0000000000000000000000000000000011000000101000000000000011111111",
	                          "0000000000000000000000000000000011000000101000000000000100000000",
	                          "0000000000000000000000000000000011000000101000000000000111111111")
	C_ARD_NUM_CE_ARRAY = (2,16)
	C_BUS_AWIDTH = 32
	C_FAMILY = "nofamily"
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <counter_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_FAMILY = "nofamily"
	C_NUM_BITS = 8

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 24
	C_AW = 32
	C_BAR = "11000000101000000000000000000000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 1
	C_AW = 1
	C_BAR = "0"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 1
	C_AW = 1
	C_BAR = "1"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 24
	C_AW = 32
	C_BAR = "11000000101000000000000100000000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "0000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "0001"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "0010"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "0011"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "0100"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "0101"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "0110"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "0111"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "1000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "1001"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "1010"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "1011"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "1100"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "1101"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "1110"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 4
	C_AW = 4
	C_BAR = "1111"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <or_gate128> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 2
	C_USE_LUT_OR = false

Analyzing hierarchy for entity <or_muxcy> in library <proc_common_v3_00_a> (architecture <implementation>) with generics.
	C_NUM_BITS = 2


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <my_timer_0_wrapper> in library <work> (Architecture <STRUCTURE>).
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
Entity <my_timer_0_wrapper> analyzed. Unit <my_timer_0_wrapper> generated.

Analyzing generic Entity <my_timer> in library <my_timer_v1_00_a> (Architecture <IMP>).
	C_BASEADDR = "11000000101000000000000000000000"
	C_FAMILY = "spartan3e"
	C_HIGHADDR = "11000000101000001111111111111111"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SPLB_AWIDTH = 32
	C_SPLB_CLK_PERIOD_PS = 20000
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SMALLEST_MASTER = 32
	C_SPLB_SUPPORT_BURSTS = 0
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:753 - "C:/Temp/Bomberman/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" line 435: Unconnected output port 'Intr2Bus_Retry' of component 'interrupt_control'.
WARNING:Xst:753 - "C:/Temp/Bomberman/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd" line 435: Unconnected output port 'Intr2Bus_ToutSup' of component 'interrupt_control'.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
Entity <my_timer> analyzed. Unit <my_timer> generated.

Analyzing generic Entity <plbv46_slave_single> in library <plbv46_slave_single_v1_01_a> (Architecture <implementation>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000000101000000000000000000000",
	                          "0000000000000000000000000000000011000000101000000000000011111111",
	                          "0000000000000000000000000000000011000000101000000000000100000000",
	                          "0000000000000000000000000000000011000000101000000000000111111111")
	C_ARD_NUM_CE_ARRAY = (2,16)
	C_BUS2CORE_CLK_RATIO = 1
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SIPIF_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
Entity <plbv46_slave_single> analyzed. Unit <plbv46_slave_single> generated.

Analyzing generic Entity <plb_slave_attachment> in library <plbv46_slave_single_v1_01_a> (Architecture <implementation>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000000101000000000000000000000",
	                          "0000000000000000000000000000000011000000101000000000000011111111",
	                          "0000000000000000000000000000000011000000101000000000000100000000",
	                          "0000000000000000000000000000000011000000101000000000000111111111")
	C_ARD_NUM_CE_ARRAY = (2,16)
	C_BUS2CORE_CLK_RATIO = 1
	C_DPHASE_TIMEOUT = 128
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" line 1201: Unconnected output port 'Count_Out' of component 'counter_f'.
Entity <plb_slave_attachment> analyzed. Unit <plb_slave_attachment> generated.

Analyzing generic Entity <plb_address_decoder> in library <plbv46_slave_single_v1_01_a> (Architecture <IMP>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000000101000000000000000000000",
	                          "0000000000000000000000000000000011000000101000000000000011111111",
	                          "0000000000000000000000000000000011000000101000000000000100000000",
	                          "0000000000000000000000000000000011000000101000000000000111111111")
	C_ARD_NUM_CE_ARRAY = (2,16)
	C_BUS_AWIDTH = 32
	C_FAMILY = "nofamily"
	C_SPLB_P2P = 0
Entity <plb_address_decoder> analyzed. Unit <plb_address_decoder> generated.

Analyzing generic Entity <pselect_f.1> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 24
	C_AW = 32
	C_BAR = "11000000101000000000000000000000"
	C_FAMILY = "nofamily"
Entity <pselect_f.1> analyzed. Unit <pselect_f.1> generated.

Analyzing generic Entity <pselect_f.2> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 1
	C_AW = 1
	C_BAR = "0"
	C_FAMILY = "nofamily"
Entity <pselect_f.2> analyzed. Unit <pselect_f.2> generated.

Analyzing generic Entity <pselect_f.3> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 1
	C_AW = 1
	C_BAR = "1"
	C_FAMILY = "nofamily"
Entity <pselect_f.3> analyzed. Unit <pselect_f.3> generated.

Analyzing generic Entity <pselect_f.4> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 24
	C_AW = 32
	C_BAR = "11000000101000000000000100000000"
	C_FAMILY = "nofamily"
Entity <pselect_f.4> analyzed. Unit <pselect_f.4> generated.

Analyzing generic Entity <pselect_f.5> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "0000"
	C_FAMILY = "nofamily"
Entity <pselect_f.5> analyzed. Unit <pselect_f.5> generated.

Analyzing generic Entity <pselect_f.6> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "0001"
	C_FAMILY = "nofamily"
Entity <pselect_f.6> analyzed. Unit <pselect_f.6> generated.

Analyzing generic Entity <pselect_f.7> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "0010"
	C_FAMILY = "nofamily"
Entity <pselect_f.7> analyzed. Unit <pselect_f.7> generated.

Analyzing generic Entity <pselect_f.8> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "0011"
	C_FAMILY = "nofamily"
Entity <pselect_f.8> analyzed. Unit <pselect_f.8> generated.

Analyzing generic Entity <pselect_f.9> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "0100"
	C_FAMILY = "nofamily"
Entity <pselect_f.9> analyzed. Unit <pselect_f.9> generated.

Analyzing generic Entity <pselect_f.10> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "0101"
	C_FAMILY = "nofamily"
Entity <pselect_f.10> analyzed. Unit <pselect_f.10> generated.

Analyzing generic Entity <pselect_f.11> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "0110"
	C_FAMILY = "nofamily"
Entity <pselect_f.11> analyzed. Unit <pselect_f.11> generated.

Analyzing generic Entity <pselect_f.12> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "0111"
	C_FAMILY = "nofamily"
Entity <pselect_f.12> analyzed. Unit <pselect_f.12> generated.

Analyzing generic Entity <pselect_f.13> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "1000"
	C_FAMILY = "nofamily"
Entity <pselect_f.13> analyzed. Unit <pselect_f.13> generated.

Analyzing generic Entity <pselect_f.14> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "1001"
	C_FAMILY = "nofamily"
Entity <pselect_f.14> analyzed. Unit <pselect_f.14> generated.

Analyzing generic Entity <pselect_f.15> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "1010"
	C_FAMILY = "nofamily"
Entity <pselect_f.15> analyzed. Unit <pselect_f.15> generated.

Analyzing generic Entity <pselect_f.16> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "1011"
	C_FAMILY = "nofamily"
Entity <pselect_f.16> analyzed. Unit <pselect_f.16> generated.

Analyzing generic Entity <pselect_f.17> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "1100"
	C_FAMILY = "nofamily"
Entity <pselect_f.17> analyzed. Unit <pselect_f.17> generated.

Analyzing generic Entity <pselect_f.18> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "1101"
	C_FAMILY = "nofamily"
Entity <pselect_f.18> analyzed. Unit <pselect_f.18> generated.

Analyzing generic Entity <pselect_f.19> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "1110"
	C_FAMILY = "nofamily"
Entity <pselect_f.19> analyzed. Unit <pselect_f.19> generated.

Analyzing generic Entity <pselect_f.20> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 4
	C_AW = 4
	C_BAR = "1111"
	C_FAMILY = "nofamily"
Entity <pselect_f.20> analyzed. Unit <pselect_f.20> generated.

Analyzing generic Entity <or_gate128> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 2
	C_USE_LUT_OR = false
Entity <or_gate128> analyzed. Unit <or_gate128> generated.

Analyzing generic Entity <or_muxcy> in library <proc_common_v3_00_a> (Architecture <implementation>).
	C_NUM_BITS = 2
Entity <or_muxcy> analyzed. Unit <or_muxcy> generated.

Analyzing generic Entity <counter_f> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_FAMILY = "nofamily"
	C_NUM_BITS = 8
Entity <counter_f> analyzed. Unit <counter_f> generated.

Analyzing generic Entity <interrupt_control> in library <interrupt_control_v2_01_a> (Architecture <implementation>).
	C_INCLUDE_DEV_ISC = true
	C_INCLUDE_DEV_PENCODER = true
	C_IPIF_DWIDTH = 32
	C_IP_INTR_MODE_ARRAY = (1)
	C_NUM_CE = 16
	C_NUM_IPIF_IRPT_SRC = 4
Entity <interrupt_control> analyzed. Unit <interrupt_control> generated.

Analyzing generic Entity <user_logic> in library <my_timer_v1_00_a> (Architecture <IMP>).
	C_NUM_INTR = 1
	C_NUM_REG = 2
	C_SLV_DWIDTH = 32
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:819 - "C:/Temp/Bomberman/pcores/my_timer_v1_00_a/hdl/vhdl/user_logic.vhd" line 244: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <timer_expired>
Entity <user_logic> analyzed. Unit <user_logic> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <interrupt_control>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd".
WARNING:Xst:647 - Input <Bus2IP_Data<1:24>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_BE<1:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_RdCE<3:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_RdCE<9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_RdCE<11:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_WrCE<1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_WrCE<3:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_WrCE<9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Interrupt_WrCE<11:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <ipif_pri_encode_present> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <Intr2Bus_WrAck>.
    Found 1-bit register for signal <Intr2Bus_RdAck>.
    Found 1-bit register for signal <ip_irpt_enable_reg<0>>.
    Found 1-bit register for signal <ipif_glbl_irpt_enable_reg>.
    Found 7-bit register for signal <ipif_irpt_enable_reg>.
    Found 2-bit register for signal <ipif_irpt_status_reg>.
    Found 1-bit xor2 for signal <ipif_irpt_status_reg_0$xor0000> created at line 885.
    Found 1-bit xor2 for signal <ipif_irpt_status_reg_1$xor0000> created at line 885.
    Found 1-bit register for signal <irpt_rdack_d1>.
    Found 1-bit register for signal <irpt_wrack_d1>.
    Summary:
	inferred  15 D-type flip-flop(s).
Unit <interrupt_control> synthesized.


Synthesizing Unit <user_logic>.
    Related source file is "C:/Temp/Bomberman/pcores/my_timer_v1_00_a/hdl/vhdl/user_logic.vhd".
WARNING:Xst:646 - Signal <slv_reg1<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <intr_counter> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found 32-bit 4-to-1 multiplexer for signal <slv_ip2bus_data>.
    Found 32-bit register for signal <slv_reg0>.
    Found 31-bit register for signal <slv_reg1<1:31>>.
    Found 32-bit down counter for signal <timer_count>.
    Found 1-bit register for signal <timer_expired>.
    Summary:
	inferred   1 Counter(s).
	inferred  64 D-type flip-flop(s).
	inferred  32 Multiplexer(s).
Unit <user_logic> synthesized.


Synthesizing Unit <counter_f>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd".
    Found 9-bit register for signal <icount_out>.
    Found 9-bit subtractor for signal <icount_out$sub0000> created at line 297.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <counter_f> synthesized.


Synthesizing Unit <pselect_f_1>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
WARNING:Xst:647 - Input <A<24:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <pselect_f_1> synthesized.


Synthesizing Unit <pselect_f_2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_2> synthesized.


Synthesizing Unit <pselect_f_3>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_3> synthesized.


Synthesizing Unit <pselect_f_4>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
WARNING:Xst:647 - Input <A<24:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <pselect_f_4> synthesized.


Synthesizing Unit <pselect_f_5>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_5> synthesized.


Synthesizing Unit <pselect_f_6>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_6> synthesized.


Synthesizing Unit <pselect_f_7>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_7> synthesized.


Synthesizing Unit <pselect_f_8>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_8> synthesized.


Synthesizing Unit <pselect_f_9>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_9> synthesized.


Synthesizing Unit <pselect_f_10>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_10> synthesized.


Synthesizing Unit <pselect_f_11>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_11> synthesized.


Synthesizing Unit <pselect_f_12>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_12> synthesized.


Synthesizing Unit <pselect_f_13>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_13> synthesized.


Synthesizing Unit <pselect_f_14>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_14> synthesized.


Synthesizing Unit <pselect_f_15>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_15> synthesized.


Synthesizing Unit <pselect_f_16>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_16> synthesized.


Synthesizing Unit <pselect_f_17>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_17> synthesized.


Synthesizing Unit <pselect_f_18>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_18> synthesized.


Synthesizing Unit <pselect_f_19>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_19> synthesized.


Synthesizing Unit <pselect_f_20>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_20> synthesized.


Synthesizing Unit <or_muxcy>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd".
Unit <or_muxcy> synthesized.


Synthesizing Unit <or_gate128>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <or_gate128> synthesized.


Synthesizing Unit <plb_address_decoder>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_address_decoder.vhd".
WARNING:Xst:647 - Input <Bus_RNW_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Address_In_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Address_Valid_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <cs_s_h_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <cs_out_s_h0<0>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <cs_out_s_h<1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cs_ce_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr_out_s_h<4:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr_match_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 6-bit register for signal <addr_out_s_h>.
    Found 2-bit register for signal <cs_out_i>.
    Found 1-bit register for signal <cs_out_s_h<0>>.
    Found 1-bit register for signal <cs_out_s_h0<1>>.
    Found 1-bit register for signal <decode_hit_reg>.
    Found 18-bit register for signal <rdce_out_i>.
    Found 1-bit register for signal <rnw_s_h>.
    Found 18-bit register for signal <wrce_out_i>.
    Summary:
	inferred  48 D-type flip-flop(s).
Unit <plb_address_decoder> synthesized.


Synthesizing Unit <plb_slave_attachment>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd".
WARNING:Xst:647 - Input <PLB_UABus> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <valid_plb_type> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <valid_plb_size> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <start_data_phase> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wrdack_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wrcomp_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wait_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_rddack_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_rdcomp_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_data_ack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <set_sl_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd_ce_ld_enable> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_rd_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_rd_busy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_rd_ce> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Register <sl_rdcomp_i> equivalent to <rd_clear_sl_busy> has been removed
    Register <sl_rddack_i> equivalent to <rd_clear_sl_busy> has been removed
    Register <sl_addrack_i> equivalent to <set_sl_busy> has been removed
    Register <sl_wrdack_i> equivalent to <sl_wrcomp_i> has been removed
    Register <wr_clear_sl_busy> equivalent to <sl_wrcomp_i> has been removed
    Found 1-bit register for signal <addr_cntl_cs<0>>.
    Found 1-bit register for signal <addr_cycle_flush>.
    Found 32-bit register for signal <bus2ip_addr_i>.
    Found 4-bit register for signal <bus2ip_be_i>.
    Found 1-bit register for signal <bus2ip_rnw_i>.
    Found 1-bit register for signal <data_timeout>.
    Found 1-bit register for signal <master_id<31>>.
    Found 32-bit register for signal <plb_abus_reg>.
    Found 4-bit register for signal <plb_be_reg>.
    Found 1-bit register for signal <plb_masterid_reg<0>>.
    Found 1-bit register for signal <plb_pavalid_reg>.
    Found 1-bit register for signal <plb_rnw_reg>.
    Found 4-bit register for signal <plb_size_reg>.
    Found 3-bit register for signal <plb_type_reg>.
    Found 32-bit register for signal <plb_wrdbus_reg>.
    Found 1-bit register for signal <rd_clear_sl_busy>.
    Found 1-bit register for signal <set_sl_busy>.
    Found 1-bit register for signal <sl_busy>.
    Found 2-bit register for signal <sl_mbusy_i>.
    Found 2-bit register for signal <sl_mrderr_i>.
    Found 2-bit register for signal <sl_mwrerr_i>.
    Found 32-bit register for signal <sl_rddbus_i>.
    Found 1-bit register for signal <sl_rearbitrate_i>.
    Found 1-bit register for signal <sl_wrcomp_i>.
    Summary:
	inferred 162 D-type flip-flop(s).
Unit <plb_slave_attachment> synthesized.


Synthesizing Unit <plbv46_slave_single>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plbv46_slave_single.vhd".
WARNING:Xst:647 - Input <PLB_wrPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_MSize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdBurst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_SAValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_busLock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_reqPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_lockErr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrBurst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_TAttribute> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_abort> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <plbv46_slave_single> synthesized.


Synthesizing Unit <my_timer>.
    Related source file is "C:/Temp/Bomberman/pcores/my_timer_v1_00_a/hdl/vhdl/my_timer.vhd".
WARNING:Xst:646 - Signal <ipif_Bus2IP_RNW> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ipif_Bus2IP_Addr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 32-bit 4-to-1 multiplexer for signal <ipif_IP2Bus_Data>.
    Summary:
	inferred  32 Multiplexer(s).
Unit <my_timer> synthesized.


Synthesizing Unit <my_timer_0_wrapper>.
    Related source file is "C:/Temp/Bomberman/hdl/my_timer_0_wrapper.vhd".
Unit <my_timer_0_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 9-bit subtractor                                      : 1
# Counters                                             : 1
 32-bit down counter                                   : 1
# Registers                                            : 144
 1-bit register                                        : 133
 3-bit register                                        : 1
 32-bit register                                       : 4
 4-bit register                                        : 3
 6-bit register                                        : 1
 7-bit register                                        : 1
 9-bit register                                        : 1
# Multiplexers                                         : 33
 1-bit 4-to-1 multiplexer                              : 32
 32-bit 4-to-1 multiplexer                             : 1
# Xors                                                 : 2
 1-bit xor2                                            : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:2677 - Node <addr_out_s_h_5> of sequential type is unconnected in block <plb_address_decoder>.
WARNING:Xst:2677 - Node <addr_out_s_h_4> of sequential type is unconnected in block <plb_address_decoder>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 9-bit subtractor                                      : 1
# Counters                                             : 1
 32-bit down counter                                   : 1
# Registers                                            : 296
 Flip-Flops                                            : 296
# Multiplexers                                         : 33
 1-bit 4-to-1 multiplexer                              : 32
 32-bit 4-to-1 multiplexer                             : 1
# Xors                                                 : 2
 1-bit xor2                                            : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch <addr_cntl_cs_0> in Unit <plb_slave_attachment> is equivalent to the following FF/Latch, which will be removed : <addr_cycle_flush> 

Optimizing unit <my_timer_0_wrapper> ...

Optimizing unit <interrupt_control> ...

Optimizing unit <user_logic> ...

Optimizing unit <counter_f> ...

Optimizing unit <plb_address_decoder> ...

Optimizing unit <plb_slave_attachment> ...
WARNING:Xst:1710 - FF/Latch <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_mrderr_i_1> (without init value) has a constant value of 0 in block <my_timer_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_mrderr_i_0> (without init value) has a constant value of 0 in block <my_timer_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_mwrerr_i_1> (without init value) has a constant value of 0 in block <my_timer_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_mwrerr_i_0> (without init value) has a constant value of 0 in block <my_timer_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_3> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_5> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_6> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_7> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_8> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_11> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_5> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_6> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_13> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_7> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_14> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_15> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_16> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_17> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_11> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_13> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_14> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_15> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_16> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_17> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_0> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_1> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_2> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_3> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_4> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_5> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_6> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_7> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_8> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_9> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_10> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_11> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_12> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_13> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_14> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_15> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_16> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_17> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_18> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_19> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_20> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_21> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_22> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_23> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_24> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_25> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_26> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_27> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_28> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_29> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_30> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_31> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_24> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_25> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_30> of sequential type is unconnected in block <my_timer_0_wrapper>.
WARNING:Xst:2677 - Node <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_31> of sequential type is unconnected in block <my_timer_0_wrapper>.

Mapping all equations...
Building and optimizing final netlist ...
FlipFlop my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 268
 Flip-Flops                                            : 268

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/my_timer_0_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 202

Cell Usage :
# BELS                             : 301
#      GND                         : 1
#      INV                         : 3
#      LUT2                        : 23
#      LUT2_L                      : 5
#      LUT3                        : 90
#      LUT3_D                      : 2
#      LUT3_L                      : 2
#      LUT4                        : 65
#      LUT4_D                      : 2
#      LUT4_L                      : 29
#      MUXCY                       : 46
#      VCC                         : 1
#      XORCY                       : 32
# FlipFlops/Latches                : 268
#      FD                          : 1
#      FDCE                        : 32
#      FDP                         : 1
#      FDR                         : 116
#      FDRE                        : 107
#      FDRS                        : 4
#      FDS                         : 7
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                      191  out of   8672     2%  
 Number of Slice Flip Flops:            268  out of  17344     1%  
 Number of 4 input LUTs:                221  out of  17344     1%  
 Number of IOs:                         202
 Number of bonded IOBs:                   0  out of    250     0%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                      | Load  |
-----------------------------------+------------------------------------------------------------+-------+
SPLB_Clk                           | NONE(my_timer_0/INTERRUPT_CONTROL_I/ipif_irpt_enable_reg_6)| 268   |
-----------------------------------+------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
SPLB_Rst                           | NONE                   | 33    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 6.980ns (Maximum Frequency: 143.276MHz)
   Minimum input arrival time before clock: 3.052ns
   Maximum output required time after clock: 3.306ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'SPLB_Clk'
  Clock period: 6.980ns (frequency: 143.276MHz)
  Total number of paths / destination ports: 4542 / 410
-------------------------------------------------------------------------
Delay:               6.980ns (Levels of Logic = 3)
  Source:            my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_1 (FF)
  Destination:       my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0 (FF)
  Source Clock:      SPLB_Clk rising
  Destination Clock: SPLB_Clk rising

  Data Path: my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_1 to my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            33   0.591   1.298  my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_1 (my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_1)
     LUT3:I2->O            6   0.704   0.704  my_timer_0/ipif_IP2Bus_RdAck1 (my_timer_0/ipif_IP2Bus_RdAck)
     LUT3:I2->O            2   0.704   0.482  my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/data_ack1 (my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/data_ack)
     LUT3:I2->O           10   0.704   0.882  my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_clr1 (my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_clr)
     FDRE:R                    0.911          my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0
    ----------------------------------------
    Total                      6.980ns (3.614ns logic, 3.366ns route)
                                       (51.8% logic, 48.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SPLB_Clk'
  Total number of paths / destination ports: 300 / 300
-------------------------------------------------------------------------
Offset:              3.052ns (Levels of Logic = 1)
  Source:            SPLB_Rst (PAD)
  Destination:       my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_0 (FF)
  Destination Clock: SPLB_Clk rising

  Data Path: SPLB_Rst to my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I0->O           32   0.704   1.262  my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_or00001 (my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_or0000)
     FDR:R                     0.911          my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_29
    ----------------------------------------
    Total                      3.052ns (1.790ns logic, 1.262ns route)
                                       (58.6% logic, 41.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'SPLB_Clk'
  Total number of paths / destination ports: 48 / 41
-------------------------------------------------------------------------
Offset:              3.306ns (Levels of Logic = 2)
  Source:            my_timer_0/INTERRUPT_CONTROL_I/ipif_irpt_enable_reg_1 (FF)
  Destination:       IP2INTC_Irpt (PAD)
  Source Clock:      SPLB_Clk rising

  Data Path: my_timer_0/INTERRUPT_CONTROL_I/ipif_irpt_enable_reg_1 to IP2INTC_Irpt
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             5   0.591   0.808  my_timer_0/INTERRUPT_CONTROL_I/ipif_irpt_enable_reg_1 (my_timer_0/INTERRUPT_CONTROL_I/ipif_irpt_enable_reg_1)
     LUT4:I0->O            1   0.704   0.499  my_timer_0/INTERRUPT_CONTROL_I/ipif_interrupt4 (my_timer_0/INTERRUPT_CONTROL_I/ipif_interrupt4)
     LUT3:I1->O            0   0.704   0.000  my_timer_0/INTERRUPT_CONTROL_I/ipif_interrupt15 (IP2INTC_Irpt)
    ----------------------------------------
    Total                      3.306ns (1.999ns logic, 1.307ns route)
                                       (60.5% logic, 39.5% route)

=========================================================================


Total REAL time to Xst completion: 32.00 secs
Total CPU time to Xst completion: 32.53 secs
 
--> 

Total memory usage is 283768 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  133 (   0 filtered)
Number of infos    :    2 (   0 filtered)

