Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_xst.prj"
Verilog Include Directory          : {"C:\Temp\Bomberman\pcores\" "C:\Xilinx\12.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc3s1200efg320-4
Output File Name                   : "../implementation/system.ngc"

---- Source Options
Top Module Name                    : system

---- Target Options
Add IO Buffers                     : NO
Global Maximum Fanout              : 10000

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Temp/Bomberman/hdl/system.vhd" in Library work.
Entity <system> compiled.
Entity <system> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <system> in library <work> (architecture <STRUCTURE>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <system> in library <work> (Architecture <STRUCTURE>).
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'MB_Halted' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Instruction' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Valid_Instr' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_PC' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Reg_Write' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Reg_Addr' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_MSR_Reg' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_PID_Reg' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_New_Reg_Value' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Exception_Taken' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Exception_Kind' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Jump_Taken' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Delay_Slot' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Data_Address' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Data_Access' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Data_Read' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Data_Write' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Data_Write_Value' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Data_Byte_Enable' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_DCache_Req' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_DCache_Hit' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_DCache_Rdy' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_DCache_Read' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_ICache_Req' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_ICache_Hit' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_ICache_Rdy' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_OF_PipeRun' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_EX_PipeRun' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_MEM_PipeRun' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_MB_Halted' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'Trace_Jump_Hit' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL0_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL0_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL0_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL0_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL0_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL0_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL1_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL1_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL1_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL1_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL1_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL1_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL2_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL2_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL2_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL2_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL2_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL2_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL3_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL3_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL3_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL3_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL3_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL3_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL4_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL4_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL4_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL4_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL4_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL4_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL5_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL5_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL5_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL5_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL5_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL5_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL6_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL6_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL6_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL6_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL6_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL6_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL7_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL7_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL7_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL7_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL7_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL7_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL8_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL8_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL8_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL8_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL8_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL8_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL9_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL9_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL9_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL9_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL9_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL9_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL10_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL10_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL10_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL10_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL10_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL10_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL11_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL11_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL11_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL11_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL11_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL11_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL12_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL12_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL12_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL12_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL12_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL12_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL13_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL13_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL13_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL13_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL13_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL13_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL14_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL14_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL14_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL14_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL14_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL14_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL15_S_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL15_S_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL15_M_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL15_M_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL15_M_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'FSL15_M_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'ICACHE_FSL_IN_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'ICACHE_FSL_IN_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'ICACHE_FSL_OUT_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'ICACHE_FSL_OUT_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'ICACHE_FSL_OUT_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'ICACHE_FSL_OUT_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'DCACHE_FSL_IN_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'DCACHE_FSL_IN_READ' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'DCACHE_FSL_OUT_CLK' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'DCACHE_FSL_OUT_WRITE' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'DCACHE_FSL_OUT_DATA' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1602: Unconnected output port 'DCACHE_FSL_OUT_CONTROL' of component 'microblaze_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_Rst' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'MPLB_Rst' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_dcrAck' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_dcrDBus' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SaddrAck' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SMRdErr' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SMWrErr' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SMBusy' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SrdBTerm' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SrdComp' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SrdDAck' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SrdDBus' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SrdWdAddr' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_Srearbitrate' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_Sssize' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_Swait' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SwrBTerm' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SwrComp' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'PLB_SwrDAck' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 1907: Unconnected output port 'Bus_Error_Det' of component 'mb_plb_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2114: Unconnected output port 'IP2INTC_Irpt' of component 'leds_8bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2114: Unconnected output port 'GPIO_IO_T' of component 'leds_8bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2114: Unconnected output port 'GPIO2_IO_O' of component 'leds_8bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2114: Unconnected output port 'GPIO2_IO_T' of component 'leds_8bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2167: Unconnected output port 'IP2INTC_Irpt' of component 'led_7segment_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2167: Unconnected output port 'GPIO_IO_T' of component 'led_7segment_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2167: Unconnected output port 'GPIO2_IO_O' of component 'led_7segment_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2167: Unconnected output port 'GPIO2_IO_T' of component 'led_7segment_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2220: Unconnected output port 'IP2INTC_Irpt' of component 'push_buttons_3bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2220: Unconnected output port 'GPIO_IO_O' of component 'push_buttons_3bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2220: Unconnected output port 'GPIO_IO_T' of component 'push_buttons_3bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2220: Unconnected output port 'GPIO2_IO_O' of component 'push_buttons_3bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2220: Unconnected output port 'GPIO2_IO_T' of component 'push_buttons_3bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2273: Unconnected output port 'IP2INTC_Irpt' of component 'switches_8bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2273: Unconnected output port 'GPIO_IO_O' of component 'switches_8bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2273: Unconnected output port 'GPIO_IO_T' of component 'switches_8bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2273: Unconnected output port 'GPIO2_IO_O' of component 'switches_8bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2273: Unconnected output port 'GPIO2_IO_T' of component 'switches_8bit_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2326: Unconnected output port 'Interrupt' of component 'rs232_port_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH0_Access_Full' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH0_ReadData_Control' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH0_ReadData_Data' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH0_ReadData_Exists' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH1_Access_Full' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH1_ReadData_Control' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH1_ReadData_Data' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH1_ReadData_Exists' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH2_Access_Full' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH2_ReadData_Control' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH2_ReadData_Data' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH2_ReadData_Exists' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH3_Access_Full' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH3_ReadData_Control' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH3_ReadData_Data' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'MCH3_ReadData_Exists' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'Mem_RPN' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'Mem_CEN' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'Mem_QWEN' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'Mem_CE' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'Mem_ADV_LDN' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'Mem_LBON' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'Mem_CKEN' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2375: Unconnected output port 'Mem_RNW' of component 'micron_ram_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2469: Unconnected output port 'GenerateOut0' of component 'xps_timer_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2469: Unconnected output port 'GenerateOut1' of component 'xps_timer_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2469: Unconnected output port 'PWM0' of component 'xps_timer_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2469: Unconnected output port 'Interrupt' of component 'xps_timer_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT1' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT2' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT3' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT4' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT5' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT6' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT7' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT8' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT9' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT10' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT11' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT12' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT13' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT14' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKOUT15' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'CLKFBOUT' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2522: Unconnected output port 'PSDONE' of component 'clock_generator_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Interrupt' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'MDM_DBus' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'MDM_errAck' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'MDM_retry' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'MDM_toutSup' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'MDM_xferAck' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Clk_1' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_TDI_1' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Reg_En_1' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Capture_1' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Shift_1' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Update_1' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Rst_1' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Clk_2' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_TDI_2' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Reg_En_2' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Capture_2' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Shift_2' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Update_2' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Rst_2' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Clk_3' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_TDI_3' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Reg_En_3' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Capture_3' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Shift_3' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Update_3' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Rst_3' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Clk_4' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_TDI_4' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Reg_En_4' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Capture_4' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Shift_4' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Update_4' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Rst_4' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Clk_5' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_TDI_5' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Reg_En_5' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Capture_5' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Shift_5' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Update_5' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Rst_5' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Clk_6' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_TDI_6' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Reg_En_6' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Capture_6' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Shift_6' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Update_6' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Rst_6' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Clk_7' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_TDI_7' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Reg_En_7' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Capture_7' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Shift_7' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Update_7' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Dbg_Rst_7' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'bscan_tdi' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'bscan_reset' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'bscan_shift' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'bscan_update' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'bscan_capture' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'bscan_sel1' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'bscan_drck1' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'FSL0_S_CLK' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'FSL0_S_READ' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'FSL0_M_CLK' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'FSL0_M_WRITE' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'FSL0_M_DATA' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'FSL0_M_CONTROL' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Ext_JTAG_DRCK' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Ext_JTAG_RESET' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Ext_JTAG_SEL' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Ext_JTAG_CAPTURE' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Ext_JTAG_SHIFT' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Ext_JTAG_UPDATE' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2551: Unconnected output port 'Ext_JTAG_TDI' of component 'mdm_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2704: Unconnected output port 'RstcPPCresetcore_0' of component 'proc_sys_reset_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2704: Unconnected output port 'RstcPPCresetchip_0' of component 'proc_sys_reset_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2704: Unconnected output port 'RstcPPCresetsys_0' of component 'proc_sys_reset_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2704: Unconnected output port 'RstcPPCresetcore_1' of component 'proc_sys_reset_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2704: Unconnected output port 'RstcPPCresetchip_1' of component 'proc_sys_reset_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2704: Unconnected output port 'RstcPPCresetsys_1' of component 'proc_sys_reset_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2704: Unconnected output port 'Peripheral_Reset' of component 'proc_sys_reset_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2728: Unconnected output port 'IP2INTC_Irpt_2' of component 'xps_ps2_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2728: Unconnected output port 'PS2_2_DATA_O' of component 'xps_ps2_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2728: Unconnected output port 'PS2_2_DATA_T' of component 'xps_ps2_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2728: Unconnected output port 'PS2_2_CLK_O' of component 'xps_ps2_0_wrapper'.
WARNING:Xst:753 - "C:/Temp/Bomberman/hdl/system.vhd" line 2728: Unconnected output port 'PS2_2_CLK_T' of component 'xps_ps2_0_wrapper'.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 2932: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 2940: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 2948: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 2956: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 2964: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 2972: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 2980: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 2988: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 2996: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 3004: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 3012: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 3020: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 3028: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 3036: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 3044: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 3052: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 3060: Instantiating black box module <IOBUF>.
WARNING:Xst:2211 - "C:/Temp/Bomberman/hdl/system.vhd" line 3068: Instantiating black box module <IOBUF>.
Entity <system> analyzed. Unit <system> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <system>.
    Related source file is "C:/Temp/Bomberman/hdl/system.vhd".
WARNING:Xst:646 - Signal <pgassign3<0:8>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <pgassign2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <system> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <../implementation/microblaze_0_wrapper.ngc>.
Reading core <../implementation/mb_plb_wrapper.ngc>.
Reading core <../implementation/ilmb_wrapper.ngc>.
Reading core <../implementation/dlmb_wrapper.ngc>.
Reading core <../implementation/dlmb_cntlr_wrapper.ngc>.
Reading core <../implementation/ilmb_cntlr_wrapper.ngc>.
Reading core <../implementation/lmb_bram_wrapper.ngc>.
Reading core <../implementation/leds_8bit_wrapper.ngc>.
Reading core <../implementation/led_7segment_wrapper.ngc>.
Reading core <../implementation/push_buttons_3bit_wrapper.ngc>.
Reading core <../implementation/switches_8bit_wrapper.ngc>.
Reading core <../implementation/rs232_port_wrapper.ngc>.
Reading core <../implementation/micron_ram_wrapper.ngc>.
Reading core <../implementation/xps_timer_0_wrapper.ngc>.
Reading core <../implementation/clock_generator_0_wrapper.ngc>.
Reading core <../implementation/mdm_0_wrapper.ngc>.
Reading core <../implementation/proc_sys_reset_0_wrapper.ngc>.
Reading core <../implementation/xps_ps2_0_wrapper.ngc>.
Reading core <../implementation/xps_intc_0_wrapper.ngc>.
Reading core <../implementation/my_timer_0_wrapper.ngc>.
Reading core <../implementation/graph_acc_0_wrapper.ngc>.
Loading core <microblaze_0_wrapper> for timing and area information for instance <microblaze_0>.
Loading core <mb_plb_wrapper> for timing and area information for instance <mb_plb>.
Loading core <ilmb_wrapper> for timing and area information for instance <ilmb>.
Loading core <dlmb_wrapper> for timing and area information for instance <dlmb>.
Loading core <dlmb_cntlr_wrapper> for timing and area information for instance <dlmb_cntlr>.
Loading core <ilmb_cntlr_wrapper> for timing and area information for instance <ilmb_cntlr>.
Loading core <lmb_bram_wrapper> for timing and area information for instance <lmb_bram>.
Loading core <leds_8bit_wrapper> for timing and area information for instance <LEDs_8Bit>.
Loading core <led_7segment_wrapper> for timing and area information for instance <LED_7SEGMENT>.
Loading core <push_buttons_3bit_wrapper> for timing and area information for instance <Push_Buttons_3Bit>.
Loading core <switches_8bit_wrapper> for timing and area information for instance <Switches_8Bit>.
Loading core <rs232_port_wrapper> for timing and area information for instance <RS232_PORT>.
Loading core <micron_ram_wrapper> for timing and area information for instance <Micron_RAM>.
Loading core <xps_timer_0_wrapper> for timing and area information for instance <xps_timer_0>.
Loading core <clock_generator_0_wrapper> for timing and area information for instance <clock_generator_0>.
Loading core <mdm_0_wrapper> for timing and area information for instance <mdm_0>.
Loading core <proc_sys_reset_0_wrapper> for timing and area information for instance <proc_sys_reset_0>.
Loading core <xps_ps2_0_wrapper> for timing and area information for instance <xps_ps2_0>.
Loading core <xps_intc_0_wrapper> for timing and area information for instance <xps_intc_0>.
Loading core <my_timer_0_wrapper> for timing and area information for instance <my_timer_0>.
Loading core <graph_acc_0_wrapper> for timing and area information for instance <graph_acc_0>.

=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <system> ...

Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd2> in Unit <mb_plb> is equivalent to the following FF/Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd2_1> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_MPLB_RST[1].I_MPLB_RST> in Unit <mb_plb> is equivalent to the following 14 FFs/Latches : <mb_plb/GEN_MPLB_RST[0].I_MPLB_RST> <mb_plb/GEN_SPLB_RST[11].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[10].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[9].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[8].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[7].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[6].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[5].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[4].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[3].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[2].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[1].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[0].I_SPLB_RST> <mb_plb/I_PLB_RST> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3> in Unit <mb_plb> is equivalent to the following FF/Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3_1> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1> in Unit <mb_plb> is equivalent to the following 3 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_2> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_3> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0> in Unit <mb_plb> is equivalent to the following 3 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_2> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_3> 
INFO:Xst:2260 - The FF/Latch <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN2> in Unit <Micron_RAM> is equivalent to the following FF/Latch : <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN1> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_5> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_5_1> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2_1> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[21].TCSR0_FF_I> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[21].TCSR1_FF_I> 
INFO:Xst:2260 - The FF/Latch <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0> in Unit <my_timer_0> is equivalent to the following FF/Latch : <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_26> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_26_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_26_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_31> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_31_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_13> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_13_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_13_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_1> in Unit <graph_acc_0> is equivalent to the following 3 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_1_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_1_2> <graph_acc_0/USER_LOGIC_I/slv_reg0_1_3> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_27> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_27_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_14> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_14_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_28> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_28_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_20> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_20_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_20_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_15> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_15_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_15_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_21> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_21_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_21_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_10> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_10_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_24> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_24_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_24_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_11> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_11_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/VGA_ctrl/vcounter_5> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/VGA_ctrl/vcounter_5_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_25> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_25_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_25_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_12> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_12_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_12_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_0> in Unit <graph_acc_0> is equivalent to the following 3 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_0_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_0_2> <graph_acc_0/USER_LOGIC_I/slv_reg0_0_3> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0> in Unit <mb_plb> is equivalent to the following 3 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_2> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_3> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd2> in Unit <mb_plb> is equivalent to the following FF/Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd2_1> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1> in Unit <mb_plb> is equivalent to the following 3 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_2> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_3> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3> in Unit <mb_plb> is equivalent to the following FF/Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3_1> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_MPLB_RST[1].I_MPLB_RST> in Unit <mb_plb> is equivalent to the following 14 FFs/Latches : <mb_plb/GEN_MPLB_RST[0].I_MPLB_RST> <mb_plb/GEN_SPLB_RST[11].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[10].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[9].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[8].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[7].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[6].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[5].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[4].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[3].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[2].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[1].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[0].I_SPLB_RST> <mb_plb/I_PLB_RST> 
INFO:Xst:2260 - The FF/Latch <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN2> in Unit <Micron_RAM> is equivalent to the following FF/Latch : <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN1> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_5> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_5_1> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR0_GENERATE[21].TCSR0_FF_I> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/TC_CORE_I/TIMER_CONTROL_I/TCSR1_GENERATE[21].TCSR1_FF_I> 
INFO:Xst:2260 - The FF/Latch <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2> in Unit <xps_timer_0> is equivalent to the following FF/Latch : <xps_timer_0/PLBv46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2_1> 
INFO:Xst:2260 - The FF/Latch <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0> in Unit <my_timer_0> is equivalent to the following FF/Latch : <my_timer_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_1> in Unit <graph_acc_0> is equivalent to the following 3 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_1_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_1_2> <graph_acc_0/USER_LOGIC_I/slv_reg0_1_3> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_24> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_24_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_24_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/VGA_ctrl/vcounter_5> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/VGA_ctrl/vcounter_5_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_25> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_25_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_25_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_10> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_10_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_26> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_26_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_26_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_31> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_31_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_11> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_11_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_27> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_27_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_12> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_12_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_12_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_28> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_28_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_13> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_13_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_13_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_14> in Unit <graph_acc_0> is equivalent to the following FF/Latch : <graph_acc_0/USER_LOGIC_I/slv_reg0_14_1> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_15> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_15_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_15_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_20> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_20_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_20_2> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_0> in Unit <graph_acc_0> is equivalent to the following 3 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_0_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_0_2> <graph_acc_0/USER_LOGIC_I/slv_reg0_0_3> 
INFO:Xst:2260 - The FF/Latch <graph_acc_0/USER_LOGIC_I/slv_reg0_21> in Unit <graph_acc_0> is equivalent to the following 2 FFs/Latches : <graph_acc_0/USER_LOGIC_I/slv_reg0_21_1> <graph_acc_0/USER_LOGIC_I/slv_reg0_21_2> 

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/system.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 90

Cell Usage :
# BELS                             : 12134
#      GND                         : 22
#      INV                         : 101
#      LUT1                        : 128
#      LUT2                        : 658
#      LUT2_D                      : 264
#      LUT2_L                      : 27
#      LUT3                        : 1647
#      LUT3_D                      : 255
#      LUT3_L                      : 74
#      LUT4                        : 5648
#      LUT4_D                      : 266
#      LUT4_L                      : 885
#      MULT_AND                    : 68
#      MUXCY                       : 623
#      MUXCY_L                     : 220
#      MUXF5                       : 532
#      MUXF6                       : 138
#      MUXF7                       : 66
#      MUXF8                       : 33
#      VCC                         : 18
#      XORCY                       : 461
# FlipFlops/Latches                : 4829
#      FD                          : 321
#      FDC                         : 21
#      FDC_1                       : 5
#      FDCE                        : 46
#      FDE                         : 1340
#      FDE_1                       : 5
#      FDP                         : 10
#      FDR                         : 1496
#      FDRE                        : 1118
#      FDRE_1                      : 1
#      FDRS                        : 60
#      FDRSE                       : 130
#      FDS                         : 172
#      FDSE                        : 104
# RAMS                             : 147
#      RAM16X1D                    : 128
#      RAMB16_S2_S2                : 16
#      RAMB16_S4_S4                : 2
#      RAMB16_S9_S9                : 1
# Shift Registers                  : 195
#      SRL16                       : 40
#      SRL16E                      : 147
#      SRLC16E                     : 8
# Clock Buffers                    : 4
#      BUFG                        : 4
# IO Buffers                       : 18
#      IOBUF                       : 18
# DCMs                             : 1
#      DCM_SP                      : 1
# MULTs                            : 3
#      MULT18X18SIO                : 3
# Others                           : 1
#      BSCAN_SPARTAN3              : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                     6182  out of   8672    71%  
 Number of Slice Flip Flops:           4797  out of  17344    27%  
 Number of 4 input LUTs:              10404  out of  17344    59%  
    Number used as logic:              9953
    Number used as Shift registers:     195
    Number used as RAMs:                256
 Number of IOs:                          90
 Number of bonded IOBs:                  18  out of    250     7%  
    IOB Flip Flops:                      32
 Number of BRAMs:                        19  out of     28    67%  
 Number of MULT18X18SIOs:                 3  out of     28    10%  
 Number of GCLKs:                         4  out of     24    16%  
 Number of DCMs:                          1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal                                           | Clock buffer(FF name)                                                                                                             | Load  |
-------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------+
fpga_0_clk_1_sys_clk_pin                               | clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST:CLK0                                                                            | 4934  |
mdm_0/mdm_0/drck_i                                     | BUFG                                                                                                                              | 205   |
mdm_0/bscan_update1                                    | BUFG                                                                                                                              | 35    |
graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/dbiterr| NONE(graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram)| 3     |
-------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+
Control Signal                                                                                                                                                  | Buffer(FF name)                                                                                 | Load  |
----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+
mb_plb/SPLB_Rst<10>(mb_plb/mb_plb/GEN_SPLB_RST[10].I_SPLB_RST:Q)                                                                                                | NONE(my_timer_0/my_timer_0/USER_LOGIC_I/timer_count_0)                                          | 33    |
mdm_0/mdm_0/MDM_Core_I1/Config_Reg_Acst_inv(mdm_0/mdm_0/MDM_Core_I1/Config_Reg_Acst_inv1_INV_0:O)                                                               | NONE(mdm_0/mdm_0/MDM_Core_I1/Config_Reg_0)                                                      | 23    |
mdm_0/mdm_0/MDM_Core_I1/SEL_inv(mdm_0/mdm_0/MDM_Core_I1/SEL_inv1_INV_0:O)                                                                                       | NONE(mdm_0/mdm_0/MDM_Core_I1/PORT_Selector_0)                                                   | 12    |
fpga_0_rst_1_sys_rst_pin                                                                                                                                        | NONE                                                                                            | 4     |
microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/Command_Reg_Rst(microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/Command_Reg_Rst:Q)    | NONE(microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/command_reg_0)                | 2     |
mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/data_cmd_inv(mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/data_cmd_inv1_INV_0:O)             | NONE(mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/execute)                           | 1     |
mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/local_sel_n3(mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/Insert_Delays[4].LUT_Delay:O)      | NONE(mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/FDC_I)                             | 1     |
mdm_0/mdm_0/MDM_Core_I1/reset_RX_FIFO(mdm_0/mdm_0/MDM_Core_I1/reset_RX_FIFO:Q)                                                                                  | NONE(mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/Have_UARTs.RX_FIFO_I/data_Exists_I)| 1     |
mdm_0/mdm_0/MDM_Core_I1/reset_TX_FIFO(mdm_0/mdm_0/MDM_Core_I1/reset_TX_FIFO:Q)                                                                                  | NONE(mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/Have_UARTs.TX_FIFO_I/data_Exists_I)| 1     |
microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/continue_from_brk(microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/continue_from_brk:Q)| NONE(microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/continue_from_brk_TClk)       | 1     |
microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_cmd(microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_cmd1:O)     | NONE(microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_TClk)              | 1     |
microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/normal_stop_cmd(microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/normal_stop_cmd1:O)   | NONE(microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/normal_stop_TClk)             | 1     |
microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/start_single_step(microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/start_single_step:Q)| NONE(microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/single_Step_TClk)             | 1     |
----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 17.187ns (Maximum Frequency: 58.183MHz)
   Minimum input arrival time before clock: 5.294ns
   Maximum output required time after clock: 11.922ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'fpga_0_clk_1_sys_clk_pin'
  Clock period: 17.187ns (frequency: 58.183MHz)
  Total number of paths / destination ports: 3588443 / 12884
-------------------------------------------------------------------------
Delay:               17.187ns (Levels of Logic = 16)
  Source:            graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_20_2 (FF)
  Destination:       graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram (RAM)
  Source Clock:      fpga_0_clk_1_sys_clk_pin rising
  Destination Clock: fpga_0_clk_1_sys_clk_pin rising

  Data Path: graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_20_2 to graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            30   0.591   1.437  graph_acc_0/USER_LOGIC_I/slv_reg0_20_2 (graph_acc_0/USER_LOGIC_I/slv_reg0_20_2)
     LUT4_D:I0->O         71   0.704   1.279  graph_acc_0/USER_LOGIC_I/gameboard<1>_0_cmp_eq00001 (graph_acc_0/USER_LOGIC_I/gameboard<1>_0_cmp_eq0000)
     LUT4:I3->O            1   0.704   0.424  graph_acc_0/USER_LOGIC_I/gameboard<1>_1_mux0003<0>31_SW0 (N5444)
     LUT4:I3->O            1   0.704   0.455  graph_acc_0/USER_LOGIC_I/gameboard<1>_1_mux0003<3>_SW0 (N274)
     LUT3:I2->O            1   0.704   0.424  graph_acc_0/USER_LOGIC_I/gameboard<1>_1_mux0003<3> (graph_acc_0/USER_LOGIC_I/gameboard<1><1><3>)
     LUT4:I3->O            1   0.704   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_1674 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_1674)
     MUXF5:I0->O           1   0.321   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f5_53 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f554)
     MUXF6:I0->O           1   0.521   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f6_36 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f637)
     MUXF7:I0->O           1   0.521   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f7_22 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f723)
     MUXF8:I1->O           1   0.521   0.499  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_9_f8_10 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_9_f811)
     LUT3:I1->O            1   0.704   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_63 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_63)
     MUXF5:I0->O           1   0.321   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5_2 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f53)
     MUXF6:I0->O          10   0.521   0.961  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6_2 (graph_acc_0/USER_LOGIC_I/gameboard_mux0016<3>)
     LUT2_D:I1->LO         1   0.704   0.104  graph_acc_0/USER_LOGIC_I/bram_sprite_addr<11>_SW0_SW0 (N10721)
     LUT4:I3->O            4   0.704   0.762  graph_acc_0/USER_LOGIC_I/bram_sprite_addr<11> (graph_acc_0/USER_LOGIC_I/bram_sprite_addr<11>)
     begin scope: 'graph_acc_0/USER_LOGIC_I/Sprite'
     begin scope: 'BU2'
     LUT2:I0->O            1   0.704   0.420  U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq00001 (U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq0000)
     RAMB16_S9_S9:ENA          0.770          U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram
    ----------------------------------------
    Total                     17.187ns (10.423ns logic, 6.764ns route)
                                       (60.6% logic, 39.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'mdm_0/mdm_0/drck_i'
  Clock period: 9.972ns (frequency: 100.281MHz)
  Total number of paths / destination ports: 307 / 251
-------------------------------------------------------------------------
Delay:               4.986ns (Levels of Logic = 4)
  Source:            mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/SYNC_FDRE (FF)
  Destination:       microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/shift_Count_0 (FF)
  Source Clock:      mdm_0/mdm_0/drck_i falling
  Destination Clock: mdm_0/mdm_0/drck_i rising

  Data Path: mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/SYNC_FDRE to microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/shift_Count_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE_1:C->Q           1   0.591   0.499  PLB_Interconnect.JTAG_CONTROL_I/SYNC_FDRE (PLB_Interconnect.JTAG_CONTROL_I/sync)
     LUT4:I1->O            9   0.704   0.820  PLB_Interconnect.JTAG_CONTROL_I/shifting_Data24 (Dbg_Shift_7)
     end scope: 'mdm_0/MDM_Core_I1'
     end scope: 'mdm_0'
     begin scope: 'microblaze_0'
     INV:I->O              8   0.704   0.757  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Shift_inv1_INV_0 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/Shift_inv)
     FDR:R                     0.911          microblaze_0/Area.Implement_Debug_Logic.Debug_I/shift_Count_0
    ----------------------------------------
    Total                      4.986ns (2.910ns logic, 2.076ns route)
                                       (58.4% logic, 41.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'mdm_0/bscan_update1'
  Clock period: 12.758ns (frequency: 78.382MHz)
  Total number of paths / destination ports: 209 / 40
-------------------------------------------------------------------------
Delay:               6.379ns (Levels of Logic = 5)
  Source:            mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/FDC_I (FF)
  Destination:       microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_TClk (FF)
  Source Clock:      mdm_0/bscan_update1 falling
  Destination Clock: mdm_0/bscan_update1 rising

  Data Path: mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/FDC_I to microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_TClk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           10   0.591   1.057  PLB_Interconnect.JTAG_CONTROL_I/FDC_I (PLB_Interconnect.JTAG_CONTROL_I/data_cmd)
     LUT2:I0->O            4   0.704   0.762  PLB_Interconnect.JTAG_CONTROL_I/Dbg_Reg_En_I<3>1 (Dbg_Reg_En_0<3>)
     end scope: 'mdm_0/MDM_Core_I1'
     end scope: 'mdm_0'
     begin scope: 'microblaze_0'
     LUT3:I0->O            2   0.704   0.482  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Control_Reg_En_cmp_eq000011 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/N8)
     LUT3:I2->O            9   0.704   0.820  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Control_Reg_En_cmp_eq00001 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/Control_Reg_En)
     FDCE:CE                   0.555          microblaze_0/Area.Implement_Debug_Logic.Debug_I/force_stop_TClk
    ----------------------------------------
    Total                      6.379ns (3.258ns logic, 3.121ns route)
                                       (51.1% logic, 48.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'mdm_0/mdm_0/drck_i'
  Total number of paths / destination ports: 129 / 96
-------------------------------------------------------------------------
Offset:              5.294ns (Levels of Logic = 4)
  Source:            mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:CAPTURE (PAD)
  Destination:       mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/tdo_reg_4 (FF)
  Destination Clock: mdm_0/mdm_0/drck_i rising

  Data Path: mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:CAPTURE to mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/tdo_reg_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BSCAN_SPARTAN3:CAPTURE   51   0.000   0.000  mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I (bscan_capture)
     begin scope: 'mdm_0/MDM_Core_I1'
     LUT4:I0->O            8   0.704   0.836  PLB_Interconnect.JTAG_CONTROL_I/tdo_reg_mux0001<2>3 (PLB_Interconnect.JTAG_CONTROL_I/N5)
     LUT4:I1->O            1   0.704   0.595  PLB_Interconnect.JTAG_CONTROL_I/tdo_reg_mux0001<6>_SW0 (N4)
     LUT3:I0->O            1   0.704   0.000  PLB_Interconnect.JTAG_CONTROL_I/tdo_reg_mux0001<6> (PLB_Interconnect.JTAG_CONTROL_I/tdo_reg_mux0001<6>)
     FDE:D                     0.308          PLB_Interconnect.JTAG_CONTROL_I/tdo_reg_6
    ----------------------------------------
    Total                      5.294ns (3.863ns logic, 1.431ns route)
                                       (73.0% logic, 27.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'fpga_0_clk_1_sys_clk_pin'
  Total number of paths / destination ports: 31 / 31
-------------------------------------------------------------------------
Offset:              1.946ns (Levels of Logic = 2)
  Source:            fpga_0_Micron_RAM_Mem_DQ_pin<15> (PAD)
  Destination:       Micron_RAM/Micron_RAM/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_int_15 (FF)
  Destination Clock: fpga_0_clk_1_sys_clk_pin rising

  Data Path: fpga_0_Micron_RAM_Mem_DQ_pin<15> to Micron_RAM/Micron_RAM/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_int_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           1   1.218   0.420  iobuf_15 (fpga_0_Micron_RAM_Mem_DQ_pin_I<15>)
     begin scope: 'Micron_RAM'
     FDR:D                     0.308          Micron_RAM/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_int_15
    ----------------------------------------
    Total                      1.946ns (1.526ns logic, 0.420ns route)
                                       (78.4% logic, 21.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'mdm_0/bscan_update1'
  Total number of paths / destination ports: 14 / 14
-------------------------------------------------------------------------
Offset:              4.005ns (Levels of Logic = 3)
  Source:            mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:SEL2 (PAD)
  Destination:       mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/command_0 (FF)
  Destination Clock: mdm_0/bscan_update1 falling

  Data Path: mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:SEL2 to mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/command_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BSCAN_SPARTAN3:SEL2    2   0.000   0.000  mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I (mdm_0/sel)
     begin scope: 'mdm_0/MDM_Core_I1'
     LUT3:I1->O            7   0.704   0.883  Ext_JTAG_SEL11 (N2)
     LUT3:I0->O            5   0.704   0.633  Old_MDM_SEL1 (Old_MDM_SEL)
     FDE_1:CE                  0.555          PLB_Interconnect.JTAG_CONTROL_I/command_4
    ----------------------------------------
    Total                      4.005ns (2.489ns logic, 1.516ns route)
                                       (62.1% logic, 37.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'fpga_0_clk_1_sys_clk_pin'
  Total number of paths / destination ports: 93 / 75
-------------------------------------------------------------------------
Offset:              4.283ns (Levels of Logic = 2)
  Source:            xps_ps2_0/xps_ps2_0/PS2_1_I/PS2_SIE_I/PS2_CLK_O (FF)
  Destination:       xps_ps2_0_PS2_1_CLK (PAD)
  Source Clock:      fpga_0_clk_1_sys_clk_pin rising

  Data Path: xps_ps2_0/xps_ps2_0/PS2_1_I/PS2_SIE_I/PS2_CLK_O to xps_ps2_0_PS2_1_CLK
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              1   0.591   0.420  xps_ps2_0/PS2_1_I/PS2_SIE_I/PS2_CLK_O (PS2_1_CLK_O)
     end scope: 'xps_ps2_0'
     IOBUF:I->IO               3.272          iobuf_17 (xps_ps2_0_PS2_1_CLK)
    ----------------------------------------
    Total                      4.283ns (3.863ns logic, 0.420ns route)
                                       (90.2% logic, 9.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'mdm_0/mdm_0/drck_i'
  Total number of paths / destination ports: 130 / 1
-------------------------------------------------------------------------
Offset:              11.922ns (Levels of Logic = 11)
  Source:            microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/Use_SRL16.The_Cache_Addresses[7].SRL16E_Cache_I (FF)
  Destination:       mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2 (PAD)
  Source Clock:      mdm_0/mdm_0/drck_i rising

  Data Path: microblaze_0/microblaze_0/Area.Implement_Debug_Logic.Debug_I/Use_SRL16.The_Cache_Addresses[7].SRL16E_Cache_I to mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     SRL16E:CLK->Q         1   3.706   0.499  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Use_SRL16.The_Cache_Addresses[7].SRL16E_Cache_I (microblaze_0/Area.Implement_Debug_Logic.Debug_I/tdo_config_word1<8>)
     LUT3:I1->O            1   0.704   0.000  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Mmux_TDO_Config_Word_11 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/Mmux_TDO_Config_Word_11)
     MUXF5:I0->O           2   0.321   0.482  microblaze_0/Area.Implement_Debug_Logic.Debug_I/Mmux_TDO_Config_Word_9_f5 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/Mmux_TDO_Config_Word_9_f5)
     LUT4:I2->O            1   0.704   0.000  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO141 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO141)
     MUXF5:I1->O           1   0.321   0.455  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO14_f5 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO14)
     LUT3:I2->O            1   0.704   0.000  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO56_G (N124)
     MUXF5:I1->O           1   0.321   0.499  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO56 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO56)
     LUT4:I1->O            1   0.704   0.595  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO158 (DBG_TDO)
     end scope: 'microblaze_0'
     begin scope: 'mdm_0'
     begin scope: 'mdm_0/MDM_Core_I1'
     LUT4:I0->O            1   0.704   0.499  TDO_i78 (TDO_i78)
     LUT4:I1->O            0   0.704   0.000  TDO_i189 (TDO)
     end scope: 'mdm_0/MDM_Core_I1'
    BSCAN_SPARTAN3:TDO2        0.000          mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I
    ----------------------------------------
    Total                     11.922ns (8.893ns logic, 3.029ns route)
                                       (74.6% logic, 25.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'mdm_0/bscan_update1'
  Total number of paths / destination ports: 45 / 1
-------------------------------------------------------------------------
Offset:              8.653ns (Levels of Logic = 10)
  Source:            mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/FDC_I (FF)
  Destination:       mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2 (PAD)
  Source Clock:      mdm_0/bscan_update1 falling

  Data Path: mdm_0/mdm_0/MDM_Core_I1/PLB_Interconnect.JTAG_CONTROL_I/FDC_I to mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           10   0.591   1.057  PLB_Interconnect.JTAG_CONTROL_I/FDC_I (PLB_Interconnect.JTAG_CONTROL_I/data_cmd)
     LUT2:I0->O            5   0.704   0.808  PLB_Interconnect.JTAG_CONTROL_I/Dbg_Reg_En_I<4>1 (Dbg_Reg_En_0<4>)
     end scope: 'mdm_0/MDM_Core_I1'
     end scope: 'mdm_0'
     begin scope: 'microblaze_0'
     LUT2:I0->O            1   0.704   0.455  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO120 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO120)
     LUT4:I2->O            1   0.704   0.424  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO123 (microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO123)
     LUT4:I3->O            1   0.704   0.595  microblaze_0/Area.Implement_Debug_Logic.Debug_I/TDO158 (DBG_TDO)
     end scope: 'microblaze_0'
     begin scope: 'mdm_0'
     begin scope: 'mdm_0/MDM_Core_I1'
     LUT4:I0->O            1   0.704   0.499  TDO_i78 (TDO_i78)
     LUT4:I1->O            0   0.704   0.000  TDO_i189 (TDO)
     end scope: 'mdm_0/MDM_Core_I1'
    BSCAN_SPARTAN3:TDO2        0.000          mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I
    ----------------------------------------
    Total                      8.653ns (4.815ns logic, 3.838ns route)
                                       (55.6% logic, 44.4% route)

=========================================================================


Total REAL time to Xst completion: 57.00 secs
Total CPU time to Xst completion: 56.70 secs
 
--> 

Total memory usage is 192440 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  330 (   0 filtered)
Number of infos    :   55 (   0 filtered)

