Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "graph_acc_0_wrapper_xst.prj"
Verilog Include Directory          : {"C:\Temp\Bomberman\pcores\" "C:\Xilinx\12.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc3s1200efg320-4
Output File Name                   : "../implementation/graph_acc_0_wrapper.ngc"

---- Source Options
Top Module Name                    : graph_acc_0_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation/graph_acc_0_wrapper}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/pcores/graph_acc_v1_00_a/hdl/vhdl/BRAM_imgs.vhd" in Library graph_acc_v1_00_a.
Entity <BRAM_imgs> compiled.
Entity <BRAM_imgs> (Architecture <BRAM_imgs_a>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/pcores/graph_acc_v1_00_a/hdl/vhdl/vga_controller_640_60.vhd" in Library graph_acc_v1_00_a.
Entity <vga_controller_640_60> compiled.
Entity <vga_controller_640_60> (Architecture <Behavioral>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/pcores/graph_acc_v1_00_a/hdl/vhdl/user_logic.vhd" in Library graph_acc_v1_00_a.
Entity <user_logic> compiled.
Entity <user_logic> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/pcores/graph_acc_v1_00_a/hdl/vhdl/graph_acc.vhd" in Library graph_acc_v1_00_a.
Entity <graph_acc> compiled.
Entity <graph_acc> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/hdl/graph_acc_0_wrapper.vhd" in Library work.
Entity <graph_acc_0_wrapper> compiled.
Entity <graph_acc_0_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <graph_acc_0_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <graph_acc> in library <graph_acc_v1_00_a> (architecture <IMP>) with generics.
	C_BASEADDR = "11000001111000000000000000000000"
	C_FAMILY = "spartan3e"
	C_HIGHADDR = "11000001111000001111111111111111"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SPLB_AWIDTH = 32
	C_SPLB_CLK_PERIOD_PS = 20000
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SMALLEST_MASTER = 32
	C_SPLB_SUPPORT_BURSTS = 0

Analyzing hierarchy for entity <plbv46_slave_single> in library <plbv46_slave_single_v1_01_a> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000001111000000000000000000000",
	                          "0000000000000000000000000000000011000001111000001111111111111111")
	C_ARD_NUM_CE_ARRAY = (4)
	C_BUS2CORE_CLK_RATIO = 1
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SIPIF_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <user_logic> in library <graph_acc_v1_00_a> (architecture <IMP>) with generics.
	C_NUM_REG = 4
	C_SLV_DWIDTH = 32

Analyzing hierarchy for entity <plb_slave_attachment> in library <plbv46_slave_single_v1_01_a> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000001111000000000000000000000",
	                          "0000000000000000000000000000000011000001111000001111111111111111")
	C_ARD_NUM_CE_ARRAY = (4)
	C_BUS2CORE_CLK_RATIO = 1
	C_DPHASE_TIMEOUT = 128
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <vga_controller_640_60> in library <graph_acc_v1_00_a> (architecture <Behavioral>).

Analyzing hierarchy for entity <plb_address_decoder> in library <plbv46_slave_single_v1_01_a> (architecture <IMP>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000001111000000000000000000000",
	                          "0000000000000000000000000000000011000001111000001111111111111111")
	C_ARD_NUM_CE_ARRAY = (4)
	C_BUS_AWIDTH = 32
	C_FAMILY = "nofamily"
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <counter_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_FAMILY = "nofamily"
	C_NUM_BITS = 8

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 16
	C_AW = 32
	C_BAR = "11000001111000000000000000000000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 2
	C_AW = 2
	C_BAR = "00"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 2
	C_AW = 2
	C_BAR = "01"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 2
	C_AW = 2
	C_BAR = "10"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 2
	C_AW = 2
	C_BAR = "11"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <or_gate128> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 1
	C_USE_LUT_OR = false

Analyzing hierarchy for entity <or_muxcy> in library <proc_common_v3_00_a> (architecture <implementation>) with generics.
	C_NUM_BITS = 1


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <graph_acc_0_wrapper> in library <work> (Architecture <STRUCTURE>).
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
Entity <graph_acc_0_wrapper> analyzed. Unit <graph_acc_0_wrapper> generated.

Analyzing generic Entity <graph_acc> in library <graph_acc_v1_00_a> (Architecture <IMP>).
	C_BASEADDR = "11000001111000000000000000000000"
	C_FAMILY = "spartan3e"
	C_HIGHADDR = "11000001111000001111111111111111"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SPLB_AWIDTH = 32
	C_SPLB_CLK_PERIOD_PS = 20000
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SMALLEST_MASTER = 32
	C_SPLB_SUPPORT_BURSTS = 0
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
Entity <graph_acc> analyzed. Unit <graph_acc> generated.

Analyzing generic Entity <plbv46_slave_single> in library <plbv46_slave_single_v1_01_a> (Architecture <implementation>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000001111000000000000000000000",
	                          "0000000000000000000000000000000011000001111000001111111111111111")
	C_ARD_NUM_CE_ARRAY = (4)
	C_BUS2CORE_CLK_RATIO = 1
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SIPIF_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
Entity <plbv46_slave_single> analyzed. Unit <plbv46_slave_single> generated.

Analyzing generic Entity <plb_slave_attachment> in library <plbv46_slave_single_v1_01_a> (Architecture <implementation>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000001111000000000000000000000",
	                          "0000000000000000000000000000000011000001111000001111111111111111")
	C_ARD_NUM_CE_ARRAY = (4)
	C_BUS2CORE_CLK_RATIO = 1
	C_DPHASE_TIMEOUT = 128
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" line 1201: Unconnected output port 'Count_Out' of component 'counter_f'.
Entity <plb_slave_attachment> analyzed. Unit <plb_slave_attachment> generated.

Analyzing generic Entity <plb_address_decoder> in library <plbv46_slave_single_v1_01_a> (Architecture <IMP>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000011000001111000000000000000000000",
	                          "0000000000000000000000000000000011000001111000001111111111111111")
	C_ARD_NUM_CE_ARRAY = (4)
	C_BUS_AWIDTH = 32
	C_FAMILY = "nofamily"
	C_SPLB_P2P = 0
Entity <plb_address_decoder> analyzed. Unit <plb_address_decoder> generated.

Analyzing generic Entity <pselect_f.1> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 16
	C_AW = 32
	C_BAR = "11000001111000000000000000000000"
	C_FAMILY = "nofamily"
Entity <pselect_f.1> analyzed. Unit <pselect_f.1> generated.

Analyzing generic Entity <pselect_f.2> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 2
	C_AW = 2
	C_BAR = "00"
	C_FAMILY = "nofamily"
Entity <pselect_f.2> analyzed. Unit <pselect_f.2> generated.

Analyzing generic Entity <pselect_f.3> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 2
	C_AW = 2
	C_BAR = "01"
	C_FAMILY = "nofamily"
Entity <pselect_f.3> analyzed. Unit <pselect_f.3> generated.

Analyzing generic Entity <pselect_f.4> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 2
	C_AW = 2
	C_BAR = "10"
	C_FAMILY = "nofamily"
Entity <pselect_f.4> analyzed. Unit <pselect_f.4> generated.

Analyzing generic Entity <pselect_f.5> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 2
	C_AW = 2
	C_BAR = "11"
	C_FAMILY = "nofamily"
Entity <pselect_f.5> analyzed. Unit <pselect_f.5> generated.

Analyzing generic Entity <or_gate128> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 1
	C_USE_LUT_OR = false
Entity <or_gate128> analyzed. Unit <or_gate128> generated.

Analyzing generic Entity <or_muxcy> in library <proc_common_v3_00_a> (Architecture <implementation>).
	C_NUM_BITS = 1
Entity <or_muxcy> analyzed. Unit <or_muxcy> generated.

Analyzing generic Entity <counter_f> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_FAMILY = "nofamily"
	C_NUM_BITS = 8
Entity <counter_f> analyzed. Unit <counter_f> generated.

Analyzing generic Entity <user_logic> in library <graph_acc_v1_00_a> (Architecture <IMP>).
	C_NUM_REG = 4
	C_SLV_DWIDTH = 32
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:2211 - "C:/Temp/Bomberman/pcores/graph_acc_v1_00_a/hdl/vhdl/user_logic.vhd" line 201: Instantiating black box module <BRAM_imgs>.
WARNING:Xst:819 - "C:/Temp/Bomberman/pcores/graph_acc_v1_00_a/hdl/vhdl/user_logic.vhd" line 259: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <p1h>, <p1v>, <bram_sprite_dout>, <p2h>, <p2v>
WARNING:Xst:819 - "C:/Temp/Bomberman/pcores/graph_acc_v1_00_a/hdl/vhdl/user_logic.vhd" line 304: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <gb_keep<0>>, <gb_keep<1>>, <gb_keep<2>>, <gb_keep<3>>, <gb_keep<4>>, <gb_keep<5>>, <gb_keep<6>>, <gb_keep<7>>, <gb_keep<8>>, <gb_keep<9>>, <gb_keep<10>>, <gb_keep<11>>, <gb_keep<12>>, <gb_keep<13>>, <gb_keep<14>>, <gb_keep<15>>, <p1h_keep>, <p2h_keep>, <p1v_keep>, <p2v_keep>
INFO:Xst:2679 - Register <slv_reg1> in unit <user_logic> has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <slv_reg2> in unit <user_logic> has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <slv_reg3> in unit <user_logic> has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic.
Entity <user_logic> analyzed. Unit <user_logic> generated.

Analyzing Entity <vga_controller_640_60> in library <graph_acc_v1_00_a> (Architecture <Behavioral>).
Entity <vga_controller_640_60> analyzed. Unit <vga_controller_640_60> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <counter_f>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd".
    Found 9-bit register for signal <icount_out>.
    Found 9-bit subtractor for signal <icount_out$sub0000> created at line 297.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <counter_f> synthesized.


Synthesizing Unit <pselect_f_1>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
WARNING:Xst:647 - Input <A<16:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <pselect_f_1> synthesized.


Synthesizing Unit <pselect_f_2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_2> synthesized.


Synthesizing Unit <pselect_f_3>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_3> synthesized.


Synthesizing Unit <pselect_f_4>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_4> synthesized.


Synthesizing Unit <pselect_f_5>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_5> synthesized.


Synthesizing Unit <or_muxcy>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd".
Unit <or_muxcy> synthesized.


Synthesizing Unit <vga_controller_640_60>.
    Related source file is "C:/Temp/Bomberman/pcores/graph_acc_v1_00_a/hdl/vhdl/vga_controller_640_60.vhd".
    Found 1-bit register for signal <HS>.
    Found 1-bit register for signal <VS>.
    Found 1-bit register for signal <blank>.
    Found 11-bit up counter for signal <hcounter>.
    Found 11-bit comparator greatequal for signal <HS$cmp_ge0000> created at line 177.
    Found 11-bit comparator less for signal <HS$cmp_lt0000> created at line 177.
    Found 11-bit up counter for signal <vcounter>.
    Found 11-bit comparator less for signal <video_enable$cmp_lt0000> created at line 202.
    Found 11-bit comparator less for signal <video_enable$cmp_lt0001> created at line 202.
    Found 11-bit comparator greatequal for signal <VS$cmp_ge0000> created at line 193.
    Found 11-bit comparator less for signal <VS$cmp_lt0000> created at line 193.
    Summary:
	inferred   2 Counter(s).
	inferred   3 D-type flip-flop(s).
	inferred   6 Comparator(s).
Unit <vga_controller_640_60> synthesized.


Synthesizing Unit <user_logic>.
    Related source file is "C:/Temp/Bomberman/pcores/graph_acc_v1_00_a/hdl/vhdl/user_logic.vhd".
WARNING:Xst:646 - Signal <vcount<10>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <slv_reg3> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <slv_reg2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <pixel_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <hcount<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clock_dev_2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clock_dev_1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clk_locked> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <VGA_keep> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 8-bit register for signal <VGA_rgb>.
    Found 10-bit adder for signal <bram_sprite_addr$add0000> created at line 238.
    Found 10-bit adder for signal <bram_sprite_addr$add0001> created at line 238.
    Found 10-bit comparator greatequal for signal <bram_sprite_addr$cmp_ge0000> created at line 238.
    Found 10-bit comparator greatequal for signal <bram_sprite_addr$cmp_ge0001> created at line 238.
    Found 10-bit comparator greatequal for signal <bram_sprite_addr$cmp_ge0002> created at line 241.
    Found 10-bit comparator greatequal for signal <bram_sprite_addr$cmp_ge0003> created at line 241.
    Found 10-bit comparator less for signal <bram_sprite_addr$cmp_lt0000> created at line 238.
    Found 10-bit comparator less for signal <bram_sprite_addr$cmp_lt0001> created at line 238.
    Found 10-bit comparator less for signal <bram_sprite_addr$cmp_lt0002> created at line 241.
    Found 10-bit comparator less for signal <bram_sprite_addr$cmp_lt0003> created at line 241.
    Found 5-bit subtractor for signal <bram_sprite_addr$sub0000> created at line 239.
    Found 5-bit subtractor for signal <bram_sprite_addr$sub0001> created at line 239.
    Found 5-bit subtractor for signal <bram_sprite_addr$sub0002> created at line 242.
    Found 5-bit subtractor for signal <bram_sprite_addr$sub0003> created at line 242.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0016> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0017> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0018> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0019> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0020> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0021> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0022> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0023> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0024> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0025> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0026> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0027> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0028> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0029> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0030> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0031> created at line 244.
    Found 4-bit 16-to-1 multiplexer for signal <gameboard$mux0032> created at line 244.
    Found 64-bit register for signal <gb_keep<0>>.
    Found 64-bit register for signal <gb_keep<10>>.
    Found 64-bit register for signal <gb_keep<11>>.
    Found 64-bit register for signal <gb_keep<12>>.
    Found 64-bit register for signal <gb_keep<13>>.
    Found 64-bit register for signal <gb_keep<14>>.
    Found 64-bit register for signal <gb_keep<15>>.
    Found 64-bit register for signal <gb_keep<1>>.
    Found 64-bit register for signal <gb_keep<2>>.
    Found 64-bit register for signal <gb_keep<3>>.
    Found 64-bit register for signal <gb_keep<4>>.
    Found 64-bit register for signal <gb_keep<5>>.
    Found 64-bit register for signal <gb_keep<6>>.
    Found 64-bit register for signal <gb_keep<7>>.
    Found 64-bit register for signal <gb_keep<8>>.
    Found 64-bit register for signal <gb_keep<9>>.
    Found 10-bit register for signal <p1h_keep>.
    Found 9-bit register for signal <p1v_keep>.
    Found 10-bit register for signal <p2h_keep>.
    Found 9-bit register for signal <p2v_keep>.
    Found 32-bit adder for signal <slv_ip2bus_data$addsub0000> created at line 421.
    Found 32-bit register for signal <slv_reg0>.
    Found 4-bit comparator greater for signal <VGA_out$cmp_gt0000> created at line 262.
    Found 5-bit comparator greater for signal <VGA_out$cmp_gt0001> created at line 263.
    Found 4-bit comparator less for signal <VGA_out$cmp_lt0000> created at line 262.
    Found 5-bit comparator less for signal <VGA_out$cmp_lt0001> created at line 263.
    Summary:
	inferred 1102 D-type flip-flop(s).
	inferred   7 Adder/Subtractor(s).
	inferred  12 Comparator(s).
	inferred  68 Multiplexer(s).
Unit <user_logic> synthesized.


Synthesizing Unit <or_gate128>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <or_gate128> synthesized.


Synthesizing Unit <plb_address_decoder>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_address_decoder.vhd".
WARNING:Xst:647 - Input <Bus_RNW_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Address_In_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Address_Valid_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <cs_s_h_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cs_ce_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr_out_s_h<2:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr_match_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 4-bit register for signal <addr_out_s_h>.
    Found 1-bit register for signal <cs_out_i<0>>.
    Found 1-bit register for signal <cs_out_s_h<0>>.
    Found 1-bit register for signal <decode_hit_reg>.
    Found 4-bit register for signal <rdce_out_i>.
    Found 1-bit register for signal <rnw_s_h>.
    Found 4-bit register for signal <wrce_out_i>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <plb_address_decoder> synthesized.


Synthesizing Unit <plb_slave_attachment>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd".
WARNING:Xst:647 - Input <PLB_UABus> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <valid_plb_type> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <valid_plb_size> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <start_data_phase> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wrdack_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wrcomp_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wait_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_rddack_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_rdcomp_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_data_ack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <set_sl_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd_ce_ld_enable> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_rd_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_rd_busy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_rd_ce> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Register <sl_rdcomp_i> equivalent to <rd_clear_sl_busy> has been removed
    Register <sl_rddack_i> equivalent to <rd_clear_sl_busy> has been removed
    Register <sl_addrack_i> equivalent to <set_sl_busy> has been removed
    Register <sl_wrdack_i> equivalent to <sl_wrcomp_i> has been removed
    Register <wr_clear_sl_busy> equivalent to <sl_wrcomp_i> has been removed
    Found 1-bit register for signal <addr_cntl_cs<0>>.
    Found 1-bit register for signal <addr_cycle_flush>.
    Found 32-bit register for signal <bus2ip_addr_i>.
    Found 4-bit register for signal <bus2ip_be_i>.
    Found 1-bit register for signal <bus2ip_rnw_i>.
    Found 1-bit register for signal <data_timeout>.
    Found 1-bit register for signal <master_id<31>>.
    Found 32-bit register for signal <plb_abus_reg>.
    Found 4-bit register for signal <plb_be_reg>.
    Found 1-bit register for signal <plb_masterid_reg<0>>.
    Found 1-bit register for signal <plb_pavalid_reg>.
    Found 1-bit register for signal <plb_rnw_reg>.
    Found 4-bit register for signal <plb_size_reg>.
    Found 3-bit register for signal <plb_type_reg>.
    Found 32-bit register for signal <plb_wrdbus_reg>.
    Found 1-bit register for signal <rd_clear_sl_busy>.
    Found 1-bit register for signal <set_sl_busy>.
    Found 1-bit register for signal <sl_busy>.
    Found 2-bit register for signal <sl_mbusy_i>.
    Found 2-bit register for signal <sl_mrderr_i>.
    Found 2-bit register for signal <sl_mwrerr_i>.
    Found 32-bit register for signal <sl_rddbus_i>.
    Found 1-bit register for signal <sl_rearbitrate_i>.
    Found 1-bit register for signal <sl_wrcomp_i>.
    Summary:
	inferred 162 D-type flip-flop(s).
Unit <plb_slave_attachment> synthesized.


Synthesizing Unit <plbv46_slave_single>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plbv46_slave_single.vhd".
WARNING:Xst:647 - Input <PLB_wrPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_MSize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdBurst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_SAValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_busLock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_reqPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_lockErr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrBurst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_TAttribute> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_abort> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <plbv46_slave_single> synthesized.


Synthesizing Unit <graph_acc>.
    Related source file is "C:/Temp/Bomberman/pcores/graph_acc_v1_00_a/hdl/vhdl/graph_acc.vhd".
WARNING:Xst:646 - Signal <ipif_Bus2IP_RNW> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ipif_Bus2IP_CS<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ipif_Bus2IP_Addr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <graph_acc> synthesized.


Synthesizing Unit <graph_acc_0_wrapper>.
    Related source file is "C:/Temp/Bomberman/hdl/graph_acc_0_wrapper.vhd".
Unit <graph_acc_0_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 8
 10-bit adder                                          : 2
 32-bit adder                                          : 1
 5-bit subtractor                                      : 4
 9-bit subtractor                                      : 1
# Counters                                             : 2
 11-bit up counter                                     : 2
# Registers                                            : 306
 1-bit register                                        : 34
 10-bit register                                       : 2
 3-bit register                                        : 1
 32-bit register                                       : 5
 4-bit register                                        : 260
 8-bit register                                        : 1
 9-bit register                                        : 3
# Comparators                                          : 18
 10-bit comparator greatequal                          : 4
 10-bit comparator less                                : 4
 11-bit comparator greatequal                          : 2
 11-bit comparator less                                : 4
 4-bit comparator greater                              : 1
 4-bit comparator less                                 : 1
 5-bit comparator greater                              : 1
 5-bit comparator less                                 : 1
# Multiplexers                                         : 17
 4-bit 16-to-1 multiplexer                             : 17

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <../implementation/graph_acc_0_wrapper/BRAM_imgs.ngc>.
Loading core <BRAM_imgs> for timing and area information for instance <Sprite>.
WARNING:Xst:2677 - Node <addr_out_s_h_3> of sequential type is unconnected in block <plb_address_decoder>.
WARNING:Xst:2677 - Node <addr_out_s_h_2> of sequential type is unconnected in block <plb_address_decoder>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 8
 10-bit adder                                          : 2
 32-bit adder                                          : 1
 5-bit subtractor                                      : 4
 9-bit subtractor                                      : 1
# Counters                                             : 2
 11-bit up counter                                     : 2
# Registers                                            : 1290
 Flip-Flops                                            : 1290
# Comparators                                          : 18
 10-bit comparator greatequal                          : 4
 10-bit comparator less                                : 4
 11-bit comparator greatequal                          : 2
 11-bit comparator less                                : 4
 4-bit comparator greater                              : 1
 4-bit comparator less                                 : 1
 5-bit comparator greater                              : 1
 5-bit comparator less                                 : 1
# Multiplexers                                         : 17
 4-bit 16-to-1 multiplexer                             : 17

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch <addr_cntl_cs_0> in Unit <plb_slave_attachment> is equivalent to the following FF/Latch, which will be removed : <addr_cycle_flush> 

Optimizing unit <graph_acc_0_wrapper> ...

Optimizing unit <counter_f> ...

Optimizing unit <vga_controller_640_60> ...

Optimizing unit <user_logic> ...

Optimizing unit <plb_address_decoder> ...

Optimizing unit <plb_slave_attachment> ...
WARNING:Xst:1710 - FF/Latch <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_mrderr_i_1> (without init value) has a constant value of 0 in block <graph_acc_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_mrderr_i_0> (without init value) has a constant value of 0 in block <graph_acc_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_mwrerr_i_1> (without init value) has a constant value of 0 in block <graph_acc_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_mwrerr_i_0> (without init value) has a constant value of 0 in block <graph_acc_0_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_out_s_h_0> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_out_i_0> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_0> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_1> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_2> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_3> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_4> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_5> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_6> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_7> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_8> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_9> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_10> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_11> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_12> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_13> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_14> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_15> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_16> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_17> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_18> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_19> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_20> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_21> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_22> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_23> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_24> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_25> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_26> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_27> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_28> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_29> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_30> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_31> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_16> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_17> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_18> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_19> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_20> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_21> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_22> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_23> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_24> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_25> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_26> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_27> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_30> of sequential type is unconnected in block <graph_acc_0_wrapper>.
WARNING:Xst:2677 - Node <graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/plb_abus_reg_31> of sequential type is unconnected in block <graph_acc_0_wrapper>.

Mapping all equations...
Building and optimizing final netlist ...
FlipFlop graph_acc_0/USER_LOGIC_I/VGA_ctrl/vcounter_5 has been replicated 1 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_0 has been replicated 3 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_1 has been replicated 3 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_10 has been replicated 1 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_11 has been replicated 1 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_12 has been replicated 2 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_13 has been replicated 2 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_14 has been replicated 1 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_15 has been replicated 2 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_20 has been replicated 2 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_21 has been replicated 2 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_24 has been replicated 2 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_25 has been replicated 2 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_26 has been replicated 2 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_27 has been replicated 1 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_28 has been replicated 1 time(s)
FlipFlop graph_acc_0/USER_LOGIC_I/slv_reg0_31 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 1288
 Flip-Flops                                            : 1288

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/graph_acc_0_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 211

Cell Usage :
# BELS                             : 7017
#      GND                         : 2
#      INV                         : 37
#      LUT1                        : 21
#      LUT2                        : 208
#      LUT2_D                      : 246
#      LUT2_L                      : 1
#      LUT3                        : 712
#      LUT3_D                      : 230
#      LUT3_L                      : 45
#      LUT4                        : 3793
#      LUT4_D                      : 208
#      LUT4_L                      : 790
#      MUXCY                       : 152
#      MUXF5                       : 268
#      MUXF6                       : 132
#      MUXF7                       : 64
#      MUXF8                       : 32
#      VCC                         : 2
#      XORCY                       : 74
# FlipFlops/Latches                : 1290
#      FD                          : 1
#      FDE                         : 1064
#      FDR                         : 121
#      FDRE                        : 92
#      FDRS                        : 5
#      FDS                         : 7
# RAMS                             : 3
#      RAMB16_S4_S4                : 2
#      RAMB16_S9_S9                : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                     3323  out of   8672    38%  
 Number of Slice Flip Flops:           1290  out of  17344     7%  
 Number of 4 input LUTs:               6291  out of  17344    36%  
 Number of IOs:                         211
 Number of bonded IOBs:                   0  out of    250     0%  
 Number of BRAMs:                         3  out of     28    10%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal                               | Clock buffer(FF name)                                                                                                 | Load  |
-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+-------+
SPLB_Clk                                   | NONE(graph_acc_0/USER_LOGIC_I/VGA_ctrl/VS)                                                                            | 1293  |
graph_acc_0/USER_LOGIC_I/Sprite/BU2/dbiterr| NONE(graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram)| 3     |
-------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 17.187ns (Maximum Frequency: 58.183MHz)
   Minimum input arrival time before clock: 2.912ns
   Maximum output required time after clock: 0.591ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'SPLB_Clk'
  Clock period: 17.187ns (frequency: 58.183MHz)
  Total number of paths / destination ports: 3392168 / 2512
-------------------------------------------------------------------------
Delay:               17.187ns (Levels of Logic = 16)
  Source:            graph_acc_0/USER_LOGIC_I/slv_reg0_20_2 (FF)
  Destination:       graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram (RAM)
  Source Clock:      SPLB_Clk rising
  Destination Clock: SPLB_Clk rising

  Data Path: graph_acc_0/USER_LOGIC_I/slv_reg0_20_2 to graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            30   0.591   1.437  graph_acc_0/USER_LOGIC_I/slv_reg0_20_2 (graph_acc_0/USER_LOGIC_I/slv_reg0_20_2)
     LUT4_D:I0->O         71   0.704   1.279  graph_acc_0/USER_LOGIC_I/gameboard<1>_0_cmp_eq00001 (graph_acc_0/USER_LOGIC_I/gameboard<1>_0_cmp_eq0000)
     LUT4:I3->O            1   0.704   0.424  graph_acc_0/USER_LOGIC_I/gameboard<1>_1_mux0003<0>31_SW0 (N5444)
     LUT4:I3->O            1   0.704   0.455  graph_acc_0/USER_LOGIC_I/gameboard<1>_1_mux0003<3>_SW0 (N274)
     LUT3:I2->O            1   0.704   0.424  graph_acc_0/USER_LOGIC_I/gameboard<1>_1_mux0003<3> (graph_acc_0/USER_LOGIC_I/gameboard<1><1><3>)
     LUT4:I3->O            1   0.704   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_1674 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_1674)
     MUXF5:I0->O           1   0.321   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f5_53 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f554)
     MUXF6:I0->O           1   0.521   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f6_36 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f637)
     MUXF7:I0->O           1   0.521   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f7_22 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f723)
     MUXF8:I1->O           1   0.521   0.499  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_9_f8_10 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_9_f811)
     LUT3:I1->O            1   0.704   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_63 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_63)
     MUXF5:I0->O           1   0.321   0.000  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5_2 (graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f53)
     MUXF6:I0->O          10   0.521   0.961  graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6_2 (graph_acc_0/USER_LOGIC_I/gameboard_mux0016<3>)
     LUT2_D:I1->LO         1   0.704   0.104  graph_acc_0/USER_LOGIC_I/bram_sprite_addr<11>_SW0_SW0 (N10721)
     LUT4:I3->O            4   0.704   0.762  graph_acc_0/USER_LOGIC_I/bram_sprite_addr<11> (graph_acc_0/USER_LOGIC_I/bram_sprite_addr<11>)
     begin scope: 'graph_acc_0/USER_LOGIC_I/Sprite'
     begin scope: 'BU2'
     LUT2:I0->O            1   0.704   0.420  U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq00001 (U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq0000)
     RAMB16_S9_S9:ENA          0.770          U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram
    ----------------------------------------
    Total                     17.187ns (10.423ns logic, 6.764ns route)
                                       (60.6% logic, 39.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SPLB_Clk'
  Total number of paths / destination ports: 270 / 270
-------------------------------------------------------------------------
Offset:              2.912ns (Levels of Logic = 1)
  Source:            SPLB_Rst (PAD)
  Destination:       graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_0 (FF)
  Destination Clock: SPLB_Clk rising

  Data Path: SPLB_Rst to graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I2->O           32   0.704   1.262  graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_or00001 (graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_or0000)
     FDR:R                     0.911          graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_31
    ----------------------------------------
    Total                      2.912ns (1.650ns logic, 1.262ns route)
                                       (56.7% logic, 43.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'SPLB_Clk'
  Total number of paths / destination ports: 50 / 50
-------------------------------------------------------------------------
Offset:              0.591ns (Levels of Logic = 0)
  Source:            graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rearbitrate_i (FF)
  Destination:       Sl_rearbitrate (PAD)
  Source Clock:      SPLB_Clk rising

  Data Path: graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rearbitrate_i to Sl_rearbitrate
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              0   0.591   0.000  graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rearbitrate_i (graph_acc_0/PLBV46_SLAVE_SINGLE_I/I_SLAVE_ATTACHMENT/sl_rearbitrate_i)
    ----------------------------------------
    Total                      0.591ns (0.591ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================


Total REAL time to Xst completion: 260.00 secs
Total CPU time to Xst completion: 260.78 secs
 
--> 

Total memory usage is 236088 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  118 (   0 filtered)
Number of infos    :    5 (   0 filtered)

