Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "ilmb_cntlr_wrapper_xst.prj"
Verilog Include Directory          : {"C:\Temp\Bomberman\pcores\" "C:\Xilinx\12.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc3s1200efg320-4
Output File Name                   : "../implementation/ilmb_cntlr_wrapper.ngc"

---- Source Options
Top Module Name                    : ilmb_cntlr_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation/ilmb_cntlr_wrapper}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_b/hdl/vhdl/pselect_mask.vhd" in Library lmb_bram_if_cntlr_v2_10_b.
Entity <pselect_mask> compiled.
Entity <pselect_mask> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_b/hdl/vhdl/lmb_bram_if_cntlr.vhd" in Library lmb_bram_if_cntlr_v2_10_b.
Entity <lmb_bram_if_cntlr> compiled.
Entity <lmb_bram_if_cntlr> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/hdl/ilmb_cntlr_wrapper.vhd" in Library work.
Entity <ilmb_cntlr_wrapper> compiled.
Entity <ilmb_cntlr_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <ilmb_cntlr_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <lmb_bram_if_cntlr> in library <lmb_bram_if_cntlr_v2_10_b> (architecture <imp>) with generics.
	C_BASEADDR = "00000000000000000000000000000000"
	C_HIGHADDR = "00000000000000000111111111111111"
	C_LMB_AWIDTH = 32
	C_LMB_DWIDTH = 32
	C_MASK = "10000000000000000000000000000000"

Analyzing hierarchy for entity <pselect_mask> in library <lmb_bram_if_cntlr_v2_10_b> (architecture <imp>) with generics.
	C_AW = 32
	C_BAR = "00000000000000000000000000000000"
	C_MASK = "10000000000000000000000000000000"


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ilmb_cntlr_wrapper> in library <work> (Architecture <STRUCTURE>).
Entity <ilmb_cntlr_wrapper> analyzed. Unit <ilmb_cntlr_wrapper> generated.

Analyzing generic Entity <lmb_bram_if_cntlr> in library <lmb_bram_if_cntlr_v2_10_b> (Architecture <imp>).
	C_BASEADDR = "00000000000000000000000000000000"
	C_HIGHADDR = "00000000000000000111111111111111"
	C_LMB_AWIDTH = 32
	C_LMB_DWIDTH = 32
	C_MASK = "10000000000000000000000000000000"
Entity <lmb_bram_if_cntlr> analyzed. Unit <lmb_bram_if_cntlr> generated.

Analyzing generic Entity <pselect_mask> in library <lmb_bram_if_cntlr_v2_10_b> (Architecture <imp>).
	C_AW = 32
	C_BAR = "00000000000000000000000000000000"
	C_MASK = "10000000000000000000000000000000"
Entity <pselect_mask> analyzed. Unit <pselect_mask> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <pselect_mask>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_b/hdl/vhdl/pselect_mask.vhd".
WARNING:Xst:647 - Input <A<1:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <pselect_mask> synthesized.


Synthesizing Unit <lmb_bram_if_cntlr>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_b/hdl/vhdl/lmb_bram_if_cntlr.vhd".
WARNING:Xst:647 - Input <LMB_ReadStrobe> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <lmb_select_1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <lmb_addrstrobe_i>.
    Found 1-bit register for signal <Sl_Ready_i>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <lmb_bram_if_cntlr> synthesized.


Synthesizing Unit <ilmb_cntlr_wrapper>.
    Related source file is "C:/Temp/Bomberman/hdl/ilmb_cntlr_wrapper.vhd".
Unit <ilmb_cntlr_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 2
 1-bit register                                        : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 2
 Flip-Flops                                            : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ilmb_cntlr_wrapper> ...

Optimizing unit <lmb_bram_if_cntlr> ...

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 2
 Flip-Flops                                            : 2

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/ilmb_cntlr_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 209

Cell Usage :
# BELS                             : 7
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 1
#      LUT3                        : 4
# FlipFlops/Latches                : 2
#      FDR                         : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                        3  out of   8672     0%  
 Number of Slice Flip Flops:              2  out of  17344     0%  
 Number of 4 input LUTs:                  6  out of  17344     0%  
 Number of IOs:                         209
 Number of bonded IOBs:                   0  out of    250     0%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+----------------------------+-------+
Clock Signal                       | Clock buffer(FF name)      | Load  |
-----------------------------------+----------------------------+-------+
BRAM_Clk_A                         | NONE(ilmb_cntlr/Sl_Ready_i)| 2     |
-----------------------------------+----------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: 1.432ns
   Maximum output required time after clock: 1.890ns
   Maximum combinational path delay: 0.879ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'BRAM_Clk_A'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              1.432ns (Levels of Logic = 1)
  Source:            LMB_ABus<0> (PAD)
  Destination:       ilmb_cntlr/Sl_Ready_i (FF)
  Destination Clock: BRAM_Clk_A rising

  Data Path: LMB_ABus<0> to ilmb_cntlr/Sl_Ready_i
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     INV:I->O              1   0.704   0.420  ilmb_cntlr/pselect_mask_lmb/CS_cmp_eq00001_INV_0 (ilmb_cntlr/lmb_select)
     FDR:D                     0.308          ilmb_cntlr/Sl_Ready_i
    ----------------------------------------
    Total                      1.432ns (1.012ns logic, 0.420ns route)
                                       (70.7% logic, 29.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'BRAM_Clk_A'
  Total number of paths / destination ports: 2 / 1
-------------------------------------------------------------------------
Offset:              1.890ns (Levels of Logic = 1)
  Source:            ilmb_cntlr/Sl_Ready_i (FF)
  Destination:       Sl_Ready (PAD)
  Source Clock:      BRAM_Clk_A rising

  Data Path: ilmb_cntlr/Sl_Ready_i to Sl_Ready
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.591   0.595  ilmb_cntlr/Sl_Ready_i (ilmb_cntlr/Sl_Ready_i)
     LUT2:I0->O            0   0.704   0.000  ilmb_cntlr/Sl_Ready1 (Sl_Ready)
    ----------------------------------------
    Total                      1.890ns (1.295ns logic, 0.595ns route)
                                       (68.5% logic, 31.5% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 110 / 102
-------------------------------------------------------------------------
Delay:               0.879ns (Levels of Logic = 1)
  Source:            LMB_BE<0> (PAD)
  Destination:       BRAM_WEN_A<0> (PAD)

  Data Path: LMB_BE<0> to BRAM_WEN_A<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT3:I0->O            0   0.704   0.000  ilmb_cntlr/lmb_we_0_and00001 (BRAM_WEN_A<0>)
    ----------------------------------------
    Total                      0.879ns (0.879ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.77 secs
 
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Total memory usage is 137144 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    1 (   0 filtered)

