Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "switches_8bit_wrapper_xst.prj"
Verilog Include Directory          : {"C:\Temp\Bomberman\pcores\" "C:\Xilinx\12.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc3s1200efg320-4
Output File Name                   : "../implementation/switches_8bit_wrapper.ngc"

---- Source Options
Top Module Name                    : switches_8bit_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation/switches_8bit_wrapper}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/inferred_lut4.vhd" in Library proc_common_v3_00_a.
Entity <inferred_lut4> compiled.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/muxf_struct_f.vhd" in Library proc_common_v3_00_a.
Entity <muxf_struct> compiled.
Entity <muxf_struct> (Architecture <imp>) compiled.
Entity <muxf_struct_f> compiled.
Entity <muxf_struct_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_bit> compiled.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/cntr_incr_decr_addn_f.vhd" in Library proc_common_v3_00_a.
Entity <cntr_incr_decr_addn_f> compiled.
Entity <cntr_incr_decr_addn_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_f> compiled.
Entity <dynshreg_f> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_adder_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder_bit> compiled.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter> compiled.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_occ_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter> compiled.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <counter_bit> compiled.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy_f.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy_f> compiled.
Entity <or_muxcy_f> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu_f> compiled.
Entity <srl_fifo_rbu_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family.vhd" in Library proc_common_v3_00_a.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_occ_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter_top> compiled.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_top> compiled.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_adder.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder> compiled.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter.vhd" in Library proc_common_v3_00_a.
Entity <Counter> compiled.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/coregen_comp_defs.vhd" in Library proc_common_v3_00_a.
Package <coregen_comp_defs> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/common_types_pkg.vhd" in Library proc_common_v3_00_a.
Package <Common_Types> compiled.
WARNING:HDLParsers:3534 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/common_types_pkg.vhd" Line 223. In the function Get_RLOC_Name, not all control paths contain a return statement.
Package body <Common_Types> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/conv_funs_pkg.vhd" in Library proc_common_v3_00_a.
Package <conv_funs_pkg> compiled.
Package body <conv_funs_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/async_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <async_fifo_fg> compiled.
Entity <async_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/sync_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <sync_fifo_fg> compiled.
Entity <sync_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/blk_mem_gen_wrapper.vhd" in Library proc_common_v3_00_a.
Entity <blk_mem_gen_wrapper> compiled.
Entity <blk_mem_gen_wrapper> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/addsub.vhd" in Library proc_common_v3_00_a.
Entity <addsub> compiled.
Entity <addsub> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/direct_path_cntr.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr> compiled.
Entity <direct_path_cntr> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/direct_path_cntr_ai.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr_ai> compiled.
Entity <direct_path_cntr_ai> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/down_counter.vhd" in Library proc_common_v3_00_a.
Entity <down_counter> compiled.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/eval_timer.vhd" in Library proc_common_v3_00_a.
Entity <eval_timer> compiled.
Entity <eval_timer> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_steer.vhd" in Library proc_common_v3_00_a.
Entity <IPIF_Steer> compiled.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_steer128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_steer128> compiled.
Entity <ipif_steer128> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_mirror128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_mirror128> compiled.
Entity <ipif_mirror128> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg> compiled.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg2.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg2> compiled.
Entity <ld_arith_reg2> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/mux_onehot.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_bits.vhd" in Library proc_common_v3_00_a.
Entity <or_bits> compiled.
Entity <or_bits> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate.vhd" in Library proc_common_v3_00_a.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_dpram_select.vhd" in Library proc_common_v3_00_a.
Entity <pf_dpram_select> compiled.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect.vhd" in Library proc_common_v3_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_mask.vhd" in Library proc_common_v3_00_a.
Entity <pselect_mask> compiled.
Entity <pselect_mask> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl16_fifo.vhd" in Library proc_common_v3_00_a.
Entity <srl16_fifo> compiled.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo.vhd" in Library proc_common_v3_00_a.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo2.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo2> compiled.
Entity <srl_fifo2> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo3.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo3> compiled.
Entity <srl_fifo3> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu> compiled.
Entity <srl_fifo_rbu> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/valid_be.vhd" in Library proc_common_v3_00_a.
Entity <valid_be> compiled.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_with_enable_f.vhd" in Library proc_common_v3_00_a.
Entity <or_with_enable_f> compiled.
Entity <or_with_enable_f> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_i_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_i_f> compiled.
Entity <dynshreg_i_f> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/mux_onehot_f.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot_f> compiled.
Entity <mux_onehot_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_f> compiled.
Entity <srl_fifo_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/compare_vectors_f.vhd" in Library proc_common_v3_00_a.
Entity <compare_vectors_f> compiled.
Entity <compare_vectors_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate_f.vhd" in Library proc_common_v3_00_a.
Entity <or_gate_f> compiled.
Entity <or_gate_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/soft_reset.vhd" in Library proc_common_v3_00_a.
Entity <soft_reset> compiled.
Entity <soft_reset> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/hdl/vhdl/gpio_core.vhd" in Library xps_gpio_v2_00_a.
Entity <GPIO_Core> compiled.
Entity <GPIO_Core> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/hdl/vhdl/xps_gpio.vhd" in Library xps_gpio_v2_00_a.
Entity <xps_gpio> compiled.
Entity <xps_gpio> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/hdl/switches_8bit_wrapper.vhd" in Library work.
Entity <switches_8bit_wrapper> compiled.
Entity <switches_8bit_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <switches_8bit_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <xps_gpio> in library <xps_gpio_v2_00_a> (architecture <imp>) with generics.
	C_ALL_INPUTS = 1
	C_ALL_INPUTS_2 = 0
	C_BASEADDR = "10000001010000000000000000000000"
	C_DOUT_DEFAULT = "00000000000000000000000000000000"
	C_DOUT_DEFAULT_2 = "00000000000000000000000000000000"
	C_FAMILY = "spartan3e"
	C_GPIO2_WIDTH = 32
	C_GPIO_WIDTH = 8
	C_HIGHADDR = "10000001010000001111111111111111"
	C_INTERRUPT_PRESENT = 0
	C_IS_DUAL = 0
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SUPPORT_BURSTS = 0
	C_TRI_DEFAULT = "11111111111111111111111111111111"
	C_TRI_DEFAULT_2 = "11111111111111111111111111111111"
WARNING:Xst:821 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/hdl/vhdl/xps_gpio.vhd" line 364: Loop body will iterate zero times
WARNING:Xst:821 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/hdl/vhdl/xps_gpio.vhd" line 391: Loop body will iterate zero times

Analyzing hierarchy for entity <plbv46_slave_single> in library <plbv46_slave_single_v1_01_a> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000001010000000000000000000000",
	                          "0000000000000000000000000000000010000001010000000000000000001111")
	C_ARD_NUM_CE_ARRAY = (5)
	C_BUS2CORE_CLK_RATIO = 1
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SIPIF_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <GPIO_Core> in library <xps_gpio_v2_00_a> (architecture <IMP>) with generics.
	C_AW = 32
	C_DOUT_DEFAULT = "00000000000000000000000000000000"
	C_DOUT_DEFAULT_2 = "00000000000000000000000000000000"
	C_DW = 32
	C_FAMILY = "spartan3e"
	C_GPIO2_WIDTH = 32
	C_GPIO_WIDTH = 8
	C_INTERRUPT_PRESENT = 0
	C_IS_DUAL = 0
	C_MAX_GPIO_WIDTH = 8
	C_TRI_DEFAULT = "11111111111111111111111111111111"
	C_TRI_DEFAULT_2 = "11111111111111111111111111111111"

Analyzing hierarchy for entity <plb_slave_attachment> in library <plbv46_slave_single_v1_01_a> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000001010000000000000000000000",
	                          "0000000000000000000000000000000010000001010000000000000000001111")
	C_ARD_NUM_CE_ARRAY = (5)
	C_BUS2CORE_CLK_RATIO = 1
	C_DPHASE_TIMEOUT = 128
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <plb_address_decoder> in library <plbv46_slave_single_v1_01_a> (architecture <IMP>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000001010000000000000000000000",
	                          "0000000000000000000000000000000010000001010000000000000000001111")
	C_ARD_NUM_CE_ARRAY = (5)
	C_BUS_AWIDTH = 32
	C_FAMILY = "nofamily"
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <counter_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_FAMILY = "nofamily"
	C_NUM_BITS = 8

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 28
	C_AW = 32
	C_BAR = "10000001010000000000000000000000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 3
	C_AW = 3
	C_BAR = "000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 3
	C_AW = 3
	C_BAR = "001"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 3
	C_AW = 3
	C_BAR = "010"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 3
	C_AW = 3
	C_BAR = "011"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 3
	C_AW = 3
	C_BAR = "100"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <or_gate128> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 1
	C_USE_LUT_OR = false

Analyzing hierarchy for entity <or_muxcy> in library <proc_common_v3_00_a> (architecture <implementation>) with generics.
	C_NUM_BITS = 1


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <switches_8bit_wrapper> in library <work> (Architecture <STRUCTURE>).
WARNING:Xst:37 - Detected unknown constraint/property "IP_GROUP". This constraint/property is not supported by the current software release and will be ignored.
    Set property "MAX_FANOUT = 10000" for signal <SPLB_Clk> in unit <xps_gpio>.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
    Set property "MAX_FANOUT = 10000" for signal <SPLB_Rst> in unit <xps_gpio>.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "IP_GROUP". This constraint/property is not supported by the current software release and will be ignored.
Entity <switches_8bit_wrapper> analyzed. Unit <switches_8bit_wrapper> generated.

Analyzing generic Entity <xps_gpio> in library <xps_gpio_v2_00_a> (Architecture <imp>).
	C_ALL_INPUTS = 1
	C_ALL_INPUTS_2 = 0
	C_BASEADDR = "10000001010000000000000000000000"
	C_DOUT_DEFAULT = "00000000000000000000000000000000"
	C_DOUT_DEFAULT_2 = "00000000000000000000000000000000"
	C_FAMILY = "spartan3e"
	C_GPIO2_WIDTH = 32
	C_GPIO_WIDTH = 8
	C_HIGHADDR = "10000001010000001111111111111111"
	C_INTERRUPT_PRESENT = 0
	C_IS_DUAL = 0
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NATIVE_DWIDTH = 32
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SUPPORT_BURSTS = 0
	C_TRI_DEFAULT = "11111111111111111111111111111111"
	C_TRI_DEFAULT_2 = "11111111111111111111111111111111"
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:821 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/hdl/vhdl/xps_gpio.vhd" line 364: Loop body will iterate zero times
Entity <xps_gpio> analyzed. Unit <xps_gpio> generated.

Analyzing generic Entity <plbv46_slave_single> in library <plbv46_slave_single_v1_01_a> (Architecture <implementation>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000001010000000000000000000000",
	                          "0000000000000000000000000000000010000001010000000000000000001111")
	C_ARD_NUM_CE_ARRAY = (5)
	C_BUS2CORE_CLK_RATIO = 1
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_SIPIF_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
Entity <plbv46_slave_single> analyzed. Unit <plbv46_slave_single> generated.

Analyzing generic Entity <plb_slave_attachment> in library <plbv46_slave_single_v1_01_a> (Architecture <implementation>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000001010000000000000000000000",
	                          "0000000000000000000000000000000010000001010000000000000000001111")
	C_ARD_NUM_CE_ARRAY = (5)
	C_BUS2CORE_CLK_RATIO = 1
	C_DPHASE_TIMEOUT = 128
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 1
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" line 1201: Unconnected output port 'Count_Out' of component 'counter_f'.
Entity <plb_slave_attachment> analyzed. Unit <plb_slave_attachment> generated.

Analyzing generic Entity <plb_address_decoder> in library <plbv46_slave_single_v1_01_a> (Architecture <IMP>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000001010000000000000000000000",
	                          "0000000000000000000000000000000010000001010000000000000000001111")
	C_ARD_NUM_CE_ARRAY = (5)
	C_BUS_AWIDTH = 32
	C_FAMILY = "nofamily"
	C_SPLB_P2P = 0
Entity <plb_address_decoder> analyzed. Unit <plb_address_decoder> generated.

Analyzing generic Entity <pselect_f.1> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 28
	C_AW = 32
	C_BAR = "10000001010000000000000000000000"
	C_FAMILY = "nofamily"
Entity <pselect_f.1> analyzed. Unit <pselect_f.1> generated.

Analyzing generic Entity <pselect_f.2> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 3
	C_AW = 3
	C_BAR = "000"
	C_FAMILY = "nofamily"
Entity <pselect_f.2> analyzed. Unit <pselect_f.2> generated.

Analyzing generic Entity <pselect_f.3> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 3
	C_AW = 3
	C_BAR = "001"
	C_FAMILY = "nofamily"
Entity <pselect_f.3> analyzed. Unit <pselect_f.3> generated.

Analyzing generic Entity <pselect_f.4> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 3
	C_AW = 3
	C_BAR = "010"
	C_FAMILY = "nofamily"
Entity <pselect_f.4> analyzed. Unit <pselect_f.4> generated.

Analyzing generic Entity <pselect_f.5> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 3
	C_AW = 3
	C_BAR = "011"
	C_FAMILY = "nofamily"
Entity <pselect_f.5> analyzed. Unit <pselect_f.5> generated.

Analyzing generic Entity <pselect_f.6> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 3
	C_AW = 3
	C_BAR = "100"
	C_FAMILY = "nofamily"
Entity <pselect_f.6> analyzed. Unit <pselect_f.6> generated.

Analyzing generic Entity <or_gate128> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 1
	C_USE_LUT_OR = false
Entity <or_gate128> analyzed. Unit <or_gate128> generated.

Analyzing generic Entity <or_muxcy> in library <proc_common_v3_00_a> (Architecture <implementation>).
	C_NUM_BITS = 1
Entity <or_muxcy> analyzed. Unit <or_muxcy> generated.

Analyzing generic Entity <counter_f> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_FAMILY = "nofamily"
	C_NUM_BITS = 8
Entity <counter_f> analyzed. Unit <counter_f> generated.

Analyzing generic Entity <GPIO_Core> in library <xps_gpio_v2_00_a> (Architecture <IMP>).
	C_AW = 32
	C_DOUT_DEFAULT = "00000000000000000000000000000000"
	C_DOUT_DEFAULT_2 = "00000000000000000000000000000000"
	C_DW = 32
	C_FAMILY = "spartan3e"
	C_GPIO2_WIDTH = 32
	C_GPIO_WIDTH = 8
	C_INTERRUPT_PRESENT = 0
	C_IS_DUAL = 0
	C_MAX_GPIO_WIDTH = 8
	C_TRI_DEFAULT = "11111111111111111111111111111111"
	C_TRI_DEFAULT_2 = "11111111111111111111111111111111"
Entity <GPIO_Core> analyzed. Unit <GPIO_Core> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <GPIO_Core>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/hdl/vhdl/gpio_core.vhd".
WARNING:Xst:647 - Input <ABus_Reg<0:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ABus_Reg<30:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <GPIO2_IO_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BE_Reg<0:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <GPIO2_IO_O> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:1305 - Output <GPIO2_IO_T> is never assigned. Tied to value 00000000000000000000000000000000.
WARNING:Xst:646 - Signal <tri2_default_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <reset_zeros> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <reset2_zeros> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <or_ints2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <or_ints> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <gpio_in_d2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <gpio_in_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <gpio_data_in_xor_reg> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <gpio_data_in_xor> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dout2_default_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 8-bit register for signal <gpio_Data_In>.
    Found 8-bit register for signal <gpio_Data_Out>.
    Found 8-bit register for signal <GPIO_DBus_i<24:31>>.
    Found 8-bit register for signal <gpio_io_i_d1>.
    Found 8-bit register for signal <gpio_io_i_d2>.
    Found 8-bit register for signal <gpio_OE>.
    Found 1-bit register for signal <gpio_xferAck_Reg>.
    Found 1-bit register for signal <iGPIO_xferAck>.
    Summary:
	inferred  50 D-type flip-flop(s).
Unit <GPIO_Core> synthesized.


Synthesizing Unit <counter_f>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd".
    Found 9-bit register for signal <icount_out>.
    Found 9-bit subtractor for signal <icount_out$sub0000> created at line 297.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <counter_f> synthesized.


Synthesizing Unit <pselect_f_1>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
WARNING:Xst:647 - Input <A<28:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <pselect_f_1> synthesized.


Synthesizing Unit <pselect_f_2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_2> synthesized.


Synthesizing Unit <pselect_f_3>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_3> synthesized.


Synthesizing Unit <pselect_f_4>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_4> synthesized.


Synthesizing Unit <pselect_f_5>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_5> synthesized.


Synthesizing Unit <pselect_f_6>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
Unit <pselect_f_6> synthesized.


Synthesizing Unit <or_muxcy>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd".
Unit <or_muxcy> synthesized.


Synthesizing Unit <or_gate128>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <or_gate128> synthesized.


Synthesizing Unit <plb_address_decoder>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_address_decoder.vhd".
WARNING:Xst:647 - Input <Bus_RNW_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Address_In_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Address_Valid_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <cs_s_h_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cs_ce_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr_out_s_h<3:4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr_match_clr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 5-bit register for signal <addr_out_s_h>.
    Found 1-bit register for signal <cs_out_i<0>>.
    Found 1-bit register for signal <cs_out_s_h<0>>.
    Found 1-bit register for signal <decode_hit_reg>.
    Found 5-bit register for signal <rdce_out_i>.
    Found 1-bit register for signal <rnw_s_h>.
    Found 5-bit register for signal <wrce_out_i>.
    Summary:
	inferred  19 D-type flip-flop(s).
Unit <plb_address_decoder> synthesized.


Synthesizing Unit <plb_slave_attachment>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd".
WARNING:Xst:647 - Input <PLB_UABus> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <valid_plb_type> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <valid_plb_size> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <start_data_phase> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wrdack_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wrcomp_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wait_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_rddack_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_rdcomp_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_data_ack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <set_sl_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd_ce_ld_enable> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_rd_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_rd_busy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_sl_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <clear_rd_ce> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Register <sl_rdcomp_i> equivalent to <rd_clear_sl_busy> has been removed
    Register <sl_rddack_i> equivalent to <rd_clear_sl_busy> has been removed
    Register <sl_addrack_i> equivalent to <set_sl_busy> has been removed
    Register <sl_wrdack_i> equivalent to <sl_wrcomp_i> has been removed
    Register <wr_clear_sl_busy> equivalent to <sl_wrcomp_i> has been removed
    Found 1-bit register for signal <addr_cntl_cs<0>>.
    Found 1-bit register for signal <addr_cycle_flush>.
    Found 32-bit register for signal <bus2ip_addr_i>.
    Found 4-bit register for signal <bus2ip_be_i>.
    Found 1-bit register for signal <bus2ip_rnw_i>.
    Found 1-bit register for signal <data_timeout>.
    Found 1-bit register for signal <master_id<31>>.
    Found 32-bit register for signal <plb_abus_reg>.
    Found 4-bit register for signal <plb_be_reg>.
    Found 1-bit register for signal <plb_masterid_reg<0>>.
    Found 1-bit register for signal <plb_pavalid_reg>.
    Found 1-bit register for signal <plb_rnw_reg>.
    Found 4-bit register for signal <plb_size_reg>.
    Found 3-bit register for signal <plb_type_reg>.
    Found 32-bit register for signal <plb_wrdbus_reg>.
    Found 1-bit register for signal <rd_clear_sl_busy>.
    Found 1-bit register for signal <set_sl_busy>.
    Found 1-bit register for signal <sl_busy>.
    Found 2-bit register for signal <sl_mbusy_i>.
    Found 2-bit register for signal <sl_mrderr_i>.
    Found 2-bit register for signal <sl_mwrerr_i>.
    Found 32-bit register for signal <sl_rddbus_i>.
    Found 1-bit register for signal <sl_rearbitrate_i>.
    Found 1-bit register for signal <sl_wrcomp_i>.
    Summary:
	inferred 162 D-type flip-flop(s).
Unit <plb_slave_attachment> synthesized.


Synthesizing Unit <plbv46_slave_single>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1_01_a/hdl/vhdl/plbv46_slave_single.vhd".
WARNING:Xst:647 - Input <PLB_wrPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_MSize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdBurst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_SAValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_busLock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_reqPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_lockErr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrBurst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_TAttribute> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_abort> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <plbv46_slave_single> synthesized.


Synthesizing Unit <xps_gpio>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/hdl/vhdl/xps_gpio.vhd".
WARNING:Xst:646 - Signal <ip2bus_intrevent> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <bus2ip_wrce> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <bus2ip_rdce> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <Bus2IP_Data_i<8:31>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <Bus2IP1_Data_i<8:31>> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000.
Unit <xps_gpio> synthesized.


Synthesizing Unit <switches_8bit_wrapper>.
    Related source file is "C:/Temp/Bomberman/hdl/switches_8bit_wrapper.vhd".
Unit <switches_8bit_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 9-bit subtractor                                      : 1
# Registers                                            : 72
 1-bit register                                        : 59
 3-bit register                                        : 1
 32-bit register                                       : 4
 4-bit register                                        : 3
 5-bit register                                        : 1
 8-bit register                                        : 3
 9-bit register                                        : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:2677 - Node <addr_out_s_h_4> of sequential type is unconnected in block <plb_address_decoder>.
WARNING:Xst:2677 - Node <addr_out_s_h_3> of sequential type is unconnected in block <plb_address_decoder>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 9-bit subtractor                                      : 1
# Registers                                            : 238
 Flip-Flops                                            : 238

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <sl_mwrerr_i_0> (without init value) has a constant value of 0 in block <plb_slave_attachment>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sl_mwrerr_i_1> (without init value) has a constant value of 0 in block <plb_slave_attachment>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sl_mrderr_i_0> (without init value) has a constant value of 0 in block <plb_slave_attachment>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <sl_mrderr_i_1> (without init value) has a constant value of 0 in block <plb_slave_attachment>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <addr_cntl_cs_0> in Unit <plb_slave_attachment> is equivalent to the following FF/Latch, which will be removed : <addr_cycle_flush> 

Optimizing unit <switches_8bit_wrapper> ...

Optimizing unit <GPIO_Core> ...

Optimizing unit <counter_f> ...

Optimizing unit <plb_address_decoder> ...

Optimizing unit <plb_slave_attachment> ...

Optimizing unit <xps_gpio> ...
WARNING:Xst:1710 - FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_0> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_1> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_2> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_3> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_4> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_5> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_6> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_7> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_8> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_9> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_10> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_11> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_12> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_13> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_14> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_15> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_16> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_17> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_18> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_19> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_20> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_21> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_22> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_23> (without init value) has a constant value of 0 in block <switches_8bit_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_23> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_22> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_21> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_20> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_19> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_18> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_17> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_16> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_15> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_14> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_13> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_12> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_11> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_10> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_9> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_8> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_abus_reg_31> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_abus_reg_30> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_be_reg_2> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_be_reg_1> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_be_reg_0> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_be_i_2> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_be_i_1> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_be_i_0> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_31> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_30> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_27> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_26> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_25> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_24> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_23> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_22> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_21> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_20> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_19> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_18> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_17> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_16> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_15> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_14> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_13> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_12> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_11> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_10> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_9> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_8> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_7> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_6> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_5> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_4> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_3> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_2> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_1> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_0> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_0> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_4> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_3> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_2> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_1> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/rdce_out_i_0> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_4> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_3> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_1> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/wrce_out_i_2> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/addr_out_s_h_0> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/addr_out_s_h_1> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/addr_out_s_h_2> of sequential type is unconnected in block <switches_8bit_wrapper>.
WARNING:Xst:2677 - Node <Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/I_DECODER/rnw_s_h> of sequential type is unconnected in block <switches_8bit_wrapper>.

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

Processing Unit <switches_8bit_wrapper> :
	Found 3-bit shift register for signal <Switches_8Bit/gpio_core_1/gpio_Data_In_7>.
	Found 3-bit shift register for signal <Switches_8Bit/gpio_core_1/gpio_Data_In_6>.
	Found 3-bit shift register for signal <Switches_8Bit/gpio_core_1/gpio_Data_In_5>.
	Found 3-bit shift register for signal <Switches_8Bit/gpio_core_1/gpio_Data_In_4>.
	Found 3-bit shift register for signal <Switches_8Bit/gpio_core_1/gpio_Data_In_3>.
	Found 3-bit shift register for signal <Switches_8Bit/gpio_core_1/gpio_Data_In_2>.
	Found 3-bit shift register for signal <Switches_8Bit/gpio_core_1/gpio_Data_In_1>.
	Found 3-bit shift register for signal <Switches_8Bit/gpio_core_1/gpio_Data_In_0>.
Unit <switches_8bit_wrapper> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 117
 Flip-Flops                                            : 117
# Shift Registers                                      : 8
 3-bit shift register                                  : 8

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/switches_8bit_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 322

Cell Usage :
# BELS                             : 72
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 12
#      LUT3                        : 9
#      LUT3_L                      : 1
#      LUT4                        : 35
#      LUT4_D                      : 2
#      LUT4_L                      : 2
#      MUXCY                       : 8
#      VCC                         : 1
# FlipFlops/Latches                : 125
#      FD                          : 9
#      FDR                         : 73
#      FDRE                        : 26
#      FDRS                        : 2
#      FDS                         : 7
#      FDSE                        : 8
# Shift Registers                  : 8
#      SRL16                       : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                       79  out of   8672     0%  
 Number of Slice Flip Flops:            125  out of  17344     0%  
 Number of 4 input LUTs:                 70  out of  17344     0%  
    Number used as logic:                62
    Number used as Shift registers:       8
 Number of IOs:                         322
 Number of bonded IOBs:                   0  out of    250     0%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                            | Load  |
-----------------------------------+------------------------------------------------------------------+-------+
SPLB_Clk                           | NONE(Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_31)| 133   |
-----------------------------------+------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.973ns (Maximum Frequency: 201.086MHz)
   Minimum input arrival time before clock: 2.547ns
   Maximum output required time after clock: 0.591ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'SPLB_Clk'
  Clock period: 4.973ns (frequency: 201.086MHz)
  Total number of paths / destination ports: 558 / 137
-------------------------------------------------------------------------
Delay:               4.973ns (Levels of Logic = 2)
  Source:            Switches_8Bit/gpio_core_1/iGPIO_xferAck (FF)
  Destination:       Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/INCLUDE_DATA_PHASE_WDT.I_DPTO_COUNTER/icount_out_7 (FF)
  Source Clock:      SPLB_Clk rising
  Destination Clock: SPLB_Clk rising

  Data Path: Switches_8Bit/gpio_core_1/iGPIO_xferAck to Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/INCLUDE_DATA_PHASE_WDT.I_DPTO_COUNTER/icount_out_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              9   0.591   0.855  Switches_8Bit/gpio_core_1/iGPIO_xferAck (Switches_8Bit/gpio_core_1/iGPIO_xferAck)
     LUT3:I2->O            8   0.704   0.761  Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/dpto_cntr_ld_en1 (Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/dpto_cntr_ld_en)
     LUT4:I3->O            2   0.704   0.447  Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/INCLUDE_DATA_PHASE_WDT.I_DPTO_COUNTER/icount_out_sub0000<8>1 (Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/INCLUDE_DATA_PHASE_WDT.I_DPTO_COUNTER/icount_out_sub0000<8>1)
     FDS:S                     0.911          Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/INCLUDE_DATA_PHASE_WDT.I_DPTO_COUNTER/icount_out_7
    ----------------------------------------
    Total                      4.973ns (2.910ns logic, 2.063ns route)
                                       (58.5% logic, 41.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SPLB_Clk'
  Total number of paths / destination ports: 165 / 165
-------------------------------------------------------------------------
Offset:              2.547ns (Levels of Logic = 1)
  Source:            SPLB_Rst (PAD)
  Destination:       Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_31 (FF)
  Destination Clock: SPLB_Clk rising

  Data Path: SPLB_Rst to Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT4:I0->O            8   0.704   0.757  Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_or00001 (Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_or0000)
     FDR:R                     0.911          Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rddbus_i_31
    ----------------------------------------
    Total                      2.547ns (1.790ns logic, 0.757ns route)
                                       (70.3% logic, 29.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'SPLB_Clk'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              0.591ns (Levels of Logic = 0)
  Source:            Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rearbitrate_i (FF)
  Destination:       Sl_rearbitrate (PAD)
  Source Clock:      SPLB_Clk rising

  Data Path: Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rearbitrate_i to Sl_rearbitrate
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              0   0.591   0.000  Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rearbitrate_i (Switches_8Bit/PLBV46_I/I_SLAVE_ATTACHMENT/sl_rearbitrate_i)
    ----------------------------------------
    Total                      0.591ns (0.591ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================


Total REAL time to Xst completion: 17.00 secs
Total CPU time to Xst completion: 17.00 secs
 
--> 

Total memory usage is 207160 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  172 (   0 filtered)
Number of infos    :    2 (   0 filtered)

