
----------------------------------------------------------------------------
--                            Design Analysis                             --
----------------------------------------------------------------------------
Analyze pcore my_timer ...


----------------------------------------------------------------------------
--                            File Generation                             --
----------------------------------------------------------------------------
Creating HDL source directory ...
Generating top peripheral VHDL template ...
Generating stub user logic VHDL template ...
HDL templates successfully generated ...
Creating data directory ...
Generating XPS inteface files ...
Compiling vhdl file
"C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file
"C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_0
1_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_single_v1
_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Temp/Bomberman/pcores/my_timer_v1_00_a/data/../hdl/vhdl/user_logic.vhd" in
Library my_timer_v1_00_a.
Entity <user_logic> compiled.
Entity <user_logic> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Temp/Bomberman/pcores/my_timer_v1_00_a/data/../hdl/vhdl/my_timer.vhd" in
Library my_timer_v1_00_a.
Entity <my_timer> compiled.
Entity <my_timer> (Architecture <IMP>) compiled.


Analyzing HDL attributes ...
Entity name = my_timer
INFO:EDK:1607 - IPTYPE set to value : PERIPHERAL
INFO:EDK:1511 - IMP_NETLIST set to value : TRUE
INFO:EDK:1486 - HDL set to value : VHDL
WARNING:EDK:3588 - Unable to delete temporary XST project file
   C:\Temp\Bomberman\pcores\my_timer_v1_00_a\data\_my_timer_xst.prj : 13
XPS interface files successfully generated ...
Creating development directory ...
Generating command option file ...
Generating readme file ...
Development misc files successfully generated ...
No ProjNavigator support files will be generated at this time ...
No XST synthesis support files will be generated at this time ...
No BFM simulation files will be generated at this time ...
No software driver files will be generated at this time ...

----------------------------------------------------------------------------
--                              Final Report                              --
----------------------------------------------------------------------------
Thank you for using Create and Import Peripheral Wizard! Please find your
peripheral hardware templates under C:\Temp\Bomberman/pcores/my_timer_v1_00_a.

Peripheral Summary:

  top name       : my_timer
  version        : 1.00.a
  type           : PLB (v4.6) slave
  features       : slave attachment
                   interrupt control
                   user s/w registers

Address Block Summary:

  user logic slv : C_BASEADDR + 0x00000000
                 : C_BASEADDR + 0x000000FF
  interrupt      : C_BASEADDR + 0x00000100
                 : C_BASEADDR + 0x000001FF

File Summary

  - HDL source -
  C:\Temp\Bomberman/pcores/my_timer_v1_00_a/hdl
  top entity     : vhdl/my_timer.vhd
  user logic     : vhdl/user_logic.vhd

  - XPS interface -
  C:\Temp\Bomberman/pcores/my_timer_v1_00_a/data
  mpd            : my_timer_v2_1_0.mpd
  pao            : my_timer_v2_1_0.pao

  - Misc file -
  C:\Temp\Bomberman/pcores/my_timer_v1_00_a/devl
  help           : README.txt
  option         : ipwiz.opt
  log            : ipwiz.log


