--------------------------------------------------------------------------------
Release 12.2 Trace  (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

C:\Xilinx\12.2\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 4 -n
3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf top.ucf

Design file:              top.ncd
Physical constraint file: top.pcf
Device,package,speed:     xc3s1200e,fg320,-4 (PRODUCTION 1.27 2010-06-22)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.

================================================================================
Timing constraint: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 50 MHz HIGH 
50%;

 3 paths analyzed, 3 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   6.000ns.
--------------------------------------------------------------------------------

Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti (SLICE_X60Y118.BY), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     18.212ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2 (FF)
  Destination:          Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti (FF)
  Requirement:          20.000ns
  Data Path Delay:      1.786ns (Levels of Logic = 0)
  Clock Path Skew:      -0.002ns (0.001 - 0.003)
  Source Clock:         fpga_0_clk_1_sys_clk_pin_IBUF rising at 0.000ns
  Destination Clock:    fpga_0_clk_1_sys_clk_pin_IBUF rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2 to Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X62Y119.YQ     Tcko                  0.652   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<2>
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2
    SLICE_X60Y118.BY     net (fanout=1)        0.752   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<2>
    SLICE_X60Y118.CLK    Tdick                 0.382   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti
    -------------------------------------------------  ---------------------------
    Total                                      1.786ns (1.034ns logic, 0.752ns route)
                                                       (57.9% logic, 42.1% route)

--------------------------------------------------------------------------------

Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1 (SLICE_X63Y118.BX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     18.351ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0 (FF)
  Destination:          Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1 (FF)
  Requirement:          20.000ns
  Data Path Delay:      1.649ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         fpga_0_clk_1_sys_clk_pin_IBUF rising at 0.000ns
  Destination Clock:    fpga_0_clk_1_sys_clk_pin_IBUF rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0 to Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X63Y118.YQ     Tcko                  0.587   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<1>
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0
    SLICE_X63Y118.BX     net (fanout=1)        0.754   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<0>
    SLICE_X63Y118.CLK    Tdick                 0.308   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<1>
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1
    -------------------------------------------------  ---------------------------
    Total                                      1.649ns (0.895ns logic, 0.754ns route)
                                                       (54.3% logic, 45.7% route)

--------------------------------------------------------------------------------

Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2 (SLICE_X62Y119.BY), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     18.553ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1 (FF)
  Destination:          Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2 (FF)
  Requirement:          20.000ns
  Data Path Delay:      1.447ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         fpga_0_clk_1_sys_clk_pin_IBUF rising at 0.000ns
  Destination Clock:    fpga_0_clk_1_sys_clk_pin_IBUF rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1 to Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X63Y118.XQ     Tcko                  0.591   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<1>
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1
    SLICE_X62Y119.BY     net (fanout=1)        0.474   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<1>
    SLICE_X62Y119.CLK    Tdick                 0.382   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<2>
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2
    -------------------------------------------------  ---------------------------
    Total                                      1.447ns (0.973ns logic, 0.474ns route)
                                                       (67.2% logic, 32.8% route)

--------------------------------------------------------------------------------

Hold Paths: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 50 MHz HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2 (SLICE_X62Y119.BY), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.408ns (requirement - (clock path skew + uncertainty - data path))
  Source:               Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1 (FF)
  Destination:          Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.004ns (Levels of Logic = 0)
  Clock Path Skew:      0.596ns (0.826 - 0.230)
  Source Clock:         fpga_0_clk_1_sys_clk_pin_IBUF rising at 20.000ns
  Destination Clock:    fpga_0_clk_1_sys_clk_pin_IBUF rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1 to Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X63Y118.XQ     Tcko                  0.473   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<1>
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1
    SLICE_X62Y119.BY     net (fanout=1)        0.379   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<1>
    SLICE_X62Y119.CLK    Tckdi       (-Th)    -0.152   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<2>
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2
    -------------------------------------------------  ---------------------------
    Total                                      1.004ns (0.625ns logic, 0.379ns route)
                                                       (62.3% logic, 37.7% route)

--------------------------------------------------------------------------------

Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1 (SLICE_X63Y118.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      1.166ns (requirement - (clock path skew + uncertainty - data path))
  Source:               Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0 (FF)
  Destination:          Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.166ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         fpga_0_clk_1_sys_clk_pin_IBUF rising at 20.000ns
  Destination Clock:    fpga_0_clk_1_sys_clk_pin_IBUF rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0 to Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X63Y118.YQ     Tcko                  0.470   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<1>
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0
    SLICE_X63Y118.BX     net (fanout=1)        0.603   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<0>
    SLICE_X63Y118.CLK    Tckdi       (-Th)    -0.093   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<1>
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1
    -------------------------------------------------  ---------------------------
    Total                                      1.166ns (0.563ns logic, 0.603ns route)
                                                       (48.3% logic, 51.7% route)

--------------------------------------------------------------------------------

Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti (SLICE_X60Y118.BY), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      1.277ns (requirement - (clock path skew + uncertainty - data path))
  Source:               Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2 (FF)
  Destination:          Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.275ns (Levels of Logic = 0)
  Clock Path Skew:      -0.002ns (0.001 - 0.003)
  Source Clock:         fpga_0_clk_1_sys_clk_pin_IBUF rising at 20.000ns
  Destination Clock:    fpga_0_clk_1_sys_clk_pin_IBUF rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2 to Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X62Y119.YQ     Tcko                  0.522   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<2>
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2
    SLICE_X60Y118.BY     net (fanout=1)        0.601   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay<2>
    SLICE_X60Y118.CLK    Tckdi       (-Th)    -0.152   Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti
                                                       Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti
    -------------------------------------------------  ---------------------------
    Total                                      1.275ns (0.674ns logic, 0.601ns route)
                                                       (52.9% logic, 47.1% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 50 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: 14.000ns (period - (min low pulse limit / (low pulse / period)))
  Period: 20.000ns
  Low pulse: 10.000ns
  Low pulse limit: 3.000ns (Tdcmpw_CLKIN_50_100)
  Physical resource: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN
  Logical resource: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN
  Location pin: DCM_X1Y3.CLKIN
  Clock network: fpga_0_clk_1_sys_clk_pin_IBUF
--------------------------------------------------------------------------------
Slack: 14.000ns (period - (min high pulse limit / (high pulse / period)))
  Period: 20.000ns
  High pulse: 10.000ns
  High pulse limit: 3.000ns (Tdcmpw_CLKIN_50_100)
  Physical resource: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN
  Logical resource: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN
  Location pin: DCM_X1Y3.CLKIN
  Clock network: fpga_0_clk_1_sys_clk_pin_IBUF
--------------------------------------------------------------------------------
Slack: 15.834ns (period - min period limit)
  Period: 20.000ns
  Min period limit: 4.166ns (240.038MHz) (Tdcmpc)
  Physical resource: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN
  Logical resource: Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN
  Location pin: DCM_X1Y3.CLKIN
  Clock network: fpga_0_clk_1_sys_clk_pin_IBUF
--------------------------------------------------------------------------------

================================================================================
Timing constraint: 
TS_Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0 = PERIOD       
  TIMEGRP         
"Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0"         
TS_sys_clk_pin HIGH 50%;

 3593254 paths analyzed, 18413 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  19.958ns.
--------------------------------------------------------------------------------

Paths for end point Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A (RAMB16_X1Y4.ADDRA7), 109502 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.042ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_0 (FF)
  Destination:          Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A (RAM)
  Requirement:          20.000ns
  Data Path Delay:      19.958ns (Levels of Logic = 13)
  Clock Path Skew:      0.000ns
  Source Clock:         Inst_system/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_0 to Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X60Y55.YQ      Tcko                  0.652   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0<1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_0
    SLICE_X65Y51.G2      net (fanout=446)      2.336   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0<0>
    SLICE_X65Y51.Y       Tilo                  0.704   Inst_system/graph_acc_0/N5594
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_7_mux0003<0>31_SW1_SW0
    SLICE_X77Y66.G3      net (fanout=14)       1.440   Inst_system/graph_acc_0/N8455
    SLICE_X77Y66.Y       Tilo                  0.704   Inst_system/graph_acc_0/N5520
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>31_SW1
    SLICE_X74Y72.G4      net (fanout=1)        1.460   Inst_system/graph_acc_0/N5472
    SLICE_X74Y72.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><3><0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>_SW0_SW0
    SLICE_X74Y72.F4      net (fanout=1)        0.023   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>_SW0_SW0/O
    SLICE_X74Y72.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><3><0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>
    SLICE_X72Y73.G2      net (fanout=1)        0.434   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><3><0>
    SLICE_X72Y73.F5      Tif5                  1.033   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f512
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_1615
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f5_11
    SLICE_X72Y72.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f512
    SLICE_X72Y72.FX      Tinbfx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f519
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f6_8
    SLICE_X72Y73.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f69
    SLICE_X72Y73.FX      Tinafx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f512
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f7_2
    SLICE_X73Y73.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f73
    SLICE_X73Y73.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f8
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f8
    SLICE_X71Y37.G1      net (fanout=1)        1.641   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f8
    SLICE_X71Y37.F5      Tif5                  0.875   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_6
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5
    SLICE_X71Y36.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5
    SLICE_X71Y36.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6
    SLICE_X68Y30.G3      net (fanout=7)        0.855   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
    SLICE_X68Y30.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>31
    SLICE_X68Y30.F4      net (fanout=4)        0.051   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N566
    SLICE_X68Y30.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
    SLICE_X70Y30.G3      net (fanout=1)        0.345   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
    SLICE_X70Y30.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>20
    RAMB16_X1Y4.ADDRA7   net (fanout=3)        1.463   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>
    RAMB16_X1Y4.CLKA     Tback                 0.377   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    -------------------------------------------------  ---------------------------
    Total                                     19.958ns (9.910ns logic, 10.048ns route)
                                                       (49.7% logic, 50.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.062ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1 (FF)
  Destination:          Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A (RAM)
  Requirement:          20.000ns
  Data Path Delay:      19.938ns (Levels of Logic = 13)
  Clock Path Skew:      0.000ns
  Source Clock:         Inst_system/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1 to Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X57Y57.YQ      Tcko                  0.587   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1
    SLICE_X48Y58.G1      net (fanout=9)        1.772   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1
    SLICE_X48Y58.Y       Tilo                  0.759   Inst_system/graph_acc_0/N1042
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<7>_8_cmp_eq00031
    SLICE_X59Y65.F4      net (fanout=41)       1.284   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<7>_8_cmp_eq0003
    SLICE_X59Y65.X       Tilo                  0.704   Inst_system/graph_acc_0/N1138
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3>_8_mux0003<0>2_SW0
    SLICE_X45Y62.G3      net (fanout=1)        0.959   Inst_system/graph_acc_0/N1138
    SLICE_X45Y62.Y       Tilo                  0.704   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3><8><3>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3>_8_mux0003<0>2
    SLICE_X44Y62.F1      net (fanout=4)        0.468   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N420
    SLICE_X44Y62.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3><8><0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3>_8_mux0003<0>
    SLICE_X39Y59.F2      net (fanout=1)        0.943   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3><8><0>
    SLICE_X39Y59.F5      Tif5                  0.875   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f51
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_158
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f5_0
    SLICE_X39Y58.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f51
    SLICE_X39Y58.FX      Tinbfx                0.463   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f56
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f6_0
    SLICE_X38Y59.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f61
    SLICE_X38Y59.FX      Tinbfx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f55
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f7_0
    SLICE_X39Y57.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f71
    SLICE_X39Y57.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f81
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f8_0
    SLICE_X71Y36.G4      net (fanout=1)        2.012   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f81
    SLICE_X71Y36.F5      Tif5                  0.875   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_5
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f5
    SLICE_X71Y36.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f5
    SLICE_X71Y36.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6
    SLICE_X68Y30.G3      net (fanout=7)        0.855   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
    SLICE_X68Y30.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>31
    SLICE_X68Y30.F4      net (fanout=4)        0.051   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N566
    SLICE_X68Y30.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
    SLICE_X70Y30.G3      net (fanout=1)        0.345   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
    SLICE_X70Y30.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>20
    RAMB16_X1Y4.ADDRA7   net (fanout=3)        1.463   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>
    RAMB16_X1Y4.CLKA     Tback                 0.377   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    -------------------------------------------------  ---------------------------
    Total                                     19.938ns (9.786ns logic, 10.152ns route)
                                                       (49.1% logic, 50.9% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.066ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1 (FF)
  Destination:          Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A (RAM)
  Requirement:          20.000ns
  Data Path Delay:      19.934ns (Levels of Logic = 13)
  Clock Path Skew:      0.000ns
  Source Clock:         Inst_system/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1 to Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X57Y57.YQ      Tcko                  0.587   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1
    SLICE_X48Y58.G1      net (fanout=9)        1.772   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1
    SLICE_X48Y58.Y       Tilo                  0.759   Inst_system/graph_acc_0/N1042
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<7>_8_cmp_eq00031
    SLICE_X36Y65.G4      net (fanout=41)       1.688   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<7>_8_cmp_eq0003
    SLICE_X36Y65.Y       Tilo                  0.759   Inst_system/graph_acc_0/N140
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_8_mux0003<3>_SW0_SW0
    SLICE_X38Y60.G2      net (fanout=4)        1.324   Inst_system/graph_acc_0/N9353
    SLICE_X38Y60.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><8><0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_8_mux0003<0>_SW0_SW0
    SLICE_X38Y60.F4      net (fanout=1)        0.023   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_8_mux0003<0>_SW0_SW0/O
    SLICE_X38Y60.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><8><0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_8_mux0003<0>
    SLICE_X38Y59.G1      net (fanout=1)        0.446   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><8><0>
    SLICE_X38Y59.F5      Tif5                  1.033   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f55
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_156
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f5_4
    SLICE_X38Y58.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f55
    SLICE_X38Y58.FX      Tinbfx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f58
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f6_3
    SLICE_X38Y59.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f64
    SLICE_X38Y59.FX      Tinafx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f55
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f7_0
    SLICE_X39Y57.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f71
    SLICE_X39Y57.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f81
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f8_0
    SLICE_X71Y36.G4      net (fanout=1)        2.012   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f81
    SLICE_X71Y36.F5      Tif5                  0.875   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_5
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f5
    SLICE_X71Y36.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f5
    SLICE_X71Y36.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6
    SLICE_X68Y30.G3      net (fanout=7)        0.855   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
    SLICE_X68Y30.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>31
    SLICE_X68Y30.F4      net (fanout=4)        0.051   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N566
    SLICE_X68Y30.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
    SLICE_X70Y30.G3      net (fanout=1)        0.345   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>8
    SLICE_X70Y30.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>20
    RAMB16_X1Y4.ADDRA7   net (fanout=3)        1.463   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<5>
    RAMB16_X1Y4.CLKA     Tback                 0.377   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    -------------------------------------------------  ---------------------------
    Total                                     19.934ns (9.955ns logic, 9.979ns route)
                                                       (49.9% logic, 50.1% route)

--------------------------------------------------------------------------------

Paths for end point Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram.A (RAMB16_X1Y2.ADDRA2), 109138 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.048ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_30 (FF)
  Destination:          Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram.A (RAM)
  Requirement:          20.000ns
  Data Path Delay:      19.952ns (Levels of Logic = 13)
  Clock Path Skew:      0.000ns
  Source Clock:         Inst_system/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_30 to Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X58Y58.YQ      Tcko                  0.652   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0<31>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_30
    SLICE_X52Y44.G1      net (fanout=402)      3.012   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0<30>
    SLICE_X52Y44.Y       Tilo                  0.759   Inst_system/graph_acc_0/N7136
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_12_mux0003<0>31_SW3_SW0
    SLICE_X52Y44.F4      net (fanout=4)        0.084   Inst_system/graph_acc_0/N9173
    SLICE_X52Y44.X       Tilo                  0.759   Inst_system/graph_acc_0/N7136
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_12_mux0003<0>31_SW3
    SLICE_X54Y33.G2      net (fanout=1)        1.309   Inst_system/graph_acc_0/N7136
    SLICE_X54Y33.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><12><1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_12_mux0003<1>_SW0_SW0
    SLICE_X54Y33.F3      net (fanout=1)        0.023   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_12_mux0003<1>_SW0_SW0/O
    SLICE_X54Y33.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><12><1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_12_mux0003<1>
    SLICE_X54Y19.G3      net (fanout=1)        0.956   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><12><1>
    SLICE_X54Y19.F5      Tif5                  1.033   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f516
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_1436
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f5_15
    SLICE_X54Y18.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f516
    SLICE_X54Y18.FX      Tinbfx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f58
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f6_5
    SLICE_X54Y19.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f66
    SLICE_X54Y19.FX      Tinafx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f516
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_9_f7_3
    SLICE_X55Y17.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_9_f74
    SLICE_X55Y17.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_7_f81
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_7_f8_0
    SLICE_X71Y40.F2      net (fanout=1)        1.458   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_7_f81
    SLICE_X71Y40.F5      Tif5                  0.875   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_41
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f5_0
    SLICE_X71Y40.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f51
    SLICE_X71Y40.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6_0
    SLICE_X72Y30.G2      net (fanout=7)        1.087   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<1>
    SLICE_X72Y30.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N261
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>2_SW0
    SLICE_X72Y30.F4      net (fanout=1)        0.023   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>2_SW0/O
    SLICE_X72Y30.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N261
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>2
    SLICE_X71Y31.F4      net (fanout=4)        0.358   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N261
    SLICE_X71Y31.X       Tilo                  0.704   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>211
    RAMB16_X1Y2.ADDRA2   net (fanout=3)        1.677   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>
    RAMB16_X1Y2.CLKA     Tback                 0.377   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    -------------------------------------------------  ---------------------------
    Total                                     19.952ns (9.965ns logic, 9.987ns route)
                                                       (49.9% logic, 50.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.051ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_22 (FF)
  Destination:          Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram.A (RAM)
  Requirement:          20.000ns
  Data Path Delay:      19.949ns (Levels of Logic = 12)
  Clock Path Skew:      0.000ns
  Source Clock:         Inst_system/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_22 to Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X59Y54.YQ      Tcko                  0.587   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0<23>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_22
    SLICE_X57Y51.G2      net (fanout=236)      1.306   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0<22>
    SLICE_X57Y51.Y       Tilo                  0.704   Inst_system/graph_acc_0/N5940
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<12>_10_cmp_eq00001
    SLICE_X43Y46.G2      net (fanout=96)       2.303   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<12>_10_cmp_eq0000
    SLICE_X43Y46.Y       Tilo                  0.704   Inst_system/graph_acc_0/N3982
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<12>_9_mux0003<1>_SW0_SW0_SW0
    SLICE_X43Y46.F2      net (fanout=1)        0.428   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<12>_9_mux0003<1>_SW0_SW0_SW0/O
    SLICE_X43Y46.X       Tilo                  0.704   Inst_system/graph_acc_0/N3982
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<12>_9_mux0003<1>_SW0_SW0
    SLICE_X40Y58.G1      net (fanout=1)        1.862   Inst_system/graph_acc_0/N3982
    SLICE_X40Y58.F5      Tif5                  1.033   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f510
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_1331
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f5_9
    SLICE_X40Y58.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f510
    SLICE_X40Y58.FX      Tinafx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f510
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f6_7
    SLICE_X40Y59.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f68
    SLICE_X40Y59.FX      Tinafx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f521
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_9_f7_5
    SLICE_X41Y59.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_9_f76
    SLICE_X41Y59.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f84
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f8_3
    SLICE_X71Y40.G4      net (fanout=1)        1.929   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f84
    SLICE_X71Y40.F5      Tif5                  0.875   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_52
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f5_0
    SLICE_X71Y40.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f51
    SLICE_X71Y40.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6_0
    SLICE_X72Y30.G2      net (fanout=7)        1.087   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<1>
    SLICE_X72Y30.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N261
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>2_SW0
    SLICE_X72Y30.F4      net (fanout=1)        0.023   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>2_SW0/O
    SLICE_X72Y30.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N261
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>2
    SLICE_X71Y31.F4      net (fanout=4)        0.358   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N261
    SLICE_X71Y31.X       Tilo                  0.704   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>211
    RAMB16_X1Y2.ADDRA2   net (fanout=3)        1.677   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>
    RAMB16_X1Y2.CLKA     Tback                 0.377   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    -------------------------------------------------  ---------------------------
    Total                                     19.949ns (8.976ns logic, 10.973ns route)
                                                       (45.0% logic, 55.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.061ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_0 (FF)
  Destination:          Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram.A (RAM)
  Requirement:          20.000ns
  Data Path Delay:      19.939ns (Levels of Logic = 13)
  Clock Path Skew:      0.000ns
  Source Clock:         Inst_system/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_0 to Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X60Y55.YQ      Tcko                  0.652   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0<1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_0
    SLICE_X65Y51.G2      net (fanout=446)      2.336   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0<0>
    SLICE_X65Y51.Y       Tilo                  0.704   Inst_system/graph_acc_0/N5594
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_7_mux0003<0>31_SW1_SW0
    SLICE_X77Y66.G3      net (fanout=14)       1.440   Inst_system/graph_acc_0/N8455
    SLICE_X77Y66.Y       Tilo                  0.704   Inst_system/graph_acc_0/N5520
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>31_SW1
    SLICE_X74Y72.G4      net (fanout=1)        1.460   Inst_system/graph_acc_0/N5472
    SLICE_X74Y72.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><3><0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>_SW0_SW0
    SLICE_X74Y72.F4      net (fanout=1)        0.023   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>_SW0_SW0/O
    SLICE_X74Y72.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><3><0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>
    SLICE_X72Y73.G2      net (fanout=1)        0.434   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><3><0>
    SLICE_X72Y73.F5      Tif5                  1.033   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f512
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_1615
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f5_11
    SLICE_X72Y72.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f512
    SLICE_X72Y72.FX      Tinbfx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f519
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f6_8
    SLICE_X72Y73.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f69
    SLICE_X72Y73.FX      Tinafx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f512
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f7_2
    SLICE_X73Y73.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f73
    SLICE_X73Y73.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f8
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f8
    SLICE_X71Y37.G1      net (fanout=1)        1.641   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f8
    SLICE_X71Y37.F5      Tif5                  0.875   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_6
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5
    SLICE_X71Y36.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5
    SLICE_X71Y36.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6
    SLICE_X71Y30.G2      net (fanout=7)        0.616   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
    SLICE_X71Y30.Y       Tilo                  0.704   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<9>10
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<1>21
    SLICE_X71Y31.G3      net (fanout=10)       0.139   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N522
    SLICE_X71Y31.Y       Tilo                  0.704   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>211_SW0
    SLICE_X71Y31.F2      net (fanout=1)        0.428   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>211_SW0/O
    SLICE_X71Y31.X       Tilo                  0.704   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>211
    RAMB16_X1Y2.ADDRA2   net (fanout=3)        1.677   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<0>
    RAMB16_X1Y2.CLKA     Tback                 0.377   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_init.ram/dpram.dp4x4.ram.A
    -------------------------------------------------  ---------------------------
    Total                                     19.939ns (9.745ns logic, 10.194ns route)
                                                       (48.9% logic, 51.1% route)

--------------------------------------------------------------------------------

Paths for end point Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A (RAMB16_X1Y3.ENA), 86408 paths
--------------------------------------------------------------------------------
Slack (setup path):     0.068ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_0 (FF)
  Destination:          Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A (RAM)
  Requirement:          20.000ns
  Data Path Delay:      19.932ns (Levels of Logic = 13)
  Clock Path Skew:      0.000ns
  Source Clock:         Inst_system/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_0 to Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X60Y55.YQ      Tcko                  0.652   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0<1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_0
    SLICE_X65Y51.G2      net (fanout=446)      2.336   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0<0>
    SLICE_X65Y51.Y       Tilo                  0.704   Inst_system/graph_acc_0/N5594
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_7_mux0003<0>31_SW1_SW0
    SLICE_X77Y66.G3      net (fanout=14)       1.440   Inst_system/graph_acc_0/N8455
    SLICE_X77Y66.Y       Tilo                  0.704   Inst_system/graph_acc_0/N5520
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>31_SW1
    SLICE_X74Y72.G4      net (fanout=1)        1.460   Inst_system/graph_acc_0/N5472
    SLICE_X74Y72.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><3><0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>_SW0_SW0
    SLICE_X74Y72.F4      net (fanout=1)        0.023   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>_SW0_SW0/O
    SLICE_X74Y72.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><3><0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9>_3_mux0003<0>
    SLICE_X72Y73.G2      net (fanout=1)        0.434   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<9><3><0>
    SLICE_X72Y73.F5      Tif5                  1.033   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f512
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_1615
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f5_11
    SLICE_X72Y72.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f512
    SLICE_X72Y72.FX      Tinbfx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f519
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f6_8
    SLICE_X72Y73.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f69
    SLICE_X72Y73.FX      Tinafx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f512
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f7_2
    SLICE_X73Y73.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f73
    SLICE_X73Y73.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f8
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f8
    SLICE_X71Y37.G1      net (fanout=1)        1.641   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f8
    SLICE_X71Y37.F5      Tif5                  0.875   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_6
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5
    SLICE_X71Y36.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5
    SLICE_X71Y36.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6
    SLICE_X72Y29.G4      net (fanout=7)        0.920   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
    SLICE_X72Y29.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<12>_SW0
    SLICE_X72Y29.F3      net (fanout=1)        0.023   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<12>_SW0/O
    SLICE_X72Y29.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<12>
    SLICE_X72Y28.G2      net (fanout=3)        0.146   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<12>
    SLICE_X72Y28.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq0000
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq00001
    RAMB16_X1Y3.ENA      net (fanout=1)        1.206   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq0000
    RAMB16_X1Y3.CLKA     Tbeck                 0.770   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A
    -------------------------------------------------  ---------------------------
    Total                                     19.932ns (10.303ns logic, 9.629ns route)
                                                       (51.7% logic, 48.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.088ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_14_1 (FF)
  Destination:          Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A (RAM)
  Requirement:          20.000ns
  Data Path Delay:      19.912ns (Levels of Logic = 12)
  Clock Path Skew:      0.000ns
  Source Clock:         Inst_system/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_14_1 to Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X58Y57.YQ      Tcko                  0.652   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_14_1
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_14_1
    SLICE_X60Y54.G1      net (fanout=24)       1.027   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_14_1
    SLICE_X60Y54.Y       Tilo                  0.759   Inst_system/graph_acc_0/N1044
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<1>_5_cmp_eq00011
    SLICE_X58Y21.G4      net (fanout=41)       2.949   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<1>_5_cmp_eq0001
    SLICE_X58Y21.Y       Tilo                  0.759   Inst_system/graph_acc_0/N4768
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<14>_5_mux0003<0>2_SW0
    SLICE_X59Y19.F2      net (fanout=4)        0.743   Inst_system/graph_acc_0/N2132
    SLICE_X59Y19.X       Tilo                  0.704   Inst_system/graph_acc_0/N4256
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<14>_5_mux0003<3>_SW1
    SLICE_X66Y50.F1      net (fanout=1)        1.988   Inst_system/graph_acc_0/N4256
    SLICE_X66Y50.F5      Tif5                  1.033   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f523
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_1227
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f5_22
    SLICE_X66Y50.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f523
    SLICE_X66Y50.FX      Tinafx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_11_f523
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f6_18
    SLICE_X66Y51.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f619
    SLICE_X66Y51.FX      Tinafx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f555
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_9_f7_14
    SLICE_X67Y51.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_9_f715
    SLICE_X67Y51.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f811
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f8_10
    SLICE_X69Y41.F3      net (fanout=1)        1.059   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f811
    SLICE_X69Y41.F5      Tif5                  0.875   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f53
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_57
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f5_2
    SLICE_X69Y40.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_4_f53
    SLICE_X69Y40.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<3>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6_2
    SLICE_X70Y28.G4      net (fanout=10)       0.854   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<3>
    SLICE_X70Y28.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<11>_SW0_SW0
    SLICE_X70Y28.F4      net (fanout=2)        0.042   Inst_system/graph_acc_0/N2584
    SLICE_X70Y28.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<11>
    SLICE_X72Y28.G4      net (fanout=3)        0.445   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<11>
    SLICE_X72Y28.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq0000
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq00001
    RAMB16_X1Y3.ENA      net (fanout=1)        1.206   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq0000
    RAMB16_X1Y3.CLKA     Tbeck                 0.770   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A
    -------------------------------------------------  ---------------------------
    Total                                     19.912ns (9.599ns logic, 10.313ns route)
                                                       (48.2% logic, 51.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.088ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1 (FF)
  Destination:          Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A (RAM)
  Requirement:          20.000ns
  Data Path Delay:      19.912ns (Levels of Logic = 13)
  Clock Path Skew:      0.000ns
  Source Clock:         Inst_system/clk_50_0000MHz rising at 0.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1 to Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X57Y57.YQ      Tcko                  0.587   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1
    SLICE_X48Y58.G1      net (fanout=9)        1.772   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1
    SLICE_X48Y58.Y       Tilo                  0.759   Inst_system/graph_acc_0/N1042
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<7>_8_cmp_eq00031
    SLICE_X59Y65.F4      net (fanout=41)       1.284   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<7>_8_cmp_eq0003
    SLICE_X59Y65.X       Tilo                  0.704   Inst_system/graph_acc_0/N1138
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3>_8_mux0003<0>2_SW0
    SLICE_X45Y62.G3      net (fanout=1)        0.959   Inst_system/graph_acc_0/N1138
    SLICE_X45Y62.Y       Tilo                  0.704   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3><8><3>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3>_8_mux0003<0>2
    SLICE_X44Y62.F1      net (fanout=4)        0.468   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N420
    SLICE_X44Y62.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3><8><0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3>_8_mux0003<0>
    SLICE_X39Y59.F2      net (fanout=1)        0.943   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard<3><8><0>
    SLICE_X39Y59.F5      Tif5                  0.875   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f51
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_158
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f5_0
    SLICE_X39Y58.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f51
    SLICE_X39Y58.FX      Tinbfx                0.463   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f56
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f6_0
    SLICE_X38Y59.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f61
    SLICE_X38Y59.FX      Tinbfx                0.364   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f55
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f7_0
    SLICE_X39Y57.FXINB   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f71
    SLICE_X39Y57.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f81
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f8_0
    SLICE_X71Y36.G4      net (fanout=1)        2.012   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f81
    SLICE_X71Y36.F5      Tif5                  0.875   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_5
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f5
    SLICE_X71Y36.FXINA   net (fanout=1)        0.000   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f5
    SLICE_X71Y36.Y       Tif6y                 0.521   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6
    SLICE_X72Y29.G4      net (fanout=7)        0.920   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016<0>
    SLICE_X72Y29.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<12>_SW0
    SLICE_X72Y29.F3      net (fanout=1)        0.023   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<12>_SW0/O
    SLICE_X72Y29.X       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe<1>
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<12>
    SLICE_X72Y28.G2      net (fanout=3)        0.146   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr<12>
    SLICE_X72Y28.Y       Tilo                  0.759   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq0000
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq00001
    RAMB16_X1Y3.ENA      net (fanout=1)        1.206   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq0000
    RAMB16_X1Y3.CLKA     Tbeck                 0.770   Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram
                                                       Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A
    -------------------------------------------------  ---------------------------
    Total                                     19.912ns (10.179ns logic, 9.733ns route)
                                                       (51.1% logic, 48.9% route)

--------------------------------------------------------------------------------

Hold Paths: TS_Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0 = PERIOD
        TIMEGRP
        "Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0"
        TS_sys_clk_pin HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point Inst_system/RS232_PORT/RS232_PORT/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/Mshreg_Dout_5_0 (SLICE_X32Y30.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.676ns (requirement - (clock path skew + uncertainty - data path))
  Source:               Inst_system/RS232_PORT/RS232_PORT/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_29 (FF)
  Destination:          Inst_system/RS232_PORT/RS232_PORT/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/Mshreg_Dout_5_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.677ns (Levels of Logic = 1)
  Clock Path Skew:      0.001ns (0.018 - 0.017)
  Source Clock:         Inst_system/clk_50_0000MHz rising at 20.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: Inst_system/RS232_PORT/RS232_PORT/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_29 to Inst_system/RS232_PORT/RS232_PORT/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/Mshreg_Dout_5_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X33Y33.XQ      Tcko                  0.473   Inst_system/RS232_PORT/RS232_PORT/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg<29>
                                                       Inst_system/RS232_PORT/RS232_PORT/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_29
    SLICE_X32Y30.BX      net (fanout=1)        0.353   Inst_system/RS232_PORT/RS232_PORT/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg<29>
    SLICE_X32Y30.CLK     Tdh         (-Th)     0.149   Inst_system/RS232_PORT/RS232_PORT/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_DOut<5>
                                                       Inst_system/RS232_PORT/RS232_PORT/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/Mshreg_Dout_5_0
    -------------------------------------------------  ---------------------------
    Total                                      0.677ns (0.324ns logic, 0.353ns route)
                                                       (47.9% logic, 52.1% route)

--------------------------------------------------------------------------------

Paths for end point Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/PC_OF_Buffer (SLICE_X20Y74.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.718ns (requirement - (clock path skew + uncertainty - data path))
  Source:               Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/Set_DFF.PC_IF_DFF (FF)
  Destination:          Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/PC_OF_Buffer (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.716ns (Levels of Logic = 1)
  Clock Path Skew:      -0.002ns (0.040 - 0.042)
  Source Clock:         Inst_system/clk_50_0000MHz rising at 20.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/Set_DFF.PC_IF_DFF to Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/PC_OF_Buffer
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X21Y76.YQ      Tcko                  0.470   Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/pc_I
                                                       Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/Set_DFF.PC_IF_DFF
    SLICE_X20Y74.BX      net (fanout=2)        0.395   Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/pc_I
    SLICE_X20Y74.CLK     Tdh         (-Th)     0.149   Inst_system/microblaze_0/microblaze_0/PC_EX_i<27>
                                                       Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/PC_OF_Buffer
    -------------------------------------------------  ---------------------------
    Total                                      0.716ns (0.321ns logic, 0.395ns route)
                                                       (44.8% logic, 55.2% route)

--------------------------------------------------------------------------------

Paths for end point Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/PC_OF_Buffer (SLICE_X22Y86.BX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.730ns (requirement - (clock path skew + uncertainty - data path))
  Source:               Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/Set_DFF.PC_IF_DFF (FF)
  Destination:          Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/PC_OF_Buffer (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.742ns (Levels of Logic = 1)
  Clock Path Skew:      0.012ns (0.047 - 0.035)
  Source Clock:         Inst_system/clk_50_0000MHz rising at 20.000ns
  Destination Clock:    Inst_system/clk_50_0000MHz rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/Set_DFF.PC_IF_DFF to Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/PC_OF_Buffer
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y84.YQ      Tcko                  0.470   Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/pc_I
                                                       Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/Set_DFF.PC_IF_DFF
    SLICE_X22Y86.BX      net (fanout=2)        0.421   Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/pc_I
    SLICE_X22Y86.CLK     Tdh         (-Th)     0.149   Inst_system/microblaze_0/microblaze_0/PC_EX_i<11>
                                                       Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/PC_OF_Buffer
    -------------------------------------------------  ---------------------------
    Total                                      0.742ns (0.321ns logic, 0.421ns route)
                                                       (43.3% logic, 56.7% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0 = PERIOD
        TIMEGRP
        "Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0"
        TS_sys_clk_pin HIGH 50%;
--------------------------------------------------------------------------------
Slack: 15.833ns (period - min period limit)
  Period: 20.000ns
  Min period limit: 4.167ns (239.981MHz) (Tmsper_P)
  Physical resource: Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_AD/CLK
  Logical resource: Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_AD/CLK
  Location pin: MULT18X18_X0Y8.CLK
  Clock network: Inst_system/clk_50_0000MHz
--------------------------------------------------------------------------------
Slack: 15.833ns (period - min period limit)
  Period: 20.000ns
  Min period limit: 4.167ns (239.981MHz) (Tmsper_P)
  Physical resource: Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_BC/CLK
  Logical resource: Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_BC/CLK
  Location pin: MULT18X18_X0Y6.CLK
  Clock network: Inst_system/clk_50_0000MHz
--------------------------------------------------------------------------------
Slack: 15.833ns (period - min period limit)
  Period: 20.000ns
  Min period limit: 4.167ns (239.981MHz) (Tmsper_P)
  Physical resource: Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_BD/CLK
  Logical resource: Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_BD/CLK
  Location pin: MULT18X18_X0Y7.CLK
  Clock network: Inst_system/clk_50_0000MHz
--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin                 |     20.000ns|      6.000ns|     19.958ns|            0|            0|            3|      3593254|
| TS_Inst_system_clock_generator|     20.000ns|     19.958ns|          N/A|            0|            0|      3593254|            0|
| _0_clock_generator_0_SIG_DCM0_|             |             |             |             |             |             |             |
| CLK0                          |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock fpga_0_clk_1_sys_clk_pin
------------------------+---------+---------+---------+---------+
                        | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock            |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
------------------------+---------+---------+---------+---------+
fpga_0_clk_1_sys_clk_pin|   19.958|         |         |         |
------------------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 3593257 paths, 0 nets, and 44088 connections

Design statistics:
   Minimum period:  19.958ns{1}   (Maximum frequency:  50.105MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Tue Oct 04 11:50:50 2011 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 184 MB



