----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:21:18 10/03/2011 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
    Port ( 	
		fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin : IN std_logic_vector(0 to 2);
		fpga_0_Switches_8Bit_GPIO_IO_I_pin : IN std_logic_vector(0 to 7);
		fpga_0_RS232_PORT_RX_pin : IN std_logic;
		fpga_0_clk_1_sys_clk_pin : IN std_logic;
		fpga_0_rst_1_sys_rst_pin : IN std_logic;    
		fpga_0_Micron_RAM_Mem_DQ_pin : INOUT std_logic_vector(0 to 15);
		xps_ps2_0_PS2_1_DATA : INOUT std_logic;
		xps_ps2_0_PS2_1_CLK : INOUT std_logic;      
		fpga_0_LEDs_8Bit_GPIO_IO_O_pin : OUT std_logic_vector(0 to 7);
		fpga_0_LED_7SEGMENT_GPIO_IO_O_pin : OUT std_logic_vector(0 to 11);
		fpga_0_RS232_PORT_TX_pin : OUT std_logic;
		fpga_0_Micron_RAM_Mem_A_pin : OUT std_logic_vector(9 to 31);
		fpga_0_Micron_RAM_Mem_OEN_pin : OUT std_logic;
		fpga_0_Micron_RAM_Mem_WEN_pin : OUT std_logic;
		fpga_0_Micron_RAM_Mem_BEN_pin : OUT std_logic_vector(0 to 1);
		graph_acc_0_HS_pin : OUT std_logic;
		graph_acc_0_VS_pin : OUT std_logic;
		graph_acc_0_VGA_rgb_pin : OUT std_logic_vector(0 to 7)
		);
end top;

architecture Behavioral of top is

	COMPONENT system
	PORT(
		fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin : IN std_logic_vector(0 to 2);
		fpga_0_Switches_8Bit_GPIO_IO_I_pin : IN std_logic_vector(0 to 7);
		fpga_0_RS232_PORT_RX_pin : IN std_logic;
		fpga_0_clk_1_sys_clk_pin : IN std_logic;
		fpga_0_rst_1_sys_rst_pin : IN std_logic;    
		fpga_0_Micron_RAM_Mem_DQ_pin : INOUT std_logic_vector(0 to 15);
		xps_ps2_0_PS2_1_DATA : INOUT std_logic;
		xps_ps2_0_PS2_1_CLK : INOUT std_logic;      
		fpga_0_LEDs_8Bit_GPIO_IO_O_pin : OUT std_logic_vector(0 to 7);
		fpga_0_LED_7SEGMENT_GPIO_IO_O_pin : OUT std_logic_vector(0 to 11);
		fpga_0_RS232_PORT_TX_pin : OUT std_logic;
		fpga_0_Micron_RAM_Mem_A_pin : OUT std_logic_vector(9 to 31);
		fpga_0_Micron_RAM_Mem_OEN_pin : OUT std_logic;
		fpga_0_Micron_RAM_Mem_WEN_pin : OUT std_logic;
		fpga_0_Micron_RAM_Mem_BEN_pin : OUT std_logic_vector(0 to 1);
		graph_acc_0_HS_pin : OUT std_logic;
		graph_acc_0_VS_pin : OUT std_logic;
		graph_acc_0_VGA_rgb_pin : OUT std_logic_vector(0 to 7)
		);
	END COMPONENT;
	
begin

	Inst_system: system PORT MAP(
		fpga_0_LEDs_8Bit_GPIO_IO_O_pin => fpga_0_LEDs_8Bit_GPIO_IO_O_pin,
		fpga_0_LED_7SEGMENT_GPIO_IO_O_pin => fpga_0_LED_7SEGMENT_GPIO_IO_O_pin,
		fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin => fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin,
		fpga_0_Switches_8Bit_GPIO_IO_I_pin => fpga_0_Switches_8Bit_GPIO_IO_I_pin,
		fpga_0_RS232_PORT_RX_pin => fpga_0_RS232_PORT_RX_pin,
		fpga_0_RS232_PORT_TX_pin => fpga_0_RS232_PORT_TX_pin,
		fpga_0_Micron_RAM_Mem_A_pin => fpga_0_Micron_RAM_Mem_A_pin,
		fpga_0_Micron_RAM_Mem_OEN_pin => fpga_0_Micron_RAM_Mem_OEN_pin,
		fpga_0_Micron_RAM_Mem_WEN_pin => fpga_0_Micron_RAM_Mem_WEN_pin,
		fpga_0_Micron_RAM_Mem_BEN_pin => fpga_0_Micron_RAM_Mem_BEN_pin,
		fpga_0_Micron_RAM_Mem_DQ_pin => fpga_0_Micron_RAM_Mem_DQ_pin,
		fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
		fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin,
		xps_ps2_0_PS2_1_DATA => xps_ps2_0_PS2_1_DATA,
		xps_ps2_0_PS2_1_CLK => xps_ps2_0_PS2_1_CLK,
		graph_acc_0_HS_pin => graph_acc_0_HS_pin,
		graph_acc_0_VS_pin => graph_acc_0_VS_pin,
		graph_acc_0_VGA_rgb_pin => graph_acc_0_VGA_rgb_pin
	);
end Behavioral;

