Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "micron_ram_wrapper_xst.prj"
Verilog Include Directory          : {"C:\Temp\Bomberman\pcores\" "C:\Xilinx\12.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc3s1200efg320-4
Output File Name                   : "../implementation/micron_ram_wrapper.ngc"

---- Source Options
Top Module Name                    : micron_ram_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation/micron_ram_wrapper}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/inferred_lut4.vhd" in Library proc_common_v3_00_a.
Entity <inferred_lut4> compiled.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/muxf_struct_f.vhd" in Library proc_common_v3_00_a.
Entity <muxf_struct> compiled.
Entity <muxf_struct> (Architecture <imp>) compiled.
Entity <muxf_struct_f> compiled.
Entity <muxf_struct_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_bit> compiled.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/cntr_incr_decr_addn_f.vhd" in Library proc_common_v3_00_a.
Entity <cntr_incr_decr_addn_f> compiled.
Entity <cntr_incr_decr_addn_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_f> compiled.
Entity <dynshreg_f> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_adder_bit.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder_bit> compiled.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter> compiled.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_occ_counter.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter> compiled.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_bit.vhd" in Library proc_common_v3_00_a.
Entity <counter_bit> compiled.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy_f.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy_f> compiled.
Entity <or_muxcy_f> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu_f> compiled.
Entity <srl_fifo_rbu_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family.vhd" in Library proc_common_v3_00_a.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_occ_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_occ_counter_top> compiled.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_counter_top.vhd" in Library proc_common_v3_00_a.
Entity <pf_counter_top> compiled.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_adder.vhd" in Library proc_common_v3_00_a.
Entity <pf_adder> compiled.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter.vhd" in Library proc_common_v3_00_a.
Entity <Counter> compiled.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/coregen_comp_defs.vhd" in Library proc_common_v3_00_a.
Package <coregen_comp_defs> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/common_types_pkg.vhd" in Library proc_common_v3_00_a.
Package <Common_Types> compiled.
WARNING:HDLParsers:3534 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/common_types_pkg.vhd" Line 223. In the function Get_RLOC_Name, not all control paths contain a return statement.
Package body <Common_Types> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/conv_funs_pkg.vhd" in Library proc_common_v3_00_a.
Package <conv_funs_pkg> compiled.
Package body <conv_funs_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/async_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <async_fifo_fg> compiled.
Entity <async_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/sync_fifo_fg.vhd" in Library proc_common_v3_00_a.
Entity <sync_fifo_fg> compiled.
Entity <sync_fifo_fg> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/blk_mem_gen_wrapper.vhd" in Library proc_common_v3_00_a.
Entity <blk_mem_gen_wrapper> compiled.
Entity <blk_mem_gen_wrapper> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/addsub.vhd" in Library proc_common_v3_00_a.
Entity <addsub> compiled.
Entity <addsub> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/direct_path_cntr.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr> compiled.
Entity <direct_path_cntr> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/direct_path_cntr_ai.vhd" in Library proc_common_v3_00_a.
Entity <direct_path_cntr_ai> compiled.
Entity <direct_path_cntr_ai> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/down_counter.vhd" in Library proc_common_v3_00_a.
Entity <down_counter> compiled.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/eval_timer.vhd" in Library proc_common_v3_00_a.
Entity <eval_timer> compiled.
Entity <eval_timer> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_steer.vhd" in Library proc_common_v3_00_a.
Entity <IPIF_Steer> compiled.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_steer128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_steer128> compiled.
Entity <ipif_steer128> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_mirror128.vhd" in Library proc_common_v3_00_a.
Entity <ipif_mirror128> compiled.
Entity <ipif_mirror128> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg> compiled.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg2.vhd" in Library proc_common_v3_00_a.
Entity <ld_arith_reg2> compiled.
Entity <ld_arith_reg2> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/mux_onehot.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_bits.vhd" in Library proc_common_v3_00_a.
Entity <or_bits> compiled.
Entity <or_bits> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate.vhd" in Library proc_common_v3_00_a.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pf_dpram_select.vhd" in Library proc_common_v3_00_a.
Entity <pf_dpram_select> compiled.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect.vhd" in Library proc_common_v3_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_mask.vhd" in Library proc_common_v3_00_a.
Entity <pselect_mask> compiled.
Entity <pselect_mask> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl16_fifo.vhd" in Library proc_common_v3_00_a.
Entity <srl16_fifo> compiled.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo.vhd" in Library proc_common_v3_00_a.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo2.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo2> compiled.
Entity <srl_fifo2> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo3.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo3> compiled.
Entity <srl_fifo3> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_rbu.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_rbu> compiled.
Entity <srl_fifo_rbu> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/valid_be.vhd" in Library proc_common_v3_00_a.
Entity <valid_be> compiled.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_with_enable_f.vhd" in Library proc_common_v3_00_a.
Entity <or_with_enable_f> compiled.
Entity <or_with_enable_f> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/dynshreg_i_f.vhd" in Library proc_common_v3_00_a.
Entity <dynshreg_i_f> compiled.
Entity <dynshreg_i_f> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/mux_onehot_f.vhd" in Library proc_common_v3_00_a.
Entity <mux_onehot_f> compiled.
Entity <mux_onehot_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/srl_fifo_f.vhd" in Library proc_common_v3_00_a.
Entity <srl_fifo_f> compiled.
Entity <srl_fifo_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/compare_vectors_f.vhd" in Library proc_common_v3_00_a.
Entity <compare_vectors_f> compiled.
Entity <compare_vectors_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate_f.vhd" in Library proc_common_v3_00_a.
Entity <or_gate_f> compiled.
Entity <or_gate_f> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/soft_reset.vhd" in Library proc_common_v3_00_a.
Entity <soft_reset> compiled.
Entity <soft_reset> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <flex_addr_cntr> compiled.
Entity <flex_addr_cntr> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <be_reset_gen> compiled.
Entity <be_reset_gen> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <wr_buffer> compiled.
Entity <wr_buffer> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <burst_support> compiled.
Entity <burst_support> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <addr_reg_cntr_brst_flex> compiled.
Entity <addr_reg_cntr_brst_flex> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/access_buffer.vhd" in Library mch_plbv46_slave_burst_v2_01_a.
Entity <access_buffer> compiled.
Entity <access_buffer> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/readdata_buffer.vhd" in Library mch_plbv46_slave_burst_v2_01_a.
Entity <readdata_buffer> compiled.
Entity <readdata_buffer> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/chnl_logic.vhd" in Library mch_plbv46_slave_burst_v2_01_a.
Entity <chnl_logic> compiled.
Entity <chnl_logic> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/addr_be_gen.vhd" in Library mch_plbv46_slave_burst_v2_01_a.
Entity <addr_be_gen> compiled.
Entity <addr_be_gen> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/ipic_logic.vhd" in Library mch_plbv46_slave_burst_v2_01_a.
Entity <ipic_logic> compiled.
Entity <ipic_logic> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/arbitration_logic.vhd" in Library mch_plbv46_slave_burst_v2_01_a.
Entity <arbitration_logic> compiled.
Entity <arbitration_logic> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/addr_data_mux_demux.vhd" in Library mch_plbv46_slave_burst_v2_01_a.
Entity <addr_data_mux_demux> compiled.
Entity <addr_data_mux_demux> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <data_mirror_128> compiled.
Entity <data_mirror_128> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/ipic_if.vhd" in Library emc_common_v4_01_a.
Entity <ipic_if> compiled.
Entity <ipic_if> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/mem_state_machine.vhd" in Library emc_common_v4_01_a.
Entity <mem_state_machine> compiled.
Entity <mem_state_machine> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/addr_counter_mux.vhd" in Library emc_common_v4_01_a.
Entity <addr_counter_mux> compiled.
Entity <addr_counter_mux> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/counters.vhd" in Library emc_common_v4_01_a.
Entity <counters> compiled.
Entity <counters> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/select_param.vhd" in Library emc_common_v4_01_a.
Entity <select_param> compiled.
Entity <select_param> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/mem_steer.vhd" in Library emc_common_v4_01_a.
Entity <mem_steer> compiled.
Entity <mem_steer> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/io_registers.vhd" in Library emc_common_v4_01_a.
Entity <io_registers> compiled.
Entity <io_registers> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <plbv46_slave_burst> compiled.
Entity <plbv46_slave_burst> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/arb_mux_demux.vhd" in Library mch_plbv46_slave_burst_v2_01_a.
Entity <arb_mux_demux> compiled.
Entity <arb_mux_demux> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_interface.vhd" in Library mch_plbv46_slave_burst_v2_01_a.
Entity <mch_interface> compiled.
Entity <mch_interface> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" in Library mch_plbv46_slave_burst_v2_01_a.
Entity <mch_plbv46_slave_burst> compiled.
Entity <mch_plbv46_slave_burst> (Architecture <imp>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/emc.vhd" in Library emc_common_v4_01_a.
Entity <EMC> compiled.
Entity <EMC> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" in Library xps_mch_emc_v3_01_a.
Entity <xps_mch_emc> compiled.
Entity <xps_mch_emc> (Architecture <implementation>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/hdl/micron_ram_wrapper.vhd" in Library work.
Entity <micron_ram_wrapper> compiled.
Entity <micron_ram_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <micron_ram_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <xps_mch_emc> in library <xps_mch_emc_v3_01_a> (architecture <implementation>) with generics.
	C_FAMILY = "spartan3e"
	C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_1 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_2 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_3 = 0
	C_INCLUDE_NEGEDGE_IOREGS = 0
	C_INCLUDE_PLB_IPIF = 1
	C_INCLUDE_WRBUF = 1
	C_MAX_MEM_WIDTH = 16
	C_MCH0_ACCESSBUF_DEPTH = 16
	C_MCH0_PROTOCOL = 0
	C_MCH0_RDDATABUF_DEPTH = 16
	C_MCH1_ACCESSBUF_DEPTH = 16
	C_MCH1_PROTOCOL = 0
	C_MCH1_RDDATABUF_DEPTH = 16
	C_MCH2_ACCESSBUF_DEPTH = 16
	C_MCH2_PROTOCOL = 0
	C_MCH2_RDDATABUF_DEPTH = 16
	C_MCH3_ACCESSBUF_DEPTH = 16
	C_MCH3_PROTOCOL = 0
	C_MCH3_RDDATABUF_DEPTH = 16
	C_MCH_NATIVE_DWIDTH = 32
	C_MCH_SPLB_AWIDTH = 32
	C_MCH_SPLB_CLK_PERIOD_PS = 20000
	C_MEM0_BASEADDR = "10000010000000000000000000000000"
	C_MEM0_HIGHADDR = "10000010111111111111111111111111"
	C_MEM0_WIDTH = 16
	C_MEM1_BASEADDR = "11111111111111111111111111111111"
	C_MEM1_HIGHADDR = "00000000000000000000000000000000"
	C_MEM1_WIDTH = 32
	C_MEM2_BASEADDR = "11111111111111111111111111111111"
	C_MEM2_HIGHADDR = "00000000000000000000000000000000"
	C_MEM2_WIDTH = 32
	C_MEM3_BASEADDR = "11111111111111111111111111111111"
	C_MEM3_HIGHADDR = "00000000000000000000000000000000"
	C_MEM3_WIDTH = 32
	C_NUM_BANKS_MEM = 1
	C_NUM_CHANNELS = 0
	C_PAGEMODE_FLASH_0 = 0
	C_PAGEMODE_FLASH_1 = 0
	C_PAGEMODE_FLASH_2 = 0
	C_PAGEMODE_FLASH_3 = 0
	C_PRIORITY_MODE = 0
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SMALLEST_MASTER = 32
	C_SYNCH_MEM_0 = 0
	C_SYNCH_MEM_1 = 0
	C_SYNCH_MEM_2 = 0
	C_SYNCH_MEM_3 = 0
	C_SYNCH_PIPEDELAY_0 = 2
	C_SYNCH_PIPEDELAY_1 = 2
	C_SYNCH_PIPEDELAY_2 = 2
	C_SYNCH_PIPEDELAY_3 = 2
	C_TAVDV_PS_MEM_0 = 85000
	C_TAVDV_PS_MEM_1 = 15000
	C_TAVDV_PS_MEM_2 = 15000
	C_TAVDV_PS_MEM_3 = 15000
	C_TCEDV_PS_MEM_0 = 85000
	C_TCEDV_PS_MEM_1 = 15000
	C_TCEDV_PS_MEM_2 = 15000
	C_TCEDV_PS_MEM_3 = 15000
	C_THZCE_PS_MEM_0 = 8000
	C_THZCE_PS_MEM_1 = 7000
	C_THZCE_PS_MEM_2 = 7000
	C_THZCE_PS_MEM_3 = 7000
	C_THZOE_PS_MEM_0 = 8000
	C_THZOE_PS_MEM_1 = 7000
	C_THZOE_PS_MEM_2 = 7000
	C_THZOE_PS_MEM_3 = 7000
	C_TLZWE_PS_MEM_0 = 5000
	C_TLZWE_PS_MEM_1 = 0
	C_TLZWE_PS_MEM_2 = 0
	C_TLZWE_PS_MEM_3 = 0
	C_TPACC_PS_FLASH_0 = 25000
	C_TPACC_PS_FLASH_1 = 25000
	C_TPACC_PS_FLASH_2 = 25000
	C_TPACC_PS_FLASH_3 = 25000
	C_TWC_PS_MEM_0 = 85000
	C_TWC_PS_MEM_1 = 15000
	C_TWC_PS_MEM_2 = 15000
	C_TWC_PS_MEM_3 = 15000
	C_TWP_PS_MEM_0 = 55000
	C_TWP_PS_MEM_1 = 12000
	C_TWP_PS_MEM_2 = 12000
	C_TWP_PS_MEM_3 = 12000
	C_XCL0_LINESIZE = 4
	C_XCL0_WRITEXFER = 1
	C_XCL1_LINESIZE = 4
	C_XCL1_WRITEXFER = 1
	C_XCL2_LINESIZE = 4
	C_XCL2_WRITEXFER = 1
	C_XCL3_LINESIZE = 4
	C_XCL3_WRITEXFER = 1
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_access_control> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_access_data> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_access_write> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_access_full> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_readdata_control> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_readdata_data> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_readdata_read> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_readdata_exists> is not supported.

Analyzing hierarchy for entity <mch_plbv46_slave_burst> in library <mch_plbv46_slave_burst_v2_01_a> (architecture <imp>) with generics.
	C_CACHLINE_ADDR_MODE = 0
	C_DAG_ADDR_STEP_ARRAY = (4,4)
	C_DAG_ADDR_WRAP_ARRAY = ("0000000000000000000000000000000000000000000000001111111111111111",
	                         "0000000000000000000000000000000000000000000000001111111111111111")
	C_DAG_BURSTSIZE_ARRAY = (16,16)
	C_FAMILY = "spartan3e"
	C_INCLUDE_PLB_IPIF = 1
	C_MCH_ACCESSBUF_DEPTH_ARRAY = (16,16,16,16)
	C_MCH_PROTOCOL_ARRAY = (0,0,0,0)
	C_MCH_RDDATABUF_DEPTH_ARRAY = (16,16,16,16)
	C_MCH_SIPIF_DWIDTH = 32
	C_MCH_SPLB_AWIDTH = 32
	C_MCH_USERIP_ADDRRANGE_ARRAY = ("0000000000000000000000000000000010000010000000000000000000000000",
	                                "0000000000000000000000000000000010000010111111111111111111111111")
	C_NUM_CHANNELS = 0
	C_PLB_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000010000000000000000000000000",
	                              "0000000000000000000000000000000010000010111111111111111111111111")
	C_PLB_ARD_NUM_CE_ARRAY = (1)
	C_PRIORITY_MODE = 0
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SMALLEST_MASTER = 32
	C_WR_BUFFER_DEPTH = 16
	C_XCL_LINESIZE_ARRAY = (4,4,4,4)
	C_XCL_WRITEXFER_ARRAY = (1,1,1,1)

Analyzing hierarchy for entity <EMC> in library <emc_common_v4_01_a> (architecture <IMP>) with generics.
	C_BUS_CLOCK_PERIOD_PS = 20000
	C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_1 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_2 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_3 = 0
	C_INCLUDE_NEGEDGE_IOREGS = 0
	C_IPIF_AWIDTH = 32
	C_IPIF_DWIDTH = 32
	C_MAX_MEM_WIDTH = 16
	C_MEM0_BASEADDR = "10000010000000000000000000000000"
	C_MEM0_HIGHADDR = "10000010111111111111111111111111"
	C_MEM0_WIDTH = 16
	C_MEM1_BASEADDR = "11111111111111111111111111111111"
	C_MEM1_HIGHADDR = "00000000000000000000000000000000"
	C_MEM1_WIDTH = 32
	C_MEM2_BASEADDR = "11111111111111111111111111111111"
	C_MEM2_HIGHADDR = "00000000000000000000000000000000"
	C_MEM2_WIDTH = 32
	C_MEM3_BASEADDR = "11111111111111111111111111111111"
	C_MEM3_HIGHADDR = "00000000000000000000000000000000"
	C_MEM3_WIDTH = 32
	C_NUM_BANKS_MEM = 1
	C_PAGEMODE_FLASH_0 = 0
	C_PAGEMODE_FLASH_1 = 0
	C_PAGEMODE_FLASH_2 = 0
	C_PAGEMODE_FLASH_3 = 0
	C_SPLB_DWIDTH = 32
	C_SYNCH_MEM_0 = 0
	C_SYNCH_MEM_1 = 0
	C_SYNCH_MEM_2 = 0
	C_SYNCH_MEM_3 = 0
	C_SYNCH_PIPEDELAY_0 = 2
	C_SYNCH_PIPEDELAY_1 = 2
	C_SYNCH_PIPEDELAY_2 = 2
	C_SYNCH_PIPEDELAY_3 = 2
	C_TAVDV_PS_MEM_0 = 85000
	C_TAVDV_PS_MEM_1 = 15000
	C_TAVDV_PS_MEM_2 = 15000
	C_TAVDV_PS_MEM_3 = 15000
	C_TCEDV_PS_MEM_0 = 85000
	C_TCEDV_PS_MEM_1 = 15000
	C_TCEDV_PS_MEM_2 = 15000
	C_TCEDV_PS_MEM_3 = 15000
	C_THZCE_PS_MEM_0 = 8000
	C_THZCE_PS_MEM_1 = 7000
	C_THZCE_PS_MEM_2 = 7000
	C_THZCE_PS_MEM_3 = 7000
	C_THZOE_PS_MEM_0 = 8000
	C_THZOE_PS_MEM_1 = 7000
	C_THZOE_PS_MEM_2 = 7000
	C_THZOE_PS_MEM_3 = 7000
	C_TLZWE_PS_MEM_0 = 5000
	C_TLZWE_PS_MEM_1 = 0
	C_TLZWE_PS_MEM_2 = 0
	C_TLZWE_PS_MEM_3 = 0
	C_TPACC_PS_FLASH_0 = 25000
	C_TPACC_PS_FLASH_1 = 25000
	C_TPACC_PS_FLASH_2 = 25000
	C_TPACC_PS_FLASH_3 = 25000
	C_TWC_PS_MEM_0 = 85000
	C_TWC_PS_MEM_1 = 15000
	C_TWC_PS_MEM_2 = 15000
	C_TWC_PS_MEM_3 = 15000
	C_TWP_PS_MEM_0 = 55000
	C_TWP_PS_MEM_1 = 12000
	C_TWP_PS_MEM_2 = 12000
	C_TWP_PS_MEM_3 = 12000

Analyzing hierarchy for entity <plbv46_slave_burst> in library <plbv46_slave_burst_v1_01_a> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000010000000000000000000000000",
	                          "0000000000000000000000000000000010000010111111111111111111111111")
	C_ARD_NUM_CE_ARRAY = (1)
	C_BURSTLENGTH_TYPE = 1
	C_CACHLINE_ADDR_MODE = 0
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 0
	C_SIPIF_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SMALLEST_MASTER = 32
	C_WR_BUFFER_DEPTH = 16

Analyzing hierarchy for entity <ipic_if> in library <emc_common_v4_01_a> (architecture <imp>) with generics.
	C_IPIF_DWIDTH = 32
	C_NUM_BANKS_MEM = 1
	C_SPLB_DWIDTH = 32

Analyzing hierarchy for entity <mem_state_machine> in library <emc_common_v4_01_a> (architecture <imp>).

Analyzing hierarchy for entity <addr_counter_mux> in library <emc_common_v4_01_a> (architecture <imp>) with generics.
	C_ADDR_CNTR_WIDTH = 2
	C_ADDR_OFFSET = 2
	C_GLOBAL_DATAWIDTH_MATCH = 1
	C_IPIF_AWIDTH = 32
	C_IPIF_DWIDTH = 32

Analyzing hierarchy for entity <counters> in library <emc_common_v4_01_a> (architecture <imp>).

Analyzing hierarchy for entity <select_param> in library <emc_common_v4_01_a> (architecture <IMP>) with generics.
	C_GLOBAL_DATAWIDTH_MATCH = 1
	C_GLOBAL_SYNC_MEM = 0
	C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_1 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_2 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_3 = 0
	C_IPIF_AWIDTH = 32
	C_IPIF_DWIDTH = 32
	C_MEM0_WIDTH = 16
	C_MEM1_WIDTH = 32
	C_MEM2_WIDTH = 32
	C_MEM3_WIDTH = 32
	C_NUM_BANKS_MEM = 1
	C_PAGEMODE_FLASH = 0
	C_PAGEMODE_FLASH_0 = 0
	C_PAGEMODE_FLASH_1 = 0
	C_PAGEMODE_FLASH_2 = 0
	C_PAGEMODE_FLASH_3 = 0
	C_SYNCH_MEM_0 = 0
	C_SYNCH_MEM_1 = 0
	C_SYNCH_MEM_2 = 0
	C_SYNCH_MEM_3 = 0
	C_SYNCH_PIPEDELAY_0 = 2
	C_SYNCH_PIPEDELAY_1 = 2
	C_SYNCH_PIPEDELAY_2 = 2
	C_SYNCH_PIPEDELAY_3 = 2
	THZCNT_0 = "00001"
	THZCNT_1 = "00001"
	THZCNT_2 = "00001"
	THZCNT_3 = "00001"
	TLZCNT_0 = "00001"
	TLZCNT_1 = "00001"
	TLZCNT_2 = "00001"
	TLZCNT_3 = "00001"
	TPACC_0 = "00010"
	TPACC_1 = "00010"
	TPACC_2 = "00010"
	TPACC_3 = "00010"
	TRDCNT_0 = "00101"
	TRDCNT_1 = "00001"
	TRDCNT_2 = "00001"
	TRDCNT_3 = "00001"
	TWRCNT_0 = "00101"
	TWRCNT_1 = "00001"
	TWRCNT_2 = "00001"
	TWRCNT_3 = "00001"

Analyzing hierarchy for entity <mem_steer> in library <emc_common_v4_01_a> (architecture <imp>) with generics.
	C_ADDR_CNTR_WIDTH = 2
	C_GLOBAL_DATAWIDTH_MATCH = 1
	C_GLOBAL_SYNC_MEM = 0
	C_IPIF_DWIDTH = 32
	C_MAX_MEM_WIDTH = 16
	C_MIN_MEM_WIDTH = 8
	C_NUM_BANKS_MEM = 1

Analyzing hierarchy for entity <io_registers> in library <emc_common_v4_01_a> (architecture <imp>) with generics.
	C_INCLUDE_NEGEDGE_IOREGS = 0
	C_IPIF_AWIDTH = 32
	C_MAX_MEM_WIDTH = 16
	C_NUM_BANKS_MEM = 1

Analyzing hierarchy for entity <plb_slave_attachment> in library <plbv46_slave_burst_v1_01_a> (architecture <implementation>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000010000000000000000000000000",
	                          "0000000000000000000000000000000010000010111111111111111111111111")
	C_ARD_NUM_CE_ARRAY = (1)
	C_BURSTLENGTH_TYPE = 1
	C_CACHLINE_ADDR_MODE = 0
	C_DEV_MAX_BURST_SIZE = 64
	C_DPHASE_TIMEOUT = 128
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 0
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_PLB_SMALLEST_MASTER = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_P2P = 0
	C_STEER_ADDR_SIZE = 10
	C_WR_BUFFER_DEPTH = 16

Analyzing hierarchy for entity <data_mirror_128> in library <plbv46_slave_burst_v1_01_a> (architecture <implementation>) with generics.
	C_IPIF_DWIDTH = 32
	C_PLB_AWIDTH = 10
	C_PLB_DWIDTH = 32
	C_SMALLEST = 32

Analyzing hierarchy for entity <ld_arith_reg> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_ADD_SUB_NOT = false
	C_AD_OFFSET = 0
	C_AD_WIDTH = 1
	C_LD_OFFSET = 0
	C_LD_WIDTH = 7
	C_REG_WIDTH = 7
	C_RESET_VALUE = "0000000"

Analyzing hierarchy for entity <ld_arith_reg> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_ADD_SUB_NOT = false
	C_AD_OFFSET = 0
	C_AD_WIDTH = 1
	C_LD_OFFSET = 0
	C_LD_WIDTH = 2
	C_REG_WIDTH = 2
	C_RESET_VALUE = "00"

Analyzing hierarchy for entity <ld_arith_reg> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_ADD_SUB_NOT = false
	C_AD_OFFSET = 0
	C_AD_WIDTH = 1
	C_LD_OFFSET = 0
	C_LD_WIDTH = 5
	C_REG_WIDTH = 5
	C_RESET_VALUE = "11111"

Analyzing hierarchy for entity <ld_arith_reg> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_ADD_SUB_NOT = false
	C_AD_OFFSET = 0
	C_AD_WIDTH = 1
	C_LD_OFFSET = 0
	C_LD_WIDTH = 5
	C_REG_WIDTH = 5
	C_RESET_VALUE = "00000"

Analyzing hierarchy for entity <be_reset_gen> in library <plbv46_slave_burst_v1_01_a> (architecture <implementation>) with generics.
	C_AWIDTH = 32
	C_DWIDTH = 32
	C_SMALLEST = 32

Analyzing hierarchy for entity <plb_address_decoder> in library <plbv46_slave_burst_v1_01_a> (architecture <IMP>) with generics.
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000010000000000000000000000000",
	                          "0000000000000000000000000000000010000010111111111111111111111111")
	C_ARD_NUM_CE_ARRAY = (1)
	C_BUS_AWIDTH = 32
	C_FAMILY = "nofamily"
	C_SIPIF_DWIDTH = 32
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <wr_buffer> in library <plbv46_slave_burst_v1_01_a> (architecture <imp>) with generics.
	C_AWIDTH = 4
	C_DEPTH = 16
	C_DWIDTH = 32
	C_FAMILY = "spartan3e"

Analyzing hierarchy for entity <burst_support> in library <plbv46_slave_burst_v1_01_a> (architecture <implementation>) with generics.
	C_FAMILY = "spartan3e"
	C_MAX_DBEAT_CNT = 16

Analyzing hierarchy for entity <addr_reg_cntr_brst_flex> in library <plbv46_slave_burst_v1_01_a> (architecture <implementation>) with generics.
	C_CACHLINE_ADDR_MODE = 0
	C_NUM_ADDR_BITS = 32
	C_PLB_DWIDTH = 32
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <addr_reg_cntr_brst_flex> in library <plbv46_slave_burst_v1_01_a> (architecture <implementation>) with generics.
	C_CACHLINE_ADDR_MODE = 0
	C_NUM_ADDR_BITS = 10
	C_PLB_DWIDTH = 32
	C_SPLB_P2P = 0

Analyzing hierarchy for entity <pselect_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_AB = 8
	C_AW = 32
	C_BAR = "10000010000000000000000000000000"
	C_FAMILY = "nofamily"

Analyzing hierarchy for entity <or_gate128> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 1
	C_USE_LUT_OR = true

Analyzing hierarchy for entity <counter_f> in library <proc_common_v3_00_a> (architecture <imp>) with generics.
	C_FAMILY = "spartan3e"
	C_NUM_BITS = 5

Analyzing hierarchy for entity <flex_addr_cntr> in library <plbv46_slave_burst_v1_01_a> (architecture <implementation>) with generics.
	C_AWIDTH = 32
	C_DWIDTH = 32

Analyzing hierarchy for entity <flex_addr_cntr> in library <plbv46_slave_burst_v1_01_a> (architecture <implementation>) with generics.
	C_AWIDTH = 10
	C_DWIDTH = 32


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <micron_ram_wrapper> in library <work> (Architecture <STRUCTURE>).
    Set property "MAX_FANOUT = 10000" for signal <MCH_SPLB_Clk> in unit <xps_mch_emc>.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
    Set property "MAX_FANOUT = 10000" for signal <MCH_SPLB_Rst> in unit <xps_mch_emc>.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
    Set user-defined property "IOB =  true" for signal <Mem_DQ_I> in unit <xps_mch_emc>.
    Set user-defined property "IOB =  true" for signal <Mem_DQ_O> in unit <xps_mch_emc>.
    Set property "EQUIVALENT_REGISTER_REMOVAL = no" for signal <Mem_DQ_T> in unit <xps_mch_emc>.
    Set user-defined property "IOB =  true" for signal <Mem_DQ_T> in unit <xps_mch_emc>.
Entity <micron_ram_wrapper> analyzed. Unit <micron_ram_wrapper> generated.

Analyzing generic Entity <xps_mch_emc> in library <xps_mch_emc_v3_01_a> (Architecture <implementation>).
	C_FAMILY = "spartan3e"
	C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_1 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_2 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_3 = 0
	C_INCLUDE_NEGEDGE_IOREGS = 0
	C_INCLUDE_PLB_IPIF = 1
	C_INCLUDE_WRBUF = 1
	C_MAX_MEM_WIDTH = 16
	C_MCH0_ACCESSBUF_DEPTH = 16
	C_MCH0_PROTOCOL = 0
	C_MCH0_RDDATABUF_DEPTH = 16
	C_MCH1_ACCESSBUF_DEPTH = 16
	C_MCH1_PROTOCOL = 0
	C_MCH1_RDDATABUF_DEPTH = 16
	C_MCH2_ACCESSBUF_DEPTH = 16
	C_MCH2_PROTOCOL = 0
	C_MCH2_RDDATABUF_DEPTH = 16
	C_MCH3_ACCESSBUF_DEPTH = 16
	C_MCH3_PROTOCOL = 0
	C_MCH3_RDDATABUF_DEPTH = 16
	C_MCH_NATIVE_DWIDTH = 32
	C_MCH_SPLB_AWIDTH = 32
	C_MCH_SPLB_CLK_PERIOD_PS = 20000
	C_MEM0_BASEADDR = "10000010000000000000000000000000"
	C_MEM0_HIGHADDR = "10000010111111111111111111111111"
	C_MEM0_WIDTH = 16
	C_MEM1_BASEADDR = "11111111111111111111111111111111"
	C_MEM1_HIGHADDR = "00000000000000000000000000000000"
	C_MEM1_WIDTH = 32
	C_MEM2_BASEADDR = "11111111111111111111111111111111"
	C_MEM2_HIGHADDR = "00000000000000000000000000000000"
	C_MEM2_WIDTH = 32
	C_MEM3_BASEADDR = "11111111111111111111111111111111"
	C_MEM3_HIGHADDR = "00000000000000000000000000000000"
	C_MEM3_WIDTH = 32
	C_NUM_BANKS_MEM = 1
	C_NUM_CHANNELS = 0
	C_PAGEMODE_FLASH_0 = 0
	C_PAGEMODE_FLASH_1 = 0
	C_PAGEMODE_FLASH_2 = 0
	C_PAGEMODE_FLASH_3 = 0
	C_PRIORITY_MODE = 0
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SMALLEST_MASTER = 32
	C_SYNCH_MEM_0 = 0
	C_SYNCH_MEM_1 = 0
	C_SYNCH_MEM_2 = 0
	C_SYNCH_MEM_3 = 0
	C_SYNCH_PIPEDELAY_0 = 2
	C_SYNCH_PIPEDELAY_1 = 2
	C_SYNCH_PIPEDELAY_2 = 2
	C_SYNCH_PIPEDELAY_3 = 2
	C_TAVDV_PS_MEM_0 = 85000
	C_TAVDV_PS_MEM_1 = 15000
	C_TAVDV_PS_MEM_2 = 15000
	C_TAVDV_PS_MEM_3 = 15000
	C_TCEDV_PS_MEM_0 = 85000
	C_TCEDV_PS_MEM_1 = 15000
	C_TCEDV_PS_MEM_2 = 15000
	C_TCEDV_PS_MEM_3 = 15000
	C_THZCE_PS_MEM_0 = 8000
	C_THZCE_PS_MEM_1 = 7000
	C_THZCE_PS_MEM_2 = 7000
	C_THZCE_PS_MEM_3 = 7000
	C_THZOE_PS_MEM_0 = 8000
	C_THZOE_PS_MEM_1 = 7000
	C_THZOE_PS_MEM_2 = 7000
	C_THZOE_PS_MEM_3 = 7000
	C_TLZWE_PS_MEM_0 = 5000
	C_TLZWE_PS_MEM_1 = 0
	C_TLZWE_PS_MEM_2 = 0
	C_TLZWE_PS_MEM_3 = 0
	C_TPACC_PS_FLASH_0 = 25000
	C_TPACC_PS_FLASH_1 = 25000
	C_TPACC_PS_FLASH_2 = 25000
	C_TPACC_PS_FLASH_3 = 25000
	C_TWC_PS_MEM_0 = 85000
	C_TWC_PS_MEM_1 = 15000
	C_TWC_PS_MEM_2 = 15000
	C_TWC_PS_MEM_3 = 15000
	C_TWP_PS_MEM_0 = 55000
	C_TWP_PS_MEM_1 = 12000
	C_TWP_PS_MEM_2 = 12000
	C_TWP_PS_MEM_3 = 12000
	C_XCL0_LINESIZE = 4
	C_XCL0_WRITEXFER = 1
	C_XCL1_LINESIZE = 4
	C_XCL1_WRITEXFER = 1
	C_XCL2_LINESIZE = 4
	C_XCL2_WRITEXFER = 1
	C_XCL3_LINESIZE = 4
	C_XCL3_WRITEXFER = 1
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "SIGIS". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_access_control> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_access_data> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_access_write> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_access_full> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_readdata_control> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_readdata_data> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_readdata_read> is not supported.
WARNING:Xst:2096 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Use of null array slice on signal <mch_readdata_exists> is not supported.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Unconnected output port 'Bus2IP_Clk' of component 'mch_plbv46_slave_burst'.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Unconnected output port 'Bus2IP_Reset' of component 'mch_plbv46_slave_burst'.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Unconnected output port 'Bus2IP_BurstLength' of component 'mch_plbv46_slave_burst'.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Unconnected output port 'Bus2IP_AddrBurstCntLoad' of component 'mch_plbv46_slave_burst'.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Unconnected output port 'Bus2IP_WrReq' of component 'mch_plbv46_slave_burst'.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 912: Unconnected output port 'Bus2IP_RdReq' of component 'mch_plbv46_slave_burst'.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 402: Null range in type of signal <MCH_Access_Control>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 403: Null range in type of signal <MCH_Access_Data>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 405: Null range in type of signal <MCH_Access_Write>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 406: Null range in type of signal <MCH_Access_Full>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 408: Null range in type of signal <MCH_ReadData_Control>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 409: Null range in type of signal <MCH_ReadData_Data>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 411: Null range in type of signal <MCH_ReadData_Read>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 412: Null range in type of signal <MCH_ReadData_Exists>.
    Set property "REGISTER_DUPLICATION = yes" for signal <Bus2IP_Addr> in unit <mch_plbv46_slave_burst>.
    Set property "REGISTER_DUPLICATION = yes" for signal <Bus2IP_Burst> in unit <mch_plbv46_slave_burst>.
    Set property "REGISTER_DUPLICATION = yes" for signal <Bus2IP_WrReq> in unit <mch_plbv46_slave_burst>.
    Set property "REGISTER_DUPLICATION = yes" for signal <Bus2IP_RdReq> in unit <mch_plbv46_slave_burst>.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 1039: Unconnected output port 'IP2Bus_retry' of component 'EMC'.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd" line 1039: Unconnected output port 'IP2Bus_toutSup' of component 'EMC'.
Entity <xps_mch_emc> analyzed. Unit <xps_mch_emc> generated.

Analyzing generic Entity <mch_plbv46_slave_burst> in library <mch_plbv46_slave_burst_v2_01_a> (Architecture <imp>).
	C_CACHLINE_ADDR_MODE = 0
	C_DAG_ADDR_STEP_ARRAY = (4,4)
	C_DAG_ADDR_WRAP_ARRAY = ("0000000000000000000000000000000000000000000000001111111111111111",
	                         "0000000000000000000000000000000000000000000000001111111111111111")
	C_DAG_BURSTSIZE_ARRAY = (16,16)
	C_FAMILY = "spartan3e"
	C_INCLUDE_PLB_IPIF = 1
	C_MCH_ACCESSBUF_DEPTH_ARRAY = (16,16,16,16)
	C_MCH_PROTOCOL_ARRAY = (0,0,0,0)
	C_MCH_RDDATABUF_DEPTH_ARRAY = (16,16,16,16)
	C_MCH_SIPIF_DWIDTH = 32
	C_MCH_SPLB_AWIDTH = 32
	C_MCH_USERIP_ADDRRANGE_ARRAY = ("0000000000000000000000000000000010000010000000000000000000000000",
	                                "0000000000000000000000000000000010000010111111111111111111111111")
	C_NUM_CHANNELS = 0
	C_PLB_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000010000000000000000000000000",
	                              "0000000000000000000000000000000010000010111111111111111111111111")
	C_PLB_ARD_NUM_CE_ARRAY = (1)
	C_PRIORITY_MODE = 0
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SMALLEST_MASTER = 32
	C_WR_BUFFER_DEPTH = 16
	C_XCL_LINESIZE_ARRAY = (4,4,4,4)
	C_XCL_WRITEXFER_ARRAY = (1,1,1,1)
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 402: Null range in type of signal <MCH_Access_Control>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 403: Null range in type of signal <MCH_Access_Data>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 405: Null range in type of signal <MCH_Access_Write>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 406: Null range in type of signal <MCH_Access_Full>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 408: Null range in type of signal <MCH_ReadData_Control>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 409: Null range in type of signal <MCH_ReadData_Data>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 411: Null range in type of signal <MCH_ReadData_Read>.
WARNING:Xst:1994 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 412: Null range in type of signal <MCH_ReadData_Exists>.
WARNING:Xst:1995 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 702: Use of null array on signal <MCH_Access_Full> is not supported.
WARNING:Xst:1995 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 703: Use of null array on signal <MCH_ReadData_Control> is not supported.
WARNING:Xst:1995 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 704: Use of null array on signal <MCH_ReadData_Data> is not supported.
WARNING:Xst:1995 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd" line 705: Use of null array on signal <MCH_ReadData_Exists> is not supported.
Entity <mch_plbv46_slave_burst> analyzed. Unit <mch_plbv46_slave_burst> generated.

Analyzing generic Entity <plbv46_slave_burst> in library <plbv46_slave_burst_v1_01_a> (Architecture <implementation>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000010000000000000000000000000",
	                          "0000000000000000000000000000000010000010111111111111111111111111")
	C_ARD_NUM_CE_ARRAY = (1)
	C_BURSTLENGTH_TYPE = 1
	C_CACHLINE_ADDR_MODE = 0
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 0
	C_SIPIF_DWIDTH = 32
	C_SPLB_AWIDTH = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_MID_WIDTH = 1
	C_SPLB_NUM_MASTERS = 2
	C_SPLB_P2P = 0
	C_SPLB_SMALLEST_MASTER = 32
	C_WR_BUFFER_DEPTH = 16
Entity <plbv46_slave_burst> analyzed. Unit <plbv46_slave_burst> generated.

Analyzing generic Entity <plb_slave_attachment> in library <plbv46_slave_burst_v1_01_a> (Architecture <implementation>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000010000000000000000000000000",
	                          "0000000000000000000000000000000010000010111111111111111111111111")
	C_ARD_NUM_CE_ARRAY = (1)
	C_BURSTLENGTH_TYPE = 1
	C_CACHLINE_ADDR_MODE = 0
	C_DEV_MAX_BURST_SIZE = 64
	C_DPHASE_TIMEOUT = 128
	C_FAMILY = "spartan3e"
	C_INCLUDE_DPHASE_TIMER = 0
	C_IPIF_ABUS_WIDTH = 32
	C_IPIF_DBUS_WIDTH = 32
	C_PLB_MID_WIDTH = 1
	C_PLB_NUM_MASTERS = 2
	C_PLB_SMALLEST_MASTER = 32
	C_SPLB_DWIDTH = 32
	C_SPLB_P2P = 0
	C_STEER_ADDR_SIZE = 10
	C_WR_BUFFER_DEPTH = 16
    Set user-defined property "INIT =  0" for instance <I_RDREQ_FDRSE> in unit <plb_slave_attachment>.
    Set user-defined property "INIT =  0" for instance <GEN_WRITE_BUFFER.GEN_WRBUF_WREN1> in unit <plb_slave_attachment>.
    Set user-defined property "INIT =  0" for instance <GEN_WRITE_BUFFER.GEN_WRBUF_WREN2> in unit <plb_slave_attachment>.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" line 2040: Unconnected output port 'Data_Exists' of component 'wr_buffer'.
    Set user-defined property "INIT =  0" for instance <I_WRREQ_FDRSE> in unit <plb_slave_attachment>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_32.DPHASE_REG1> in unit <plb_slave_attachment>.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" line 3380: Unconnected output port 'BE_out' of component 'addr_reg_cntr_brst_flex'.
INFO:Xst:2679 - Register <Sl_SSize> in unit <plb_slave_attachment> has a constant value of 00 during circuit operation. The register is replaced by logic.
Entity <plb_slave_attachment> analyzed. Unit <plb_slave_attachment> generated.

Analyzing generic Entity <be_reset_gen> in library <plbv46_slave_burst_v1_01_a> (Architecture <implementation>).
	C_AWIDTH = 32
	C_DWIDTH = 32
	C_SMALLEST = 32
Entity <be_reset_gen> analyzed. Unit <be_reset_gen> generated.

Analyzing generic Entity <plb_address_decoder> in library <plbv46_slave_burst_v1_01_a> (Architecture <IMP>).
	C_ARD_ADDR_RANGE_ARRAY = ("0000000000000000000000000000000010000010000000000000000000000000",
	                          "0000000000000000000000000000000010000010111111111111111111111111")
	C_ARD_NUM_CE_ARRAY = (1)
	C_BUS_AWIDTH = 32
	C_FAMILY = "nofamily"
	C_SIPIF_DWIDTH = 32
	C_SPLB_P2P = 0
    Set user-defined property "INIT =  0" for instance <I_RNW_S_H_REG> in unit <plb_address_decoder>.
    Set user-defined property "INIT =  0" for instance <MEM_DECODE_GEN[0].GEN_PLB_SHARED.I_CS_S_H_REG> in unit <plb_address_decoder>.
    Set user-defined property "INIT =  0" for instance <MEM_DECODE_GEN[0].GEN_PLB_SHARED.I_BKEND_CS_REG> in unit <plb_address_decoder>.
    Set user-defined property "INIT =  0" for instance <I_ADDR_MATCH_REG> in unit <plb_address_decoder>.
    Set user-defined property "INIT =  0" for instance <GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_RDCE_REG> in unit <plb_address_decoder>.
    Set user-defined property "INIT =  0" for instance <GEN_CE_FOR_SHARED.GEN_BKEND_CE_REGISTERS[0].I_BKEND_WRCE_REG> in unit <plb_address_decoder>.
Entity <plb_address_decoder> analyzed. Unit <plb_address_decoder> generated.

Analyzing generic Entity <pselect_f> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_AB = 8
	C_AW = 32
	C_BAR = "10000010000000000000000000000000"
	C_FAMILY = "nofamily"
Entity <pselect_f> analyzed. Unit <pselect_f> generated.

Analyzing generic Entity <or_gate128> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_BUS_WIDTH = 1
	C_OR_WIDTH = 1
	C_USE_LUT_OR = true
Entity <or_gate128> analyzed. Unit <or_gate128> generated.

Analyzing generic Entity <wr_buffer> in library <plbv46_slave_burst_v1_01_a> (Architecture <imp>).
	C_AWIDTH = 4
	C_DEPTH = 16
	C_DWIDTH = 32
	C_FAMILY = "spartan3e"
    Set user-defined property "INIT =  0" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.DATA_EXISTS_DFF> in unit <wr_buffer>.
    Set user-defined property "INIT =  0" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.Addr_Counters[0].FDRE_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.Addr_Counters[1].FDRE_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.Addr_Counters[2].FDRE_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.Addr_Counters[3].FDRE_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[0].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[1].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[2].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[3].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[4].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[5].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[6].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[7].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[8].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[9].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[10].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[11].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[12].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[13].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[14].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM[15].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[16].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[17].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[18].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[19].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[20].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[21].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[22].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[23].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[24].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[25].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[26].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[27].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[28].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[29].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[30].SRL16E_I> in unit <wr_buffer>.
    Set user-defined property "INIT =  0000" for instance <GEN_STRUCTURAL.C_DEPTH_LT_17.FIFO_RAM2[31].SRL16E_I> in unit <wr_buffer>.
Entity <wr_buffer> analyzed. Unit <wr_buffer> generated.

Analyzing generic Entity <burst_support> in library <plbv46_slave_burst_v1_01_a> (Architecture <implementation>).
	C_FAMILY = "spartan3e"
	C_MAX_DBEAT_CNT = 16
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd" line 260: Unconnected output port 'Carry_Out' of component 'counter_f'.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd" line 323: Unconnected output port 'Carry_Out' of component 'counter_f'.
Entity <burst_support> analyzed. Unit <burst_support> generated.

Analyzing generic Entity <counter_f> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_FAMILY = "spartan3e"
	C_NUM_BITS = 5
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 214: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 237: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 244: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 250: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 237: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 244: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 250: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 237: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 244: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 250: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 237: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 244: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 250: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 237: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 244: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 250: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 237: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 244: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" line 250: Instantiating black box module <FDRE>.
Entity <counter_f> analyzed. Unit <counter_f> generated.

Analyzing generic Entity <addr_reg_cntr_brst_flex.1> in library <plbv46_slave_burst_v1_01_a> (Architecture <implementation>).
	C_CACHLINE_ADDR_MODE = 0
	C_NUM_ADDR_BITS = 32
	C_PLB_DWIDTH = 32
	C_SPLB_P2P = 0
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.I_SNGL_S_H_REG> in unit <addr_reg_cntr_brst_flex.1>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.I_CACHLN_S_H_REG> in unit <addr_reg_cntr_brst_flex.1>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.I_BURST_S_H_REG> in unit <addr_reg_cntr_brst_flex.1>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG> in unit <addr_reg_cntr_brst_flex.1>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG> in unit <addr_reg_cntr_brst_flex.1>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG> in unit <addr_reg_cntr_brst_flex.1>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG> in unit <addr_reg_cntr_brst_flex.1>.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" line 628: Unconnected output port 'Carry_Out' of component 'flex_addr_cntr'.
Entity <addr_reg_cntr_brst_flex.1> analyzed. Unit <addr_reg_cntr_brst_flex.1> generated.

Analyzing generic Entity <flex_addr_cntr.1> in library <plbv46_slave_burst_v1_01_a> (Architecture <implementation>).
	C_AWIDTH = 32
	C_DWIDTH = 32
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[7].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[7].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[8].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[8].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[9].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[9].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[10].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[10].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[11].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[11].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[12].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[12].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[13].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[13].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[14].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[14].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[15].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[15].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[16].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[16].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[17].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[17].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[18].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[18].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[19].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[19].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[20].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[20].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[21].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[21].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[22].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[22].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[23].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[23].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[24].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[24].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[25].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[25].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[26].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[26].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[27].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[27].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[28].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[28].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[29].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[29].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[30].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[30].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[31].I_LUT_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[31].I_FDRE_N> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <I_LUT6> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <I_FDRE6> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <I_LUT5> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <I_FDRE5> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <I_LUT4> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <I_FDRE4> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <I_LUT3> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_FOR_32_64.I_FDRE3> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <I_LUT2> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_FOR_32.I_FDRE2> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <I_LUT1> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <I_FDRE1> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F202" for instance <I_LUT0> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <I_FDRE0> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  FF31" for instance <I_BE_GEN_LUT0> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  FF32" for instance <I_BE_GEN_LUT1> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  FFC4" for instance <I_BE_GEN_LUT2> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  FFC8" for instance <I_BE_GEN_LUT4> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F088" for instance <LDMUX_FDRSE_0to3[0].I_BE_LDMUX_0to3> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F088" for instance <LDMUX_FDRSE_0to3[1].I_BE_LDMUX_0to3> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F088" for instance <LDMUX_FDRSE_0to3[2].I_BE_LDMUX_0to3> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  F088" for instance <LDMUX_FDRSE_0to3[3].I_BE_LDMUX_0to3> in unit <flex_addr_cntr.1>.
    Set user-defined property "INIT =  0" for instance <LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3> in unit <flex_addr_cntr.1>.
Entity <flex_addr_cntr.1> analyzed. Unit <flex_addr_cntr.1> generated.

Analyzing generic Entity <addr_reg_cntr_brst_flex.2> in library <plbv46_slave_burst_v1_01_a> (Architecture <implementation>).
	C_CACHLINE_ADDR_MODE = 0
	C_NUM_ADDR_BITS = 10
	C_PLB_DWIDTH = 32
	C_SPLB_P2P = 0
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.I_SNGL_S_H_REG> in unit <addr_reg_cntr_brst_flex.2>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.I_CACHLN_S_H_REG> in unit <addr_reg_cntr_brst_flex.2>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.I_BURST_S_H_REG> in unit <addr_reg_cntr_brst_flex.2>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG> in unit <addr_reg_cntr_brst_flex.2>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG> in unit <addr_reg_cntr_brst_flex.2>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG> in unit <addr_reg_cntr_brst_flex.2>.
    Set user-defined property "INIT =  0" for instance <GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG> in unit <addr_reg_cntr_brst_flex.2>.
WARNING:Xst:753 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" line 628: Unconnected output port 'Carry_Out' of component 'flex_addr_cntr'.
Entity <addr_reg_cntr_brst_flex.2> analyzed. Unit <addr_reg_cntr_brst_flex.2> generated.

Analyzing generic Entity <flex_addr_cntr.2> in library <plbv46_slave_burst_v1_01_a> (Architecture <implementation>).
	C_AWIDTH = 10
	C_DWIDTH = 32
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[7].I_LUT_N> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[7].I_FDRE_N> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[8].I_LUT_N> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[8].I_FDRE_N> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F202" for instance <GEN_ADDR_MSB[9].I_LUT_N> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_MSB[9].I_FDRE_N> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F202" for instance <I_LUT6> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <I_FDRE6> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F202" for instance <I_LUT5> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <I_FDRE5> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F202" for instance <I_LUT4> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <I_FDRE4> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F202" for instance <I_LUT3> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_FOR_32_64.I_FDRE3> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F202" for instance <I_LUT2> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <GEN_ADDR_FOR_32.I_FDRE2> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F202" for instance <I_LUT1> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <I_FDRE1> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F202" for instance <I_LUT0> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <I_FDRE0> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  FF31" for instance <I_BE_GEN_LUT0> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  FF32" for instance <I_BE_GEN_LUT1> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  FFC4" for instance <I_BE_GEN_LUT2> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  FFC8" for instance <I_BE_GEN_LUT4> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F088" for instance <LDMUX_FDRSE_0to3[0].I_BE_LDMUX_0to3> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <LDMUX_FDRSE_0to3[0].I_FDRSE_BE0to3> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F088" for instance <LDMUX_FDRSE_0to3[1].I_BE_LDMUX_0to3> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <LDMUX_FDRSE_0to3[1].I_FDRSE_BE0to3> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F088" for instance <LDMUX_FDRSE_0to3[2].I_BE_LDMUX_0to3> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <LDMUX_FDRSE_0to3[2].I_FDRSE_BE0to3> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  F088" for instance <LDMUX_FDRSE_0to3[3].I_BE_LDMUX_0to3> in unit <flex_addr_cntr.2>.
    Set user-defined property "INIT =  0" for instance <LDMUX_FDRSE_0to3[3].I_FDRSE_BE0to3> in unit <flex_addr_cntr.2>.
Entity <flex_addr_cntr.2> analyzed. Unit <flex_addr_cntr.2> generated.

Analyzing generic Entity <data_mirror_128> in library <plbv46_slave_burst_v1_01_a> (Architecture <implementation>).
	C_IPIF_DWIDTH = 32
	C_PLB_AWIDTH = 10
	C_PLB_DWIDTH = 32
	C_SMALLEST = 32
Entity <data_mirror_128> analyzed. Unit <data_mirror_128> generated.

Analyzing generic Entity <EMC> in library <emc_common_v4_01_a> (Architecture <IMP>).
	C_BUS_CLOCK_PERIOD_PS = 20000
	C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_1 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_2 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_3 = 0
	C_INCLUDE_NEGEDGE_IOREGS = 0
	C_IPIF_AWIDTH = 32
	C_IPIF_DWIDTH = 32
	C_MAX_MEM_WIDTH = 16
	C_MEM0_BASEADDR = "10000010000000000000000000000000"
	C_MEM0_HIGHADDR = "10000010111111111111111111111111"
	C_MEM0_WIDTH = 16
	C_MEM1_BASEADDR = "11111111111111111111111111111111"
	C_MEM1_HIGHADDR = "00000000000000000000000000000000"
	C_MEM1_WIDTH = 32
	C_MEM2_BASEADDR = "11111111111111111111111111111111"
	C_MEM2_HIGHADDR = "00000000000000000000000000000000"
	C_MEM2_WIDTH = 32
	C_MEM3_BASEADDR = "11111111111111111111111111111111"
	C_MEM3_HIGHADDR = "00000000000000000000000000000000"
	C_MEM3_WIDTH = 32
	C_NUM_BANKS_MEM = 1
	C_PAGEMODE_FLASH_0 = 0
	C_PAGEMODE_FLASH_1 = 0
	C_PAGEMODE_FLASH_2 = 0
	C_PAGEMODE_FLASH_3 = 0
	C_SPLB_DWIDTH = 32
	C_SYNCH_MEM_0 = 0
	C_SYNCH_MEM_1 = 0
	C_SYNCH_MEM_2 = 0
	C_SYNCH_MEM_3 = 0
	C_SYNCH_PIPEDELAY_0 = 2
	C_SYNCH_PIPEDELAY_1 = 2
	C_SYNCH_PIPEDELAY_2 = 2
	C_SYNCH_PIPEDELAY_3 = 2
	C_TAVDV_PS_MEM_0 = 85000
	C_TAVDV_PS_MEM_1 = 15000
	C_TAVDV_PS_MEM_2 = 15000
	C_TAVDV_PS_MEM_3 = 15000
	C_TCEDV_PS_MEM_0 = 85000
	C_TCEDV_PS_MEM_1 = 15000
	C_TCEDV_PS_MEM_2 = 15000
	C_TCEDV_PS_MEM_3 = 15000
	C_THZCE_PS_MEM_0 = 8000
	C_THZCE_PS_MEM_1 = 7000
	C_THZCE_PS_MEM_2 = 7000
	C_THZCE_PS_MEM_3 = 7000
	C_THZOE_PS_MEM_0 = 8000
	C_THZOE_PS_MEM_1 = 7000
	C_THZOE_PS_MEM_2 = 7000
	C_THZOE_PS_MEM_3 = 7000
	C_TLZWE_PS_MEM_0 = 5000
	C_TLZWE_PS_MEM_1 = 0
	C_TLZWE_PS_MEM_2 = 0
	C_TLZWE_PS_MEM_3 = 0
	C_TPACC_PS_FLASH_0 = 25000
	C_TPACC_PS_FLASH_1 = 25000
	C_TPACC_PS_FLASH_2 = 25000
	C_TPACC_PS_FLASH_3 = 25000
	C_TWC_PS_MEM_0 = 85000
	C_TWC_PS_MEM_1 = 15000
	C_TWC_PS_MEM_2 = 15000
	C_TWC_PS_MEM_3 = 15000
	C_TWP_PS_MEM_0 = 55000
	C_TWP_PS_MEM_1 = 12000
	C_TWP_PS_MEM_2 = 12000
	C_TWP_PS_MEM_3 = 12000
Entity <EMC> analyzed. Unit <EMC> generated.

Analyzing generic Entity <ipic_if> in library <emc_common_v4_01_a> (Architecture <imp>).
	C_IPIF_DWIDTH = 32
	C_NUM_BANKS_MEM = 1
	C_SPLB_DWIDTH = 32
Entity <ipic_if> analyzed. Unit <ipic_if> generated.

Analyzing generic Entity <ld_arith_reg.1> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_ADD_SUB_NOT = false
	C_AD_OFFSET = 0
	C_AD_WIDTH = 1
	C_LD_OFFSET = 0
	C_LD_WIDTH = 7
	C_REG_WIDTH = 7
	C_RESET_VALUE = "0000000"
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
Entity <ld_arith_reg.1> analyzed. Unit <ld_arith_reg.1> generated.

Analyzing Entity <mem_state_machine> in library <emc_common_v4_01_a> (Architecture <imp>).
WARNING:Xst:819 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/mem_state_machine.vhd" line 342: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <addr_align_rd_d1>, <new_page_d1>
    Set user-defined property "INIT =  0" for instance <READ_COMPLETE_PIPE_GEN[0].READ_COMPLETE_PIPE> in unit <mem_state_machine>.
    Set user-defined property "INIT =  0" for instance <READ_COMPLETE_PIPE_GEN[1].READ_COMPLETE_PIPE> in unit <mem_state_machine>.
    Set user-defined property "INIT =  0" for instance <READ_COMPLETE_PIPE_GEN[2].READ_COMPLETE_PIPE> in unit <mem_state_machine>.
    Set user-defined property "INIT =  0" for instance <READ_COMPLETE_PIPE_GEN[3].READ_COMPLETE_PIPE> in unit <mem_state_machine>.
    Set user-defined property "INIT =  0" for instance <READ_COMPLETE_PIPE_GEN[4].READ_COMPLETE_PIPE> in unit <mem_state_machine>.
    Set user-defined property "INIT =  0" for instance <READ_COMPLETE_PIPE_GEN[5].READ_COMPLETE_PIPE> in unit <mem_state_machine>.
    Set user-defined property "INIT =  0" for instance <READ_COMPLETE_PIPE_GEN[6].READ_COMPLETE_PIPE> in unit <mem_state_machine>.
Entity <mem_state_machine> analyzed. Unit <mem_state_machine> generated.

Analyzing generic Entity <addr_counter_mux> in library <emc_common_v4_01_a> (Architecture <imp>).
	C_ADDR_CNTR_WIDTH = 2
	C_ADDR_OFFSET = 2
	C_GLOBAL_DATAWIDTH_MATCH = 1
	C_IPIF_AWIDTH = 32
	C_IPIF_DWIDTH = 32
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[0].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[1].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[2].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[3].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[4].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[5].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[6].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[7].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[8].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[9].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[10].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[11].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[12].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[13].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[14].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[15].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[16].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[17].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[18].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[19].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[20].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[21].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[22].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[23].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[24].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[25].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[26].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[27].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[28].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[29].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[30].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <ADDRESS_STORE_GEN[31].ADDRESS_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <BEN_STORE_GEN[0].BEN_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <BEN_STORE_GEN[1].BEN_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <BEN_STORE_GEN[2].BEN_REG> in unit <addr_counter_mux>.
    Set user-defined property "INIT =  0" for instance <BEN_STORE_GEN[3].BEN_REG> in unit <addr_counter_mux>.
Entity <addr_counter_mux> analyzed. Unit <addr_counter_mux> generated.

Analyzing generic Entity <ld_arith_reg.2> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_ADD_SUB_NOT = false
	C_AD_OFFSET = 0
	C_AD_WIDTH = 1
	C_LD_OFFSET = 0
	C_LD_WIDTH = 2
	C_REG_WIDTH = 2
	C_RESET_VALUE = "00"
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
Entity <ld_arith_reg.2> analyzed. Unit <ld_arith_reg.2> generated.

Analyzing Entity <counters> in library <emc_common_v4_01_a> (Architecture <imp>).
Entity <counters> analyzed. Unit <counters> generated.

Analyzing generic Entity <ld_arith_reg.3> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_ADD_SUB_NOT = false
	C_AD_OFFSET = 0
	C_AD_WIDTH = 1
	C_LD_OFFSET = 0
	C_LD_WIDTH = 5
	C_REG_WIDTH = 5
	C_RESET_VALUE = "11111"
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 331: Instantiating black box module <FDSE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 331: Instantiating black box module <FDSE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 331: Instantiating black box module <FDSE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 331: Instantiating black box module <FDSE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 331: Instantiating black box module <FDSE>.
Entity <ld_arith_reg.3> analyzed. Unit <ld_arith_reg.3> generated.

Analyzing generic Entity <ld_arith_reg.4> in library <proc_common_v3_00_a> (Architecture <imp>).
	C_ADD_SUB_NOT = false
	C_AD_OFFSET = 0
	C_AD_WIDTH = 1
	C_LD_OFFSET = 0
	C_LD_WIDTH = 5
	C_REG_WIDTH = 5
	C_RESET_VALUE = "00000"
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 284: Instantiating black box module <MULT_AND>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 294: Instantiating black box module <MUXCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 305: Instantiating black box module <XORCY>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd" line 321: Instantiating black box module <FDRE>.
Entity <ld_arith_reg.4> analyzed. Unit <ld_arith_reg.4> generated.

Analyzing generic Entity <select_param> in library <emc_common_v4_01_a> (Architecture <IMP>).
	C_GLOBAL_DATAWIDTH_MATCH = 1
	C_GLOBAL_SYNC_MEM = 0
	C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
	C_INCLUDE_DATAWIDTH_MATCHING_1 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_2 = 0
	C_INCLUDE_DATAWIDTH_MATCHING_3 = 0
	C_IPIF_AWIDTH = 32
	C_IPIF_DWIDTH = 32
	C_MEM0_WIDTH = 16
	C_MEM1_WIDTH = 32
	C_MEM2_WIDTH = 32
	C_MEM3_WIDTH = 32
	C_NUM_BANKS_MEM = 1
	C_PAGEMODE_FLASH = 0
	C_PAGEMODE_FLASH_0 = 0
	C_PAGEMODE_FLASH_1 = 0
	C_PAGEMODE_FLASH_2 = 0
	C_PAGEMODE_FLASH_3 = 0
	C_SYNCH_MEM_0 = 0
	C_SYNCH_MEM_1 = 0
	C_SYNCH_MEM_2 = 0
	C_SYNCH_MEM_3 = 0
	C_SYNCH_PIPEDELAY_0 = 2
	C_SYNCH_PIPEDELAY_1 = 2
	C_SYNCH_PIPEDELAY_2 = 2
	C_SYNCH_PIPEDELAY_3 = 2
	THZCNT_0 = "00001"
	THZCNT_1 = "00001"
	THZCNT_2 = "00001"
	THZCNT_3 = "00001"
	TLZCNT_0 = "00001"
	TLZCNT_1 = "00001"
	TLZCNT_2 = "00001"
	TLZCNT_3 = "00001"
	TPACC_0 = "00010"
	TPACC_1 = "00010"
	TPACC_2 = "00010"
	TPACC_3 = "00010"
	TRDCNT_0 = "00101"
	TRDCNT_1 = "00001"
	TRDCNT_2 = "00001"
	TRDCNT_3 = "00001"
	TWRCNT_0 = "00101"
	TWRCNT_1 = "00001"
	TWRCNT_2 = "00001"
	TWRCNT_3 = "00001"
Entity <select_param> analyzed. Unit <select_param> generated.

Analyzing generic Entity <mem_steer> in library <emc_common_v4_01_a> (Architecture <imp>).
	C_ADDR_CNTR_WIDTH = 2
	C_GLOBAL_DATAWIDTH_MATCH = 1
	C_GLOBAL_SYNC_MEM = 0
	C_IPIF_DWIDTH = 32
	C_MAX_MEM_WIDTH = 16
	C_MIN_MEM_WIDTH = 8
	C_NUM_BANKS_MEM = 1
    Set user-defined property "INIT =  0" for instance <ASYNC_MEM_RDACK_GEN.RDACK_PIPE_GEN_ASYNC[0].RDACK_PIPE_ASYNC> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <ASYNC_MEM_RDACK_GEN.RDACK_PIPE_GEN_ASYNC[1].RDACK_PIPE_ASYNC> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <ASYNC_MEM_RDACK_GEN.AALIGN_PIPE_GEN[0].AALIGN_PIPE> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <ASYNC_MEM_RDACK_GEN.AALIGN_PIPE_GEN[1].AALIGN_PIPE> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[0].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[1].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[2].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[3].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[4].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[5].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[6].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[7].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[8].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[9].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[10].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[11].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[12].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[13].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[14].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[15].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[16].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[17].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[18].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[19].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[20].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[21].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[22].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[23].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[24].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[25].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[26].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[27].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[28].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[29].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[30].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <DATA_STORE_GEN[31].WRDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[0].RDDATA_BYTE_GEN[0].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[0].RDDATA_BYTE_GEN[1].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[0].RDDATA_BYTE_GEN[2].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[0].RDDATA_BYTE_GEN[3].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[0].RDDATA_BYTE_GEN[4].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[0].RDDATA_BYTE_GEN[5].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[0].RDDATA_BYTE_GEN[6].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[0].RDDATA_BYTE_GEN[7].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[1].RDDATA_BYTE_GEN[0].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[1].RDDATA_BYTE_GEN[1].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[1].RDDATA_BYTE_GEN[2].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[1].RDDATA_BYTE_GEN[3].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[1].RDDATA_BYTE_GEN[4].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[1].RDDATA_BYTE_GEN[5].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[1].RDDATA_BYTE_GEN[6].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[1].RDDATA_BYTE_GEN[7].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[2].RDDATA_BYTE_GEN[0].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[2].RDDATA_BYTE_GEN[1].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[2].RDDATA_BYTE_GEN[2].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[2].RDDATA_BYTE_GEN[3].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[2].RDDATA_BYTE_GEN[4].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[2].RDDATA_BYTE_GEN[5].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[2].RDDATA_BYTE_GEN[6].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[2].RDDATA_BYTE_GEN[7].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[3].RDDATA_BYTE_GEN[0].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[3].RDDATA_BYTE_GEN[1].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[3].RDDATA_BYTE_GEN[2].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[3].RDDATA_BYTE_GEN[3].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[3].RDDATA_BYTE_GEN[4].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[3].RDDATA_BYTE_GEN[5].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[3].RDDATA_BYTE_GEN[6].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_GEN[3].RDDATA_BYTE_GEN[7].RDDATA_REG> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_PATH_MUX_GEN.ASYNC_ADDR_CNT_GEN.RDDATA_EN_GEN_ASYNC[0].RDDATA_EN_REG_ASYNC> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_PATH_MUX_GEN.ASYNC_ADDR_CNT_GEN.RDDATA_EN_GEN_ASYNC[1].RDDATA_EN_REG_ASYNC> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_PATH_MUX_GEN.ASYNC_ADDR_CNT_GEN.RDDATA_EN_GEN_ASYNC[2].RDDATA_EN_REG_ASYNC> in unit <mem_steer>.
    Set user-defined property "INIT =  0" for instance <RDDATA_PATH_MUX_GEN.ASYNC_ADDR_CNT_GEN.RDDATA_EN_GEN_ASYNC[3].RDDATA_EN_REG_ASYNC> in unit <mem_steer>.
WARNING:Xst:790 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/mem_steer.vhd" line 1419: Index value(s) does not match array range, simulation mismatch.
Entity <mem_steer> analyzed. Unit <mem_steer> generated.

Analyzing generic Entity <io_registers> in library <emc_common_v4_01_a> (Architecture <imp>).
	C_INCLUDE_NEGEDGE_IOREGS = 0
	C_IPIF_AWIDTH = 32
	C_MAX_MEM_WIDTH = 16
	C_NUM_BANKS_MEM = 1
Entity <io_registers> analyzed. Unit <io_registers> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <data_mirror_128>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd".
WARNING:Xst:647 - Input <Addr_In> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <sig_addr_bits_A28_A29> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sig_addr_bit_A29> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sig_addr_bit_A28> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <data_mirror_128> synthesized.


Synthesizing Unit <be_reset_gen>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd".
WARNING:Xst:647 - Input <Addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MSize> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <be_reset_gen> synthesized.


Synthesizing Unit <pselect_f>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd".
WARNING:Xst:647 - Input <A<8:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <pselect_f> synthesized.


Synthesizing Unit <or_gate128>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd".
WARNING:Xst:1780 - Signal <test> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <or_gate128> synthesized.


Synthesizing Unit <select_param>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/select_param.vhd".
WARNING:Xst:647 - Input <Bus2IP_Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_Mem_CS<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_RNW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_Addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_Reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <page_mode_enable> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mem_width> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ADDR_REG_0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <select_param> synthesized.


Synthesizing Unit <io_registers>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/io_registers.vhd".
    Register <mem_cken_reg> equivalent to <mem_adv_ldn_reg> has been removed
    Register <mem_lbon_reg> equivalent to <mem_adv_ldn_reg> has been removed
    Found 16-bit register for signal <Mem_DQ_I_int>.
    Found 32-bit register for signal <mem_a_reg>.
    Found 1-bit register for signal <mem_adv_ldn_reg>.
    Found 2-bit register for signal <mem_ben_reg>.
    Found 1-bit register for signal <mem_ce_reg<0>>.
    Found 1-bit register for signal <mem_cen_reg<0>>.
    Found 16-bit register for signal <mem_dq_o_reg>.
    Found 16-bit register for signal <mem_dq_t_reg>.
    Found 1-bit register for signal <mem_oen_reg<0>>.
    Found 2-bit register for signal <mem_qwen_reg>.
    Found 1-bit register for signal <mem_rnw_reg>.
    Found 1-bit register for signal <mem_rpn_reg>.
    Found 1-bit register for signal <mem_wen_reg>.
    Summary:
	inferred  91 D-type flip-flop(s).
Unit <io_registers> synthesized.


Synthesizing Unit <plb_address_decoder>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd".
WARNING:Xst:647 - Input <Address_In_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Address_Valid_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <addr_out_s_h> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <plb_address_decoder> synthesized.


Synthesizing Unit <wr_buffer>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd".
WARNING:Xst:646 - Signal <addr_cy<4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit xor2 for signal <hsum_A_0$xor0000> created at line 281.
    Found 1-bit xor2 for signal <hsum_A_1$xor0000> created at line 281.
    Found 1-bit xor2 for signal <hsum_A_2$xor0000> created at line 281.
    Found 1-bit xor2 for signal <hsum_A_3$xor0000> created at line 281.
Unit <wr_buffer> synthesized.


Synthesizing Unit <counter_f>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd".
WARNING:Xst:646 - Signal <alu_cy<6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit xor2 for signal <count_AddSub_0$xor0000> created at line 233.
    Found 1-bit xor2 for signal <count_AddSub_0$xor0001> created at line 233.
    Found 1-bit xor2 for signal <count_AddSub_1$xor0000> created at line 233.
    Found 1-bit xor2 for signal <count_AddSub_1$xor0001> created at line 233.
    Found 1-bit xor2 for signal <count_AddSub_2$xor0000> created at line 233.
    Found 1-bit xor2 for signal <count_AddSub_2$xor0001> created at line 233.
    Found 1-bit xor2 for signal <count_AddSub_3$xor0000> created at line 233.
    Found 1-bit xor2 for signal <count_AddSub_3$xor0001> created at line 233.
    Found 1-bit xor2 for signal <count_AddSub_4$xor0000> created at line 233.
    Found 1-bit xor2 for signal <count_AddSub_4$xor0001> created at line 233.
    Found 1-bit xor2 for signal <count_AddSub_5$xor0000> created at line 233.
    Found 1-bit xor2 for signal <count_AddSub_5$xor0001> created at line 233.
Unit <counter_f> synthesized.


Synthesizing Unit <flex_addr_cntr_1>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd".
WARNING:Xst:647 - Input <burst_bytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <xfer_64> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <be_extended> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <flex_addr_cntr_1> synthesized.


Synthesizing Unit <flex_addr_cntr_2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd".
WARNING:Xst:647 - Input <burst_bytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <xfer_64> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <be_extended> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <flex_addr_cntr_2> synthesized.


Synthesizing Unit <mem_state_machine>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/mem_state_machine.vhd".
WARNING:Xst:647 - Input <Bus2IP_RNW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Using one-hot encoding for signal <crnt_state>.
    Found 1-bit register for signal <Data_strobe>.
    Found 1-bit register for signal <Addr_align_rd>.
    Found 1-bit register for signal <addr_align_rd_d1>.
    Found 1-bit register for signal <addr_cnt_ce_reg>.
    Found 1-bit register for signal <addr_cnt_rst_reg>.
    Found 7-bit register for signal <crnt_state>.
    Found 1-bit register for signal <cs_strobe_reg>.
    Found 1-bit register for signal <mem_cen_reg>.
    Found 1-bit register for signal <mem_oen_reg>.
    Found 1-bit register for signal <mem_wen_reg>.
    Found 1-bit register for signal <new_page_d1>.
    Found 1-bit register for signal <read_ack_reg>.
    Found 1-bit register for signal <read_data_en_reg>.
    Found 1-bit register for signal <transaction_done_reg>.
    Summary:
	inferred  20 D-type flip-flop(s).
Unit <mem_state_machine> synthesized.


Synthesizing Unit <mem_steer>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/mem_steer.vhd".
WARNING:Xst:647 - Input <Synch_mem> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Two_pipe_delay> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_Mem_CS<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Addr_align> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <write_data_d2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <write_data_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <read_data_en_d<4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <read_data_ce<4:7>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <read_ack_d<3:5>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mem_dq_t_cmb<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <mem_dq_t_cmb<1:3>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <addr_cnt_d4> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <addr_cnt_d3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr_align_read> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <addr_align_d<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <addr_align_d<3:5>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found 2-bit register for signal <addr_cnt_d1>.
    Found 2-bit register for signal <addr_cnt_d2>.
    Found 1-bit 4-to-1 multiplexer for signal <mem_be_i<0>>.
    Found 1-bit 4-to-1 multiplexer for signal <mem_be_i_0$mux0004> created at line 926.
    Found 1-bit register for signal <mem_dqt_t_d>.
    Found 32-bit 4-to-1 multiplexer for signal <read_data>.
    Found 8-bit 4-to-1 multiplexer for signal <write_data_cmb<0:7>>.
    Found 1-bit 4-to-1 multiplexer for signal <write_data_cmb_0$mux0004> created at line 896.
    Found 1-bit 4-to-1 multiplexer for signal <write_data_cmb_1$mux0004> created at line 896.
    Found 1-bit 4-to-1 multiplexer for signal <write_data_cmb_2$mux0004> created at line 896.
    Found 1-bit 4-to-1 multiplexer for signal <write_data_cmb_3$mux0004> created at line 896.
    Found 1-bit 4-to-1 multiplexer for signal <write_data_cmb_4$mux0004> created at line 896.
    Found 1-bit 4-to-1 multiplexer for signal <write_data_cmb_5$mux0004> created at line 896.
    Found 1-bit 4-to-1 multiplexer for signal <write_data_cmb_6$mux0004> created at line 896.
    Found 1-bit 4-to-1 multiplexer for signal <write_data_cmb_7$mux0004> created at line 896.
    Summary:
	inferred   5 D-type flip-flop(s).
	inferred  50 Multiplexer(s).
Unit <mem_steer> synthesized.


Synthesizing Unit <ld_arith_reg_1>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd".
WARNING:Xst:646 - Signal <cry<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <ld_arith_reg_1> synthesized.


Synthesizing Unit <ld_arith_reg_2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd".
WARNING:Xst:646 - Signal <cry<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <ld_arith_reg_2> synthesized.


Synthesizing Unit <ld_arith_reg_3>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd".
WARNING:Xst:646 - Signal <cry<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit xor2 for signal <q_i_ns_4$xor0000>.
Unit <ld_arith_reg_3> synthesized.


Synthesizing Unit <ld_arith_reg_4>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ld_arith_reg.vhd".
WARNING:Xst:646 - Signal <cry<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit xor2 for signal <q_i_ns_4$xor0000>.
Unit <ld_arith_reg_4> synthesized.


Synthesizing Unit <burst_support>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd".
WARNING:Xst:647 - Input <WrBuf_wen> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RNW> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cntl_done_reg>.
    Found 32-bit comparator less for signal <resp_db_load_value$cmp_gt0000> created at line 249.
    Found 1-bit register for signal <resp_done_reg>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <burst_support> synthesized.


Synthesizing Unit <addr_reg_cntr_brst_flex_1>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd".
WARNING:Xst:647 - Input <Addr_Cnt_Size_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <s_h_size<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <master_64> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <master_32> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <master_128> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cacheln_4> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <addr_reg_cntr_brst_flex_1> synthesized.


Synthesizing Unit <addr_reg_cntr_brst_flex_2>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd".
WARNING:Xst:647 - Input <Addr_Cnt_Size_Erly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <s_h_size<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <master_64> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <master_32> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <master_128> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cacheln_4> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <addr_reg_cntr_brst_flex_2> synthesized.


Synthesizing Unit <ipic_if>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/ipic_if.vhd".
WARNING:Xst:647 - Input <Burst_length<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <IP2Bus_WrAck>.
    Found 1-bit register for signal <IP2Bus_AddrAck>.
    Found 1-bit register for signal <IP2Bus_RdAck>.
    Found 1-bit register for signal <bus2ip_mem_cs_reg<0>>.
    Found 1-bit register for signal <pend_rdreq>.
    Found 1-bit register for signal <pend_wrreq>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <ipic_if> synthesized.


Synthesizing Unit <addr_counter_mux>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/addr_counter_mux.vhd".
WARNING:Xst:647 - Input <Address_strobe> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit up counter for signal <addr_cnt_i>.
    Found 32-bit 4-to-1 multiplexer for signal <mem_addr_cmb>.
    Summary:
	inferred   1 Counter(s).
	inferred  32 Multiplexer(s).
Unit <addr_counter_mux> synthesized.


Synthesizing Unit <counters>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/counters.vhd".
Unit <counters> synthesized.


Synthesizing Unit <EMC>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/emc_common_v4_01_a/hdl/vhdl/emc.vhd".
WARNING:Xst:647 - Input <Bus2IP_RdReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_WrReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_Burst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <mem_be_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <cs_Strobe> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <bus2Mem_CS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <addr_align> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Tlz_cnt_en> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <Thz_cnt_en> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <EMC> synthesized.


Synthesizing Unit <plb_slave_attachment>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd".
WARNING:Xst:647 - Input <PLB_UABus> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <wrreq_out> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <write_cntrl_burst> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <wrbuf_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <wr_dphase_active_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <wr_buffer_rst> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <wr_buf_rden_ns> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <wr_buf_rden> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <wr_buf_done_in> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wrdack_i_dly1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_wait_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_rddack_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <sl_addrack_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <set_sl_busy_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <rnw_s_h> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <response_ack_dly1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb_wrprim_reg> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <plb_wrdbus_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <plb_wrburst_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <plb_size_sh_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb_savalid_reg> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb_rdprim_reg> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb_buslock_reg> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <msize_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <fixed_dbeat_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <dbeat_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <control_done_strb> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <control_done_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <bus2ip_wrreq_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <bus2ip_wrburst_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <bus2ip_rdreq_ns> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <brstlength_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <addr_cntr_load_d1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <CS_Early_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_0> for signal <addr_cntl_cs>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 5                                              |
    | Inputs             | 2                                              |
    | Outputs            | 1                                              |
    | Clock              | Bus_Clk                   (rising_edge)        |
    | Reset              | Bus_Reset                 (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | validate_req                                   |
    | Power Up State     | validate_req                                   |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <plb_read_cntl_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 10                                             |
    | Inputs             | 5                                              |
    | Outputs            | 3                                              |
    | Clock              | Bus_Clk                   (rising_edge)        |
    | Reset              | Bus_Reset                 (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | pbrd_idle                                      |
    | Power Up State     | pbrd_idle                                      |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_2> for signal <plb_write_cntl_state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 11                                             |
    | Inputs             | 7                                              |
    | Outputs            | 2                                              |
    | Clock              | Bus_Clk                   (rising_edge)        |
    | Reset              | Bus_Reset                 (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | pbwr_idle                                      |
    | Power Up State     | pbwr_idle                                      |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_3> for signal <ipif_wr_cntl_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 12                                             |
    | Inputs             | 7                                              |
    | Outputs            | 3                                              |
    | Clock              | Bus_Clk                   (rising_edge)        |
    | Reset              | Bus_Reset                 (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | iwr_idle                                       |
    | Power Up State     | iwr_idle                                       |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <addr_cycle_flush>.
    Found 1-bit register for signal <burst_transfer_reg>.
    Found 7-bit register for signal <burstlength_i>.
    Found 32-bit register for signal <bus2ip_data_i>.
    Found 1-bit register for signal <bus2ip_rdburst_i>.
    Found 1-bit register for signal <bus2ip_rnw_i>.
    Found 1-bit register for signal <bus2ip_wrburst_i>.
    Found 1-bit register for signal <cacheln_burst_reg>.
    Found 1-bit register for signal <clear_sl_rd_busy>.
    Found 4-bit down counter for signal <data_cycle_count>.
    Found 1-bit register for signal <extend_wr_busy>.
    Found 4-bit comparator lessequal for signal <line_count_done$cmp_le0000> created at line 2300.
    Found 1-bit register for signal <master_id_vector<0>>.
    Found 32-bit register for signal <plb_abus_reg>.
    Found 4-bit register for signal <plb_be_reg>.
    Found 1-bit register for signal <plb_masterid_reg<0>>.
    Found 1-bit register for signal <plb_pavalid_reg>.
    Found 1-bit register for signal <plb_rdburst_reg>.
    Found 1-bit register for signal <plb_rnw_reg>.
    Found 4-bit register for signal <plb_size_reg>.
    Found 3-bit register for signal <plb_type_reg>.
    Found 1-bit register for signal <rd_burst_done>.
    Found 1-bit register for signal <rd_data_ack>.
    Found 10-bit register for signal <sa2mirror_rdaddr_i>.
    Found 2-bit register for signal <sa2mirror_sh_size_i>.
    Found 1-bit register for signal <set_sl_busy>.
    Found 1-bit register for signal <sl_addrack_i>.
    Found 1-bit register for signal <sl_busy>.
    Found 2-bit register for signal <sl_mbusy_i>.
    Found 2-bit register for signal <sl_mrderr_i>.
    Found 1-bit register for signal <sl_rdbterm_i>.
    Found 1-bit register for signal <sl_rdcomp_i>.
    Found 32-bit register for signal <sl_rddbus1_i>.
    Found 4-bit register for signal <sl_rdwdaddr_i>.
    Found 1-bit register for signal <sl_rearbitrate_i>.
    Found 1-bit register for signal <sl_wrbterm_i>.
    Found 1-bit register for signal <sl_wrcomp_i>.
    Found 1-bit register for signal <sl_wrdack_i>.
    Found 4-bit comparator less for signal <wrbuf_goingfull$cmp_lt0000> created at line 2072.
    Summary:
	inferred   4 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred 158 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <plb_slave_attachment> synthesized.


Synthesizing Unit <plbv46_slave_burst>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd".
WARNING:Xst:647 - Input <PLB_wrPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_SAValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_wrPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendReq> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPendPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_busLock> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_reqPri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_lockErr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_TAttribute> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_rdPrim> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PLB_abort> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <plbv46_slave_burst> synthesized.


Synthesizing Unit <mch_plbv46_slave_burst>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mch_plbv46_slave_burst_v2_01_a/hdl/vhdl/mch_plbv46_slave_burst.vhd".
WARNING:Xst:1305 - Output <Bus2IP_RdCE> is never assigned. Tied to value 0.
WARNING:Xst:1305 - Output <Bus2IP_WrCE> is never assigned. Tied to value 0.
WARNING:Xst:1780 - Signal <plb2ip_wrreq> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_wrce> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_rnw> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_rdreq> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_rdce> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_cs> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_ce> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_burstlength> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_burst> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_be> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_addrvalid> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <plb2ip_addr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2plb_wrack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2plb_rdack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2plb_error> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2plb_data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2plb_addrack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <ip2plb_ack> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <bus2ip_wrreq_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <bus2ip_rdreq_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <bus2ip_cs_d1>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <mch_plbv46_slave_burst> synthesized.


Synthesizing Unit <xps_mch_emc>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/hdl/vhdl/xps_mch_emc.vhd".
WARNING:Xst:646 - Signal <mch_readdata_read> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mch_readdata_exists> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mch_readdata_data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mch_readdata_control> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mch_access_write> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mch_access_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mch_access_data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <mch_access_control> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <xps_mch_emc> synthesized.


Synthesizing Unit <micron_ram_wrapper>.
    Related source file is "C:/Temp/Bomberman/hdl/micron_ram_wrapper.vhd".
Unit <micron_ram_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 2-bit up counter                                      : 1
 4-bit down counter                                    : 1
# Registers                                            : 108
 1-bit register                                        : 90
 10-bit register                                       : 1
 16-bit register                                       : 3
 2-bit register                                        : 5
 3-bit register                                        : 1
 32-bit register                                       : 3
 4-bit register                                        : 3
 7-bit register                                        : 2
# Comparators                                          : 3
 32-bit comparator less                                : 1
 4-bit comparator less                                 : 1
 4-bit comparator lessequal                            : 1
# Multiplexers                                         : 51
 1-bit 4-to-1 multiplexer                              : 50
 32-bit 4-to-1 multiplexer                             : 1
# Xors                                                 : 33
 1-bit xor2                                            : 33

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/ipif_wr_cntl_state/FSM> on signal <ipif_wr_cntl_state[1:2]> with user encoding.
------------------------------
 State            | Encoding
------------------------------
 iwr_idle         | 00
 iwr_init         | 01
 iwr_burst_fixed1 | 10
 iwr_single1      | 11
------------------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/plb_write_cntl_state/FSM> on signal <plb_write_cntl_state[1:2]> with gray encoding.
------------------------------
 State            | Encoding
------------------------------
 pbwr_idle        | 00
 pbwr_burst_fixed | 01
 pbwrite_flush    | 11
------------------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/plb_read_cntl_state/FSM> on signal <plb_read_cntl_state[1:2]> with gray encoding.
------------------------------
 State            | Encoding
------------------------------
 pbrd_idle        | 00
 pbrd_single      | 11
 pbrd_burst_fixed | 01
 pbread_flush     | 10
------------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/addr_cntl_cs/FSM> on signal <addr_cntl_cs[1:2]> with gray encoding.
--------------------------
 State        | Encoding
--------------------------
 validate_req | 00
 rearbitrate  | 01
 gen_addrack  | 11
--------------------------
WARNING:Xst:2404 -  FFs/Latches <burstlength_i<0:3>> (without init value) have a constant value of 0 in block <plb_slave_attachment>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 4
# Counters                                             : 2
 2-bit up counter                                      : 1
 4-bit down counter                                    : 1
# Registers                                            : 521
 Flip-Flops                                            : 521
# Comparators                                          : 3
 32-bit comparator less                                : 1
 4-bit comparator less                                 : 1
 4-bit comparator lessequal                            : 1
# Multiplexers                                         : 51
 1-bit 4-to-1 multiplexer                              : 50
 32-bit 4-to-1 multiplexer                             : 1
# Xors                                                 : 33
 1-bit xor2                                            : 33

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <mem_adv_ldn_reg> (without init value) has a constant value of 0 in block <io_registers>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <clear_sl_rd_busy> in Unit <plb_slave_attachment> is equivalent to the following FF/Latch, which will be removed : <sl_rdcomp_i> 
INFO:Xst:2261 - The FF/Latch <set_sl_busy> in Unit <plb_slave_attachment> is equivalent to the following FF/Latch, which will be removed : <sl_addrack_i> 
WARNING:Xst:1293 - FF/Latch <crnt_state_5> has a constant value of 0 in block <mem_state_machine>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <new_page_d1> of sequential type is unconnected in block <mem_state_machine>.
INFO:Xst:2261 - The FF/Latch <addr_cntl_cs_FSM_FFd2> in Unit <plb_slave_attachment> is equivalent to the following FF/Latch, which will be removed : <addr_cycle_flush> 
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/bus2ip_cs_d1> of sequential type is unconnected in block <micron_ram_wrapper>.
INFO:Xst:2261 - The FF/Latch <addr_cnt_rst_reg> in Unit <mem_state_machine> is equivalent to the following FF/Latch, which will be removed : <Data_strobe> 

Optimizing unit <micron_ram_wrapper> ...

Optimizing unit <io_registers> ...

Optimizing unit <plb_address_decoder> ...

Optimizing unit <wr_buffer> ...

Optimizing unit <counter_f> ...

Optimizing unit <flex_addr_cntr_1> ...

Optimizing unit <flex_addr_cntr_2> ...

Optimizing unit <mem_state_machine> ...

Optimizing unit <mem_steer> ...

Optimizing unit <ld_arith_reg_1> ...

Optimizing unit <ld_arith_reg_2> ...

Optimizing unit <ld_arith_reg_3> ...

Optimizing unit <ld_arith_reg_4> ...

Optimizing unit <burst_support> ...

Optimizing unit <addr_reg_cntr_brst_flex_1> ...

Optimizing unit <addr_reg_cntr_brst_flex_2> ...

Optimizing unit <ipic_if> ...

Optimizing unit <addr_counter_mux> ...

Optimizing unit <counters> ...

Optimizing unit <plb_slave_attachment> ...
INFO:Xst:2261 - The FF/Latch <plb_write_cntl_state_FSM_FFd1> in Unit <plb_slave_attachment> is equivalent to the following FF/Latch, which will be removed : <sl_wrcomp_i> 
INFO:Xst:2261 - The FF/Latch <plb_write_cntl_state_FSM_FFd1> in Unit <plb_slave_attachment> is equivalent to the following FF/Latch, which will be removed : <sl_wrcomp_i> 
WARNING:Xst:1710 - FF/Latch <Micron_RAM/EMC_CTRL_I/IO_REGISTERS_I/mem_a_reg_31> (without init value) has a constant value of 0 in block <micron_ram_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Micron_RAM/EMC_CTRL_I/MEM_STATE_MACHINE_I/addr_align_rd_d1> (without init value) has a constant value of 0 in block <micron_ram_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_mrderr_i_1> (without init value) has a constant value of 0 in block <micron_ram_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_mrderr_i_0> (without init value) has a constant value of 0 in block <micron_ram_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Micron_RAM/EMC_CTRL_I/MEM_STATE_MACHINE_I/Addr_align_rd> (without init value) has a constant value of 0 in block <micron_ram_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <Micron_RAM/EMC_CTRL_I/MEM_STATE_MACHINE_I/cs_strobe_reg> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_rdaddr_i_0> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_rdaddr_i_1> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_rdaddr_i_2> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_rdaddr_i_3> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_rdaddr_i_4> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_rdaddr_i_5> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_rdaddr_i_6> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_rdaddr_i_7> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_rdaddr_i_8> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_rdaddr_i_9> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_sh_size_i_0> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sa2mirror_sh_size_i_1> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/bus2ip_rdburst_i> of sequential type is unconnected in block <micron_ram_wrapper>.
WARNING:Xst:2677 - Node <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/bus2ip_wrburst_i> of sequential type is unconnected in block <micron_ram_wrapper>.

Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <Micron_RAM/EMC_CTRL_I/IO_REGISTERS_I/mem_wen_reg> in Unit <micron_ram_wrapper> is equivalent to the following FF/Latch, which will be removed : <Micron_RAM/EMC_CTRL_I/MEM_STEER_I/mem_dqt_t_d> 
INFO:Xst:2260 - The FF/Latch <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG> in Unit <micron_ram_wrapper> is equivalent to the following FF/Latch : <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[3].I_SIZE_S_H_REG> 
INFO:Xst:2260 - The FF/Latch <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG> in Unit <micron_ram_wrapper> is equivalent to the following FF/Latch : <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[2].I_SIZE_S_H_REG> 
INFO:Xst:2260 - The FF/Latch <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_CACHLN_S_H_REG> in Unit <micron_ram_wrapper> is equivalent to the following FF/Latch : <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_CACHLN_S_H_REG> 
INFO:Xst:2260 - The FF/Latch <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_BURST_S_H_REG> in Unit <micron_ram_wrapper> is equivalent to the following FF/Latch : <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_BURST_S_H_REG> 
INFO:Xst:2260 - The FF/Latch <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG> in Unit <micron_ram_wrapper> is equivalent to the following FF/Latch : <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.GEN_S_H_SIZE_REG[1].I_SIZE_S_H_REG> 
INFO:Xst:2260 - The FF/Latch <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN2> in Unit <micron_ram_wrapper> is equivalent to the following FF/Latch : <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/GEN_WRITE_BUFFER.GEN_WRBUF_WREN1> 
INFO:Xst:2260 - The FF/Latch <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG> in Unit <micron_ram_wrapper> is equivalent to the following FF/Latch : <Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG> 

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 504
 Flip-Flops                                            : 504

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/micron_ram_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 575

Cell Usage :
# BELS                             : 586
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 2
#      LUT2                        : 59
#      LUT2_D                      : 2
#      LUT2_L                      : 7
#      LUT3                        : 73
#      LUT3_D                      : 4
#      LUT3_L                      : 2
#      LUT4                        : 190
#      LUT4_D                      : 7
#      LUT4_L                      : 4
#      MULT_AND                    : 34
#      MUXCY                       : 78
#      MUXCY_L                     : 18
#      MUXF5                       : 10
#      VCC                         : 1
#      XORCY                       : 92
# FlipFlops/Latches                : 504
#      FDR                         : 195
#      FDRE                        : 247
#      FDRS                        : 5
#      FDRSE                       : 15
#      FDS                         : 27
#      FDSE                        : 15
# Shift Registers                  : 32
#      SRL16E                      : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                      343  out of   8672     3%  
 Number of Slice Flip Flops:            472  out of  17344     2%  
 Number of 4 input LUTs:                384  out of  17344     2%  
    Number used as logic:               352
    Number used as Shift registers:      32
 Number of IOs:                         575
 Number of bonded IOBs:                   0  out of    250     0%  
    IOB Flip Flops:                      32

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+----------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                    | Load  |
-----------------------------------+----------------------------------------------------------+-------+
MCH_SPLB_Clk                       | NONE(Micron_RAM/EMC_CTRL_I/IO_REGISTERS_I/mem_oen_reg_0) | 520   |
RdClk                              | NONE(Micron_RAM/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_int_0)| 16    |
-----------------------------------+----------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.100ns (Maximum Frequency: 99.010MHz)
   Minimum input arrival time before clock: 2.956ns
   Maximum output required time after clock: 1.917ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'MCH_SPLB_Clk'
  Clock period: 10.100ns (frequency: 99.010MHz)
  Total number of paths / destination ports: 13752 / 999
-------------------------------------------------------------------------
Delay:               10.100ns (Levels of Logic = 5)
  Source:            Micron_RAM/EMC_CTRL_I/IPIC_IF_I/IP2Bus_WrAck (FF)
  Destination:       Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG (FF)
  Source Clock:      MCH_SPLB_Clk rising
  Destination Clock: MCH_SPLB_Clk rising

  Data Path: Micron_RAM/EMC_CTRL_I/IPIC_IF_I/IP2Bus_WrAck to Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/GEN_FOR_SHARED.I_SNGL_S_H_REG
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              7   0.591   0.787  Micron_RAM/EMC_CTRL_I/IPIC_IF_I/IP2Bus_WrAck (Micron_RAM/EMC_CTRL_I/IPIC_IF_I/IP2Bus_WrAck)
     LUT3:I1->O           15   0.704   1.021  Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BURST_SUPPORT/Response_Ack1 (Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/response_ack_i)
     LUT4:I3->O            1   0.704   0.424  Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/clear_sl_busy_SW0_SW0 (N101)
     LUT4_D:I3->O         12   0.704   0.996  Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/clear_sl_busy (Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/clear_sl_busy)
     LUT3_D:I2->O         11   0.704   0.968  Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/decode_s_h_cs1_2 (Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/decode_s_h_cs1)
     LUT3:I2->O           10   0.704   0.882  Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/clr_addr_be1_1 (Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_STEER_ADDRESS_COUNTER/clr_addr_be1)
     FDRE:R                    0.911          Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_ADDR_MSB[17].I_FDRE_N
    ----------------------------------------
    Total                     10.100ns (5.022ns logic, 5.078ns route)
                                       (49.7% logic, 50.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'MCH_SPLB_Clk'
  Total number of paths / destination ports: 535 / 535
-------------------------------------------------------------------------
Offset:              2.956ns (Levels of Logic = 1)
  Source:            MCH_SPLB_Rst (PAD)
  Destination:       Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_rddbus1_i_9 (FF)
  Destination Clock: MCH_SPLB_Clk rising

  Data Path: MCH_SPLB_Rst to Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_rddbus1_i_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LUT2:I1->O           32   0.704   1.262  Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_rddbus1_i_10_or00001 (Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_rddbus1_i_10_or0000)
     FDR:R                     0.911          Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_rddbus1_i_10
    ----------------------------------------
    Total                      2.956ns (1.694ns logic, 1.262ns route)
                                       (57.3% logic, 42.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'RdClk'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              0.911ns (Levels of Logic = 0)
  Source:            MCH_SPLB_Rst (PAD)
  Destination:       Micron_RAM/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_int_0 (FF)
  Destination Clock: RdClk rising

  Data Path: MCH_SPLB_Rst to Micron_RAM/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_int_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:R                     0.911          Micron_RAM/EMC_CTRL_I/IO_REGISTERS_I/Mem_DQ_I_int_15
    ----------------------------------------
    Total                      0.911ns (0.911ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'MCH_SPLB_Clk'
  Total number of paths / destination ports: 120 / 119
-------------------------------------------------------------------------
Offset:              1.917ns (Levels of Logic = 1)
  Source:            Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/rd_data_ack (FF)
  Destination:       Sl_rdDAck (PAD)
  Source Clock:      MCH_SPLB_Clk rising

  Data Path: Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/rd_data_ack to Sl_rdDAck
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.591   0.622  Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/rd_data_ack (Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/rd_data_ack)
     LUT2:I0->O            0   0.704   0.000  Micron_RAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHMENT/sl_rddack_i1 (Sl_rdDAck)
    ----------------------------------------
    Total                      1.917ns (1.295ns logic, 0.622ns route)
                                       (67.6% logic, 32.4% route)

=========================================================================


Total REAL time to Xst completion: 27.00 secs
Total CPU time to Xst completion: 27.46 secs
 
--> 

Total memory usage is 213880 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  329 (   0 filtered)
Number of infos    :   16 (   0 filtered)

