LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY system IS
PORT (
	fpga_0_LEDs_8Bit_GPIO_IO_O_pin : OUT STD_LOGIC_VECTOR(0 TO 7);
	fpga_0_LED_7SEGMENT_GPIO_IO_O_pin : OUT STD_LOGIC_VECTOR(0 TO 11);
	fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin : IN STD_LOGIC_VECTOR(0 TO 2);
	fpga_0_Switches_8Bit_GPIO_IO_I_pin : IN STD_LOGIC_VECTOR(0 TO 7);
	fpga_0_RS232_PORT_RX_pin : IN STD_LOGIC;
	fpga_0_RS232_PORT_TX_pin : OUT STD_LOGIC;
	fpga_0_Micron_RAM_Mem_A_pin : OUT STD_LOGIC_VECTOR(9 TO 31);
	fpga_0_Micron_RAM_Mem_OEN_pin : OUT STD_LOGIC;
	fpga_0_Micron_RAM_Mem_WEN_pin : OUT STD_LOGIC;
	fpga_0_Micron_RAM_Mem_BEN_pin : OUT STD_LOGIC_VECTOR(0 TO 1);
	fpga_0_Micron_RAM_Mem_DQ_pin : INOUT STD_LOGIC_VECTOR(0 TO 15);
	fpga_0_clk_1_sys_clk_pin : IN STD_LOGIC;
	fpga_0_rst_1_sys_rst_pin : IN STD_LOGIC;
	xps_ps2_0_PS2_1_DATA : INOUT STD_LOGIC;
	xps_ps2_0_PS2_1_CLK : INOUT STD_LOGIC;
	graph_acc_0_HS_pin : OUT STD_LOGIC;
	graph_acc_0_VS_pin : OUT STD_LOGIC;
	graph_acc_0_VGA_rgb_pin : OUT STD_LOGIC_VECTOR(0 TO 7)
	);
END system;

ARCHITECTURE STRUCTURE OF system IS

BEGIN
END ARCHITECTURE STRUCTURE;
