<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
					twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)> 
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET | 
							   NETDELAY | 
							   NETSKEW | 
							   PATH |
							   DEFPERIOD |
							   UNCONSTPATH |
							   DEFPATH | 
							   PATH2SETUP |
							   UNCONSTPATH2SETUP | 
							   PATHCLASS | 
							   PATHDELAY | 
							   PERIOD |
							   FREQUENCY |
							   PATHBLOCK |
							   OFFSET |
							   OFFSETIN |
							   OFFSETINCLOCK | 
							   UNCONSTOFFSETINCLOCK |
							   OFFSETINDELAY |
							   OFFSETINMOD |
							   OFFSETOUT |
							   OFFSETOUTCLOCK |
							   UNCONSTOFFSETOUTCLOCK | 
							   OFFSETOUTDELAY |
							   OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
					   twEndPtCnt?,
					   twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
						twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
					  fDCMJit CDATA #IMPLIED
					  fPhaseErr CDATA #IMPLIED
					  sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit  EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
		         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup  EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
					  best CDATA #IMPLIED requested CDATA #IMPLIED
					  errors CDATA #IMPLIED
					  score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 12.2 Trace  (nt)</twExecVer><twCopyright>Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\12.2\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 4 -n
3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf -ucf top.ucf

</twCmdLine><twDesign>top.ncd</twDesign><twDesignPath>top.ncd</twDesignPath><twPCF>top.pcf</twPCF><twPcfPath>top.pcf</twPcfPath><twDevInfo arch="spartan3e" pkg="fg320"><twDevName>xc3s1200e</twDevName><twSpeedGrade>-4</twSpeedGrade><twSpeedVer>PRODUCTION 1.27 2010-06-22</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true"  dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="3">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twInfo anchorID="4">INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</twInfo><twInfo anchorID="5">INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation.  Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</twInfo><twBody><twVerboseRpt><twConst anchorID="6" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;" ScopeName="">TS_sys_clk_pin = PERIOD TIMEGRP &quot;sys_clk_pin&quot; 50 MHz HIGH 50%;</twConstName><twItemCnt>3</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>3</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>6.000</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti (SLICE_X60Y118.BY), 1 path
</twPathRptBanner><twPathRpt anchorID="7"><twConstPath anchorID="8" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>18.212</twSlack><twSrc BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twSrc><twDest BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti</twDest><twTotPathDel>1.786</twTotPathDel><twClkSkew dest = "0.001" src = "0.003">0.002</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twSrc><twDest BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X62Y119.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_0_clk_1_sys_clk_pin_IBUF</twSrcClk><twPathDel><twSite>SLICE_X62Y119.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.652</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;2&gt;</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X60Y118.BY</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.752</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;2&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X60Y118.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.382</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti</twBEL></twPathDel><twLogDel>1.034</twLogDel><twRouteDel>0.752</twRouteDel><twTotDel>1.786</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_0_clk_1_sys_clk_pin_IBUF</twDestClk><twPctLog>57.9</twPctLog><twPctRoute>42.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1 (SLICE_X63Y118.BX), 1 path
</twPathRptBanner><twPathRpt anchorID="9"><twConstPath anchorID="10" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>18.351</twSlack><twSrc BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0</twSrc><twDest BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twDest><twTotPathDel>1.649</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0</twSrc><twDest BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X63Y118.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_0_clk_1_sys_clk_pin_IBUF</twSrcClk><twPathDel><twSite>SLICE_X63Y118.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.587</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;1&gt;</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y118.BX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.754</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X63Y118.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.308</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;1&gt;</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twBEL></twPathDel><twLogDel>0.895</twLogDel><twRouteDel>0.754</twRouteDel><twTotDel>1.649</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_0_clk_1_sys_clk_pin_IBUF</twDestClk><twPctLog>54.3</twPctLog><twPctRoute>45.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2 (SLICE_X62Y119.BY), 1 path
</twPathRptBanner><twPathRpt anchorID="11"><twConstPath anchorID="12" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>18.553</twSlack><twSrc BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twSrc><twDest BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twDest><twTotPathDel>1.447</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twSrc><twDest BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X63Y118.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">fpga_0_clk_1_sys_clk_pin_IBUF</twSrcClk><twPathDel><twSite>SLICE_X63Y118.XQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.591</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;1&gt;</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y119.BY</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.474</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;1&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X62Y119.CLK</twSite><twDelType>Tdick</twDelType><twDelInfo twEdge="twRising">0.382</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;2&gt;</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twBEL></twPathDel><twLogDel>0.973</twLogDel><twRouteDel>0.474</twRouteDel><twTotDel>1.447</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_0_clk_1_sys_clk_pin_IBUF</twDestClk><twPctLog>67.2</twPctLog><twPctRoute>32.8</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_sys_clk_pin = PERIOD TIMEGRP &quot;sys_clk_pin&quot; 50 MHz HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2 (SLICE_X62Y119.BY), 1 path
</twPathRptBanner><twPathRpt anchorID="13"><twConstPath anchorID="14" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.408</twSlack><twSrc BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twSrc><twDest BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twDest><twTotPathDel>1.004</twTotPathDel><twClkSkew dest = "0.826" src = "0.230">-0.596</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twSrc><twDest BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X63Y118.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">fpga_0_clk_1_sys_clk_pin_IBUF</twSrcClk><twPathDel><twSite>SLICE_X63Y118.XQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.473</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;1&gt;</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X62Y119.BY</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.379</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;1&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X62Y119.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.152</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;2&gt;</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twBEL></twPathDel><twLogDel>0.625</twLogDel><twRouteDel>0.379</twRouteDel><twTotDel>1.004</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_0_clk_1_sys_clk_pin_IBUF</twDestClk><twPctLog>62.3</twPctLog><twPctRoute>37.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1 (SLICE_X63Y118.BX), 1 path
</twPathRptBanner><twPathRpt anchorID="15"><twConstPath anchorID="16" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>1.166</twSlack><twSrc BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0</twSrc><twDest BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twDest><twTotPathDel>1.166</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0</twSrc><twDest BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X63Y118.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">fpga_0_clk_1_sys_clk_pin_IBUF</twSrcClk><twPathDel><twSite>SLICE_X63Y118.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.470</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;1&gt;</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X63Y118.BX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.603</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;0&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X63Y118.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.093</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;1&gt;</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_1</twBEL></twPathDel><twLogDel>0.563</twLogDel><twRouteDel>0.603</twRouteDel><twTotDel>1.166</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_0_clk_1_sys_clk_pin_IBUF</twDestClk><twPctLog>48.3</twPctLog><twPctRoute>51.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti (SLICE_X60Y118.BY), 1 path
</twPathRptBanner><twPathRpt anchorID="17"><twConstPath anchorID="18" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>1.277</twSlack><twSrc BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twSrc><twDest BELType="FF">Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti</twDest><twTotPathDel>1.275</twTotPathDel><twClkSkew dest = "0.001" src = "0.003">0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17"><twSrc BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twSrc><twDest BELType='FF'>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti</twDest><twLogLvls>0</twLogLvls><twSrcSite>SLICE_X62Y119.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">fpga_0_clk_1_sys_clk_pin_IBUF</twSrcClk><twPathDel><twSite>SLICE_X62Y119.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.522</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;2&gt;</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X60Y118.BY</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.601</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay&lt;2&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X60Y118.CLK</twSite><twDelType>Tckdi</twDelType><twDelInfo twEdge="twFalling">0.152</twDelInfo><twComp>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti</twComp><twBEL>Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/rsti</twBEL></twPathDel><twLogDel>0.674</twLogDel><twRouteDel>0.601</twRouteDel><twTotDel>1.275</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">fpga_0_clk_1_sys_clk_pin_IBUF</twDestClk><twPctLog>52.9</twPctLog><twPctRoute>47.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="19"><twPinLimitBanner>Component Switching Limit Checks: TS_sys_clk_pin = PERIOD TIMEGRP &quot;sys_clk_pin&quot; 50 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="20" type="MINLOWPULSE" name="Tdcmpw_CLKIN_50_100" slack="14.000" period="20.000" constraintValue="10.000" deviceLimit="3.000" physResource="Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN" logResource="Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN" locationPin="DCM_X1Y3.CLKIN" clockNet="fpga_0_clk_1_sys_clk_pin_IBUF"/><twPinLimit anchorID="21" type="MINHIGHPULSE" name="Tdcmpw_CLKIN_50_100" slack="14.000" period="20.000" constraintValue="10.000" deviceLimit="3.000" physResource="Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN" logResource="Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN" locationPin="DCM_X1Y3.CLKIN" clockNet="fpga_0_clk_1_sys_clk_pin_IBUF"/><twPinLimit anchorID="22" type="MINPERIOD" name="Tdcmpc" slack="15.834" period="20.000" constraintValue="20.000" deviceLimit="4.166" freqLimit="240.038" physResource="Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN" logResource="Inst_system/clock_generator_0/clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST/CLKIN" locationPin="DCM_X1Y3.CLKIN" clockNet="fpga_0_clk_1_sys_clk_pin_IBUF"/></twPinLimitRpt></twConst><twConst anchorID="23" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;" ScopeName="">TS_Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0 = PERIOD         TIMEGRP         &quot;Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0&quot;         TS_sys_clk_pin HIGH 50%;</twConstName><twItemCnt>3593254</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>18413</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>19.958</twMinPer></twConstHead><twPathRptBanner iPaths="109502" iCriticalPaths="0" sType="EndPoint">Paths for end point Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A (RAMB16_X1Y4.ADDRA7), 109502 paths
</twPathRptBanner><twPathRpt anchorID="24"><twConstPath anchorID="25" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>0.042</twSlack><twSrc BELType="FF">Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_0</twSrc><twDest BELType="RAM">Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A</twDest><twTotPathDel>19.958</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_0</twSrc><twDest BELType='RAM'>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A</twDest><twLogLvls>13</twLogLvls><twSrcSite>SLICE_X60Y55.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime 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BELType="FF">Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1</twSrc><twDest BELType="RAM">Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A</twDest><twTotPathDel>19.938</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1</twSrc><twDest BELType='RAM'>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3_init.ram/dpram.dp4x4.ram.A</twDest><twLogLvls>13</twLogLvls><twSrcSite>SLICE_X57Y57.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Inst_system/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X57Y57.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo 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Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A (RAMB16_X1Y3.ENA), 86408 paths
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BELType="RAM">Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A</twDest><twTotPathDel>19.912</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>20.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="18"><twSrc BELType='FF'>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1</twSrc><twDest BELType='RAM'>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A</twDest><twLogLvls>13</twLogLvls><twSrcSite>SLICE_X57Y57.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">Inst_system/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X57Y57.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.587</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1</twBEL></twPathDel><twPathDel><twSite>SLICE_X48Y58.G1</twSite><twDelType>net</twDelType><twFanCnt>9</twFanCnt><twDelInfo twEdge="twRising">1.772</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/slv_reg0_13_1</twComp></twPathDel><twPathDel><twSite>SLICE_X48Y58.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>Inst_system/graph_acc_0/N1042</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard&lt;7&gt;_8_cmp_eq00031</twBEL></twPathDel><twPathDel><twSite>SLICE_X59Y65.F4</twSite><twDelType>net</twDelType><twFanCnt>41</twFanCnt><twDelInfo twEdge="twRising">1.284</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard&lt;7&gt;_8_cmp_eq0003</twComp></twPathDel><twPathDel><twSite>SLICE_X59Y65.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>Inst_system/graph_acc_0/N1138</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard&lt;3&gt;_8_mux0003&lt;0&gt;2_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X45Y62.G3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.959</twDelInfo><twComp>Inst_system/graph_acc_0/N1138</twComp></twPathDel><twPathDel><twSite>SLICE_X45Y62.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.704</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard&lt;3&gt;&lt;8&gt;&lt;3&gt;</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard&lt;3&gt;_8_mux0003&lt;0&gt;2</twBEL></twPathDel><twPathDel><twSite>SLICE_X44Y62.F1</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.468</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/N420</twComp></twPathDel><twPathDel><twSite>SLICE_X44Y62.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard&lt;3&gt;&lt;8&gt;&lt;0&gt;</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard&lt;3&gt;_8_mux0003&lt;0&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X39Y59.F2</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.943</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard&lt;3&gt;&lt;8&gt;&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X39Y59.F5</twSite><twDelType>Tif5</twDelType><twDelInfo twEdge="twRising">0.875</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f51</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_158</twBEL><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f5_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X39Y58.FXINB</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_14_f51</twComp></twPathDel><twPathDel><twSite>SLICE_X39Y58.FX</twSite><twDelType>Tinbfx</twDelType><twDelInfo twEdge="twRising">0.463</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f56</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f6_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X38Y59.FXINB</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_12_f61</twComp></twPathDel><twPathDel><twSite>SLICE_X38Y59.FX</twSite><twDelType>Tinbfx</twDelType><twDelInfo twEdge="twRising">0.364</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_13_f55</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f7_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X39Y57.FXINB</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_10_f71</twComp></twPathDel><twPathDel><twSite>SLICE_X39Y57.Y</twSite><twDelType>Tif6y</twDelType><twDelInfo twEdge="twRising">0.521</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f81</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f8_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y36.G4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.012</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_8_f81</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y36.F5</twSite><twDelType>Tif5</twDelType><twDelInfo twEdge="twRising">0.875</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016&lt;0&gt;</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_5</twBEL><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f5</twBEL></twPathDel><twPathDel><twSite>SLICE_X71Y36.FXINA</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.000</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_3_f5</twComp></twPathDel><twPathDel><twSite>SLICE_X71Y36.Y</twSite><twDelType>Tif6y</twDelType><twDelInfo twEdge="twRising">0.521</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016&lt;0&gt;</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Mmux_gameboard_mux0016_2_f6</twBEL></twPathDel><twPathDel><twSite>SLICE_X72Y29.G4</twSite><twDelType>net</twDelType><twFanCnt>7</twFanCnt><twDelInfo twEdge="twRising">0.920</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/gameboard_mux0016&lt;0&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X72Y29.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe&lt;1&gt;</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr&lt;12&gt;_SW0</twBEL></twPathDel><twPathDel><twSite>SLICE_X72Y29.F3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.023</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr&lt;12&gt;_SW0/O</twComp></twPathDel><twPathDel><twSite>SLICE_X72Y29.X</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe&lt;1&gt;</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr&lt;12&gt;</twBEL></twPathDel><twPathDel><twSite>SLICE_X72Y28.G2</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twRising">0.146</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/bram_sprite_addr&lt;12&gt;</twComp></twPathDel><twPathDel><twSite>SLICE_X72Y28.Y</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.759</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq0000</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq00001</twBEL></twPathDel><twPathDel><twSite>RAMB16_X1Y3.ENA</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.206</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/bindec_a.bindec_inst_a/ENOUT_2_cmp_eq0000</twComp></twPathDel><twPathDel><twSite>RAMB16_X1Y3.CLKA</twSite><twDelType>Tbeck</twDelType><twDelInfo twEdge="twRising">0.770</twDelInfo><twComp>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram</twComp><twBEL>Inst_system/graph_acc_0/graph_acc_0/USER_LOGIC_I/Sprite/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_init.ram/dpram.dp9x9.ram.A</twBEL></twPathDel><twLogDel>10.179</twLogDel><twRouteDel>9.733</twRouteDel><twTotDel>19.912</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">Inst_system/clk_50_0000MHz</twDestClk><twPctLog>51.1</twPctLog><twPctRoute>48.9</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0 = PERIOD
        TIMEGRP
        &quot;Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0&quot;
        TS_sys_clk_pin HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point Inst_system/RS232_PORT/RS232_PORT/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/Mshreg_Dout_5_0 (SLICE_X32Y30.BX), 1 path
</twPathRptBanner><twPathRpt anchorID="42"><twConstPath anchorID="43" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.676</twSlack><twSrc BELType="FF">Inst_system/RS232_PORT/RS232_PORT/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_29</twSrc><twDest BELType="FF">Inst_system/RS232_PORT/RS232_PORT/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/Mshreg_Dout_5_0</twDest><twTotPathDel>0.677</twTotPathDel><twClkSkew dest = "0.018" src = "0.017">-0.001</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>Inst_system/RS232_PORT/RS232_PORT/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_29</twSrc><twDest BELType='FF'>Inst_system/RS232_PORT/RS232_PORT/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/Mshreg_Dout_5_0</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X33Y33.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">Inst_system/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X33Y33.XQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.473</twDelInfo><twComp>Inst_system/RS232_PORT/RS232_PORT/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg&lt;29&gt;</twComp><twBEL>Inst_system/RS232_PORT/RS232_PORT/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg_29</twBEL></twPathDel><twPathDel><twSite>SLICE_X32Y30.BX</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twFalling">0.353</twDelInfo><twComp>Inst_system/RS232_PORT/RS232_PORT/PLBV46_I/I_SLAVE_ATTACHMENT/plb_wrdbus_reg&lt;29&gt;</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X32Y30.CLK</twSite><twDelType>Tdh</twDelType><twDelInfo twEdge="twFalling">-0.149</twDelInfo><twComp>Inst_system/RS232_PORT/RS232_PORT/UARTLITE_CORE_I/UARTLITE_TX_I/fifo_DOut&lt;5&gt;</twComp><twBEL>Inst_system/RS232_PORT/RS232_PORT/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/Mshreg_Dout_5_0</twBEL></twPathDel><twLogDel>0.324</twLogDel><twRouteDel>0.353</twRouteDel><twTotDel>0.677</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">Inst_system/clk_50_0000MHz</twDestClk><twPctLog>47.9</twPctLog><twPctRoute>52.1</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/PC_OF_Buffer (SLICE_X20Y74.BX), 1 path
</twPathRptBanner><twPathRpt anchorID="44"><twConstPath anchorID="45" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.718</twSlack><twSrc BELType="FF">Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/Set_DFF.PC_IF_DFF</twSrc><twDest BELType="FF">Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/PC_OF_Buffer</twDest><twTotPathDel>0.716</twTotPathDel><twClkSkew dest = "0.040" src = "0.042">0.002</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/Set_DFF.PC_IF_DFF</twSrc><twDest BELType='FF'>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/PC_OF_Buffer</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X21Y76.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">Inst_system/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X21Y76.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.470</twDelInfo><twComp>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/pc_I</twComp><twBEL>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/Set_DFF.PC_IF_DFF</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y74.BX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.395</twDelInfo><twComp>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/pc_I</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X20Y74.CLK</twSite><twDelType>Tdh</twDelType><twDelInfo twEdge="twFalling">-0.149</twDelInfo><twComp>Inst_system/microblaze_0/microblaze_0/PC_EX_i&lt;27&gt;</twComp><twBEL>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[27].PC_Bit_I/PC_OF_Buffer</twBEL></twPathDel><twLogDel>0.321</twLogDel><twRouteDel>0.395</twRouteDel><twTotDel>0.716</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">Inst_system/clk_50_0000MHz</twDestClk><twPctLog>44.8</twPctLog><twPctRoute>55.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/PC_OF_Buffer (SLICE_X22Y86.BX), 1 path
</twPathRptBanner><twPathRpt anchorID="46"><twConstPath anchorID="47" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.730</twSlack><twSrc BELType="FF">Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/Set_DFF.PC_IF_DFF</twSrc><twDest BELType="FF">Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/PC_OF_Buffer</twDest><twTotPathDel>0.742</twTotPathDel><twClkSkew dest = "0.047" src = "0.035">-0.012</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16"><twSrc BELType='FF'>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/Set_DFF.PC_IF_DFF</twSrc><twDest BELType='FF'>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/PC_OF_Buffer</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X25Y84.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="20.000">Inst_system/clk_50_0000MHz</twSrcClk><twPathDel><twSite>SLICE_X25Y84.YQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.470</twDelInfo><twComp>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/pc_I</twComp><twBEL>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/Set_DFF.PC_IF_DFF</twBEL></twPathDel><twPathDel><twSite>SLICE_X22Y86.BX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.421</twDelInfo><twComp>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/pc_I</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X22Y86.CLK</twSite><twDelType>Tdh</twDelType><twDelInfo twEdge="twFalling">-0.149</twDelInfo><twComp>Inst_system/microblaze_0/microblaze_0/PC_EX_i&lt;11&gt;</twComp><twBEL>Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/PC_Module_I/Using_FPGA.PC_GEN[11].PC_Bit_I/PC_OF_Buffer</twBEL></twPathDel><twLogDel>0.321</twLogDel><twRouteDel>0.421</twRouteDel><twTotDel>0.742</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="20.000">Inst_system/clk_50_0000MHz</twDestClk><twPctLog>43.3</twPctLog><twPctRoute>56.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="48"><twPinLimitBanner>Component Switching Limit Checks: TS_Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0 = PERIOD
        TIMEGRP
        &quot;Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0&quot;
        TS_sys_clk_pin HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="49" type="MINPERIOD" name="Tmsper_P" slack="15.833" period="20.000" constraintValue="20.000" deviceLimit="4.167" freqLimit="239.981" physResource="Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_AD/CLK" logResource="Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_AD/CLK" locationPin="MULT18X18_X0Y8.CLK" clockNet="Inst_system/clk_50_0000MHz"/><twPinLimit anchorID="50" type="MINPERIOD" name="Tmsper_P" slack="15.833" period="20.000" constraintValue="20.000" deviceLimit="4.167" freqLimit="239.981" physResource="Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_BC/CLK" logResource="Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_BC/CLK" locationPin="MULT18X18_X0Y6.CLK" clockNet="Inst_system/clk_50_0000MHz"/><twPinLimit anchorID="51" type="MINPERIOD" name="Tmsper_P" slack="15.833" period="20.000" constraintValue="20.000" deviceLimit="4.167" freqLimit="239.981" physResource="Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_BD/CLK" logResource="Inst_system/microblaze_0/microblaze_0/Area.Data_Flow_I/mul_unit_I/Use_HW_MUL.Using_MULT18x18_Architecture.Using_FPGA.MULT18x18S_BD/CLK" locationPin="MULT18X18_X0Y7.CLK" clockNet="Inst_system/clk_50_0000MHz"/></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="52"><twConstRollup name="TS_sys_clk_pin" fullName="TS_sys_clk_pin = PERIOD TIMEGRP &quot;sys_clk_pin&quot; 50 MHz HIGH 50%;" type="origin" depth="0" requirement="20.000" prefType="period" actual="6.000" actualRollup="19.958" errors="0" errorRollup="0" items="3" itemsRollup="3593254"/><twConstRollup name="TS_Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0" fullName="TS_Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0 = PERIOD         TIMEGRP         &quot;Inst_system_clock_generator_0_clock_generator_0_SIG_DCM0_CLK0&quot;         TS_sys_clk_pin HIGH 50%;" type="child" depth="1" requirement="20.000" prefType="period" actual="19.958" actualRollup="N/A" errors="0" errorRollup="0" items="3593254" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="53">0</twUnmetConstCnt><twDataSheet anchorID="54" twNameLen="24"><twClk2SUList anchorID="55" twDestWidth="24"><twDest>fpga_0_clk_1_sys_clk_pin</twDest><twClk2SU><twSrc>fpga_0_clk_1_sys_clk_pin</twSrc><twRiseRise>19.958</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="56"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>3593257</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>44088</twConnCnt></twConstCov><twStats anchorID="57"><twMinPer>19.958</twMinPer><twFootnote number="1" /><twMaxFreq>50.105</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation  number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Tue Oct 04 11:50:50 2011 </twTimestamp></twFoot><twClientInfo anchorID="58"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 184 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
