
<EDKSYSTEM EDKVERSION="12.2" EDWVERSION="1.2" TIMESTAMP="Tue Oct 04 13:06:35 2011">

  <SYSTEMINFO ARCH="spartan3e" DEVICE="xc3s1200e" PACKAGE="fg320" PART="xc3s1200efg320-4" SOURCE="C:/Temp/Bomberman/" SPEEDGRADE="-4"/>

  <EXTERNALPORTS>
    <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MHS_INDEX="0" MSB="0" NAME="fpga_0_LEDs_8Bit_GPIO_IO_O_pin" RIGHT="7" SIGNAME="fpga_0_LEDs_8Bit_GPIO_IO_O_pin"/>
    <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="11" MHS_INDEX="1" MSB="0" NAME="fpga_0_LED_7SEGMENT_GPIO_IO_O_pin" RIGHT="11" SIGNAME="fpga_0_LED_7SEGMENT_GPIO_IO_O_pin"/>
    <PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MHS_INDEX="2" MSB="0" NAME="fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin" RIGHT="2" SIGNAME="fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin"/>
    <PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MHS_INDEX="3" MSB="0" NAME="fpga_0_Switches_8Bit_GPIO_IO_I_pin" RIGHT="7" SIGNAME="fpga_0_Switches_8Bit_GPIO_IO_I_pin"/>
    <PORT DIR="I" MHS_INDEX="4" NAME="fpga_0_RS232_PORT_RX_pin" SIGNAME="fpga_0_RS232_PORT_RX_pin"/>
    <PORT DIR="O" MHS_INDEX="5" NAME="fpga_0_RS232_PORT_TX_pin" SIGNAME="fpga_0_RS232_PORT_TX_pin"/>
    <PORT DIR="O" ENDIAN="BIG" LEFT="9" LSB="31" MHS_INDEX="6" MSB="9" NAME="fpga_0_Micron_RAM_Mem_A_pin" RIGHT="31" SIGNAME="fpga_0_Micron_RAM_Mem_A_pin_vslice_9_31_concat"/>
    <PORT DIR="O" MHS_INDEX="7" NAME="fpga_0_Micron_RAM_Mem_OEN_pin" SIGNAME="fpga_0_Micron_RAM_Mem_OEN_pin"/>
    <PORT DIR="O" MHS_INDEX="8" NAME="fpga_0_Micron_RAM_Mem_WEN_pin" SIGNAME="fpga_0_Micron_RAM_Mem_WEN_pin"/>
    <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MHS_INDEX="9" MSB="0" NAME="fpga_0_Micron_RAM_Mem_BEN_pin" RIGHT="1" SIGNAME="fpga_0_Micron_RAM_Mem_BEN_pin"/>
    <PORT DIR="IO" ENDIAN="BIG" LEFT="0" LSB="15" MHS_INDEX="10" MSB="0" NAME="fpga_0_Micron_RAM_Mem_DQ_pin" RIGHT="15" SIGNAME="fpga_0_Micron_RAM_Mem_DQ_pin"/>
    <PORT CLKFREQUENCY="50000000" DIR="I" MHS_INDEX="11" NAME="fpga_0_clk_1_sys_clk_pin" SIGIS="CLK" SIGNAME="dcm_clk_s"/>
    <PORT DIR="I" MHS_INDEX="12" NAME="fpga_0_rst_1_sys_rst_pin" RSTPOLARITY="1" SIGIS="RST" SIGNAME="sys_rst_s"/>
    <PORT DIR="IO" MHS_INDEX="13" NAME="xps_ps2_0_PS2_1_DATA" SIGNAME="xps_ps2_0_PS2_1_DATA"/>
    <PORT DIR="IO" MHS_INDEX="14" NAME="xps_ps2_0_PS2_1_CLK" SIGNAME="xps_ps2_0_PS2_1_CLK"/>
    <PORT DIR="O" MHS_INDEX="15" NAME="graph_acc_0_HS_pin" SIGNAME="graph_acc_0_HS"/>
    <PORT DIR="O" MHS_INDEX="16" NAME="graph_acc_0_VS_pin" SIGNAME="graph_acc_0_VS"/>
    <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MHS_INDEX="17" MSB="0" NAME="graph_acc_0_VGA_rgb_pin" RIGHT="7" SIGNAME="graph_acc_0_VGA_rgb"/>
  </EXTERNALPORTS>

  <MODULES>
    <MODULE HWVERSION="7.30.b" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="0" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
      <DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v7_30_b/doc/microblaze.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="50000000"/>
        <PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan3e"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="6" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="1">
          <DESCRIPTION>Select implementation to optimize area (with lower instruction throughput)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="8" NAME="C_INTERCONNECT" TYPE="integer" VALUE="1">
          <DESCRIPTION>Select Bus Interfaces</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="10" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="11" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="12" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="13" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="14" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="15" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="16" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_D_PLB" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="18" NAME="C_D_LMB" TYPE="integer" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_I_PLB" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="20" NAME="C_I_LMB" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="21" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Additional Machine Status Register Instructions</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="22" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Pattern Comparator</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="23" NAME="C_USE_BARREL" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Barrel Shifter</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="24" NAME="C_USE_DIV" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Integer Divider</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="25" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Integer Multiplier</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="26" NAME="C_USE_FPU" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Floating Point Unit</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="27" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Unaligned Data Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="28" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Illegal Instruction Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="29" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Instruction-side PLB Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="30" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Data-side PLB Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="31" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Integer Divide Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="32" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Floating Point Unit Exceptions</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="33" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable FSL Exception</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="34" NAME="C_PVR" TYPE="integer" VALUE="0">
          <DESCRIPTION>Specifies Processor Version Register</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="35" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00">
          <DESCRIPTION>Specify USER1 Bits in Processor Version Register</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="36" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Specify USER2 Bits in Processor Version Registers</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="37" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable MicroBlaze Debug Module Interface</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="38" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of PC Breakpoints </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="39" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="0">
          <DESCRIPTION>Number of Read Address Watchpoints </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="40" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="0">
          <DESCRIPTION>Number of Write Address Watchpoints </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="41" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Sense Interrupt on Edge vs. Level </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="42" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1">
          <DESCRIPTION>Sense Interrupt on Rising vs. Falling Edge </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="43" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Specify Reset Value for Select MSR Bits</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="44" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="0">
          <DESCRIPTION>&lt;qt&gt;Generate Illegal Instruction Exception for NULL Instruction&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="45" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0">
          <DESCRIPTION>Number of FSL Links </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="46" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/>
        <PARAMETER MPD_INDEX="47" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Additional FSL Instructions</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="NONE" MPD_INDEX="48" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>I-Cache Base Address </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="NONE" MPD_INDEX="49" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0x3FFFFFFF">
          <DESCRIPTION>I-Cache High Address </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="50" NAME="C_USE_ICACHE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Instruction Cache </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="51" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable I-Cache Writes</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="52" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="53" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="8192">
          <DESCRIPTION>Size of the I-Cache in Bytes</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="54" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="55" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="4">
          <DESCRIPTION>Instruction Cache Line Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="56" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="0">
          <DESCRIPTION>Use Cache Links for All I-Cache Memory Accesses </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="57" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="58" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0">
          <DESCRIPTION>Number of I-Cache Victims</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="59" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0">
          <DESCRIPTION>Number of I-Cache Streams</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="NONE" MPD_INDEX="60" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>D-Cache Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="NONE" MPD_INDEX="61" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0x3FFFFFFF">
          <DESCRIPTION>D-Cache High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="62" NAME="C_USE_DCACHE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Data Cache</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="63" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable D-Cache Writes</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="64" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="65" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="8192">
          <DESCRIPTION>Size of D-Cache in Bytes</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="66" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="67" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="4">
          <DESCRIPTION>Data Cache Line Length</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="68" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="0">
          <DESCRIPTION>Use Cache Links for All D-Cache Memory Accesses </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="69" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/>
        <PARAMETER MPD_INDEX="70" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Write-back Storage Policy</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="71" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0">
          <DESCRIPTION>Number of D-Cache Victims</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="72" NAME="C_USE_MMU" TYPE="integer" VALUE="0">
          <DESCRIPTION>Memory Management</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="73" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="4">
          <DESCRIPTION>Data Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="74" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2">
          <DESCRIPTION>Instruction Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="75" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3">
          <DESCRIPTION>Enable Access to Memory Management Special Registers</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="76" NAME="C_MMU_ZONES" TYPE="integer" VALUE="16">
          <DESCRIPTION>Number of Memory Protection Zones</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="77" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="78" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="79" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="1"/>
        <PARAMETER MPD_INDEX="80" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Enable Branch Target Cache</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="81" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Branch Target Cache Size</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="2" MSB="0" NAME="MB_RESET" RIGHT="0" SIGIS="RST" SIGNAME="mb_reset"/>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="3" MSB="0" NAME="INTERRUPT" RIGHT="0" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="microblaze_0_INTERRUPT"/>
        <PORT BUS="DPLB:IPLB:DLMB:ILMB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="DLMB:ILMB" DEF_SIGNAME="dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="dlmb_LMB_Rst"/>
        <PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/>
        <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/>
        <PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_Ready" DIR="I" MPD_INDEX="9" NAME="IREADY" SIGNAME="ilmb_LMB_Ready"/>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_Wait" DIR="I" MPD_INDEX="10" NAME="IWAIT" SIGNAME="ilmb_LMB_Wait"/>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="ilmb_M_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="12" NAME="IFETCH" SIGNAME="ilmb_M_ReadStrobe"/>
        <PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="13" NAME="I_AS" SIGNAME="ilmb_M_AddrStrobe"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_ABort" DIR="O" MPD_INDEX="14" NAME="IPLB_M_ABort" SIGNAME="mb_plb_M_ABort"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="15" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="17" MSB="0" NAME="IPLB_M_BE" RIGHT="3" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_busLock" DIR="O" MPD_INDEX="18" NAME="IPLB_M_busLock" SIGNAME="mb_plb_M_busLock"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_lockErr" DIR="O" MPD_INDEX="19" NAME="IPLB_M_lockErr" SIGNAME="mb_plb_M_lockErr"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="20" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_priority" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="21" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:1]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_rdBurst" DIR="O" MPD_INDEX="22" NAME="IPLB_M_rdBurst" SIGNAME="mb_plb_M_rdBurst"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_request" DIR="O" MPD_INDEX="23" NAME="IPLB_M_request" SIGNAME="mb_plb_M_request"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_RNW" DIR="O" MPD_INDEX="24" NAME="IPLB_M_RNW" SIGNAME="mb_plb_M_RNW"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="mb_plb_M_size" VECFORMULA="[0:3]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="26" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="mb_plb_M_type" VECFORMULA="[0:2]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_wrBurst" DIR="O" MPD_INDEX="28" NAME="IPLB_M_wrBurst" SIGNAME="mb_plb_M_wrBurst"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_M_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="29" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="31" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="I" MPD_INDEX="30" NAME="IPLB_MBusy" SIGNAME="mb_plb_PLB_MBusy"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="I" MPD_INDEX="31" NAME="IPLB_MRdErr" SIGNAME="mb_plb_PLB_MRdErr"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="I" MPD_INDEX="32" NAME="IPLB_MWrErr" SIGNAME="mb_plb_PLB_MWrErr"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="I" MPD_INDEX="33" NAME="IPLB_MIRQ" SIGNAME="mb_plb_PLB_MIRQ"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="I" MPD_INDEX="34" NAME="IPLB_MWrBTerm" SIGNAME="mb_plb_PLB_MWrBTerm"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="I" MPD_INDEX="35" NAME="IPLB_MWrDAck" SIGNAME="mb_plb_PLB_MWrDAck"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="I" MPD_INDEX="36" NAME="IPLB_MAddrAck" SIGNAME="mb_plb_PLB_MAddrAck"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="I" MPD_INDEX="37" NAME="IPLB_MRdBTerm" SIGNAME="mb_plb_PLB_MRdBTerm"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="I" MPD_INDEX="38" NAME="IPLB_MRdDAck" SIGNAME="mb_plb_PLB_MRdDAck"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="39" MSB="0" NAME="IPLB_MRdDBus" RIGHT="31" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="I" MPD_INDEX="41" NAME="IPLB_MRearbitrate" SIGNAME="mb_plb_PLB_MRearbitrate"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="42" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:1]"/>
        <PORT BUS="IPLB" DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="I" MPD_INDEX="43" NAME="IPLB_MTimeout" SIGNAME="mb_plb_PLB_MTimeout"/>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="44" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="dlmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_Ready" DIR="I" MPD_INDEX="45" NAME="DREADY" SIGNAME="dlmb_LMB_Ready"/>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_Wait" DIR="I" MPD_INDEX="46" NAME="DWAIT" SIGNAME="dlmb_LMB_Wait"/>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="dlmb_M_DBus" VECFORMULA="[0:31]"/>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="dlmb_M_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="49" NAME="D_AS" SIGNAME="dlmb_M_AddrStrobe"/>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="50" NAME="READ_STROBE" SIGNAME="dlmb_M_ReadStrobe"/>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="51" NAME="WRITE_STROBE" SIGNAME="dlmb_M_WriteStrobe"/>
        <PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="52" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="dlmb_M_BE" VECFORMULA="[0:3]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_ABort" DIR="O" MPD_INDEX="53" NAME="DPLB_M_ABort" SIGNAME="mb_plb_M_ABort"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="54" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="55" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="56" MSB="0" NAME="DPLB_M_BE" RIGHT="3" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_busLock" DIR="O" MPD_INDEX="57" NAME="DPLB_M_busLock" SIGNAME="mb_plb_M_busLock"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_lockErr" DIR="O" MPD_INDEX="58" NAME="DPLB_M_lockErr" SIGNAME="mb_plb_M_lockErr"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="59" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_priority" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="60" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:1]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_rdBurst" DIR="O" MPD_INDEX="61" NAME="DPLB_M_rdBurst" SIGNAME="mb_plb_M_rdBurst"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_request" DIR="O" MPD_INDEX="62" NAME="DPLB_M_request" SIGNAME="mb_plb_M_request"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_RNW" DIR="O" MPD_INDEX="63" NAME="DPLB_M_RNW" SIGNAME="mb_plb_M_RNW"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="64" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="mb_plb_M_size" VECFORMULA="[0:3]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="65" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="66" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="mb_plb_M_type" VECFORMULA="[0:2]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_wrBurst" DIR="O" MPD_INDEX="67" NAME="DPLB_M_wrBurst" SIGNAME="mb_plb_M_wrBurst"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_M_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="68" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="31" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="I" MPD_INDEX="69" NAME="DPLB_MBusy" SIGNAME="mb_plb_PLB_MBusy"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="I" MPD_INDEX="70" NAME="DPLB_MRdErr" SIGNAME="mb_plb_PLB_MRdErr"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="I" MPD_INDEX="71" NAME="DPLB_MWrErr" SIGNAME="mb_plb_PLB_MWrErr"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="I" MPD_INDEX="72" NAME="DPLB_MIRQ" SIGNAME="mb_plb_PLB_MIRQ"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="I" MPD_INDEX="73" NAME="DPLB_MWrBTerm" SIGNAME="mb_plb_PLB_MWrBTerm"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="I" MPD_INDEX="74" NAME="DPLB_MWrDAck" SIGNAME="mb_plb_PLB_MWrDAck"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="I" MPD_INDEX="75" NAME="DPLB_MAddrAck" SIGNAME="mb_plb_PLB_MAddrAck"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="I" MPD_INDEX="76" NAME="DPLB_MRdBTerm" SIGNAME="mb_plb_PLB_MRdBTerm"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="I" MPD_INDEX="77" NAME="DPLB_MRdDAck" SIGNAME="mb_plb_PLB_MRdDAck"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="78" MSB="0" NAME="DPLB_MRdDBus" RIGHT="31" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="79" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="I" MPD_INDEX="80" NAME="DPLB_MRearbitrate" SIGNAME="mb_plb_PLB_MRearbitrate"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="81" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:1]"/>
        <PORT BUS="DPLB" DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="I" MPD_INDEX="82" NAME="DPLB_MTimeout" SIGNAME="mb_plb_PLB_MTimeout"/>
        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Clk" DIR="I" MPD_INDEX="83" NAME="DBG_CLK" SIGNAME="microblaze_0_mdm_bus_Dbg_Clk"/>
        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDI" DIR="I" MPD_INDEX="84" NAME="DBG_TDI" SIGNAME="microblaze_0_mdm_bus_Dbg_TDI"/>
        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDO" DIR="O" MPD_INDEX="85" NAME="DBG_TDO" SIGNAME="microblaze_0_mdm_bus_Dbg_TDO"/>
        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="86" MSB="0" NAME="DBG_REG_EN" RIGHT="4" SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" VECFORMULA="[0:4]"/>
        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Shift" DIR="I" MPD_INDEX="87" NAME="DBG_SHIFT" SIGNAME="microblaze_0_mdm_bus_Dbg_Shift"/>
        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Capture" DIR="I" MPD_INDEX="88" NAME="DBG_CAPTURE" SIGNAME="microblaze_0_mdm_bus_Dbg_Capture"/>
        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Update" DIR="I" MPD_INDEX="89" NAME="DBG_UPDATE" SIGNAME="microblaze_0_mdm_bus_Dbg_Update"/>
        <PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_mdm_bus_Debug_Rst" DIR="I" MPD_INDEX="90" NAME="DEBUG_RST" SIGIS="RST" SIGNAME="microblaze_0_mdm_bus_Debug_Rst"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="91" MSB="0" NAME="Trace_Instruction" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="92" NAME="Trace_Valid_Instr" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="93" MSB="0" NAME="Trace_PC" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Trace_Reg_Write" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="95" MSB="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="14" MPD_INDEX="96" MSB="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGNAME="__NOC__" VECFORMULA="[0:14]"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="97" MSB="0" NAME="Trace_PID_Reg" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="98" MSB="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="Trace_Exception_Taken" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="100" MSB="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Trace_Jump_Taken" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="Trace_Delay_Slot" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="103" MSB="0" NAME="Trace_Data_Address" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Trace_Data_Access" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Trace_Data_Read" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Trace_Data_Write" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="107" MSB="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="108" MSB="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="Trace_DCache_Req" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="Trace_DCache_Hit" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Trace_DCache_Rdy" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Trace_DCache_Read" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Trace_ICache_Req" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Trace_ICache_Hit" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="115" NAME="Trace_ICache_Rdy" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="116" NAME="Trace_OF_PipeRun" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="Trace_EX_PipeRun" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="118" NAME="Trace_MEM_PipeRun" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Trace_MB_Halted" SIGNAME="__NOC__"/>
        <PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Trace_Jump_Hit" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="FSL0_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="FSL0_S_READ" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="123" MSB="0" NAME="FSL0_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
        <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="124" NAME="FSL0_S_CONTROL" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="125" NAME="FSL0_S_EXISTS" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="FSL0_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="FSL0_M_WRITE" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="128" MSB="0" NAME="FSL0_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
        <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="129" NAME="FSL0_M_CONTROL" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="130" NAME="FSL0_M_FULL" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="131" NAME="FSL1_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="132" NAME="FSL1_S_READ" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="133" MSB="0" NAME="FSL1_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
        <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="134" NAME="FSL1_S_CONTROL" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="135" NAME="FSL1_S_EXISTS" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="136" NAME="FSL1_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="FSL1_M_WRITE" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="138" MSB="0" NAME="FSL1_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
        <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="FSL1_M_CONTROL" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="140" NAME="FSL1_M_FULL" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="FSL2_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="FSL2_S_READ" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="143" MSB="0" NAME="FSL2_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
        <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="FSL2_S_CONTROL" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="145" NAME="FSL2_S_EXISTS" SIGNAME="__NOC__"/>
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        <PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="147" NAME="FSL2_M_WRITE" SIGNAME="__NOC__"/>
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          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="3231711232" BASENAME="C_BASEADDR" BASEVALUE="0xc0a00000" HIGHDECIMAL="3231776767" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xc0a0ffff" INSTANCE="my_timer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="3252682752" BASENAME="C_BASEADDR" BASEVALUE="0xc1e00000" HIGHDECIMAL="3252748287" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xc1e0ffff" INSTANCE="graph_acc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
          </ACCESSROUTE>
        </MEMRANGE>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="dlmb_cntlr"/>
        <PERIPHERAL INSTANCE="ilmb_cntlr"/>
        <PERIPHERAL INSTANCE="LEDs_8Bit"/>
        <PERIPHERAL INSTANCE="LED_7SEGMENT"/>
        <PERIPHERAL INSTANCE="Push_Buttons_3Bit"/>
        <PERIPHERAL INSTANCE="Switches_8Bit"/>
        <PERIPHERAL INSTANCE="RS232_PORT"/>
        <PERIPHERAL INSTANCE="Micron_RAM"/>
        <PERIPHERAL INSTANCE="xps_timer_0"/>
        <PERIPHERAL INSTANCE="mdm_0"/>
        <PERIPHERAL INSTANCE="xps_ps2_0"/>
        <PERIPHERAL INSTANCE="xps_intc_0"/>
        <PERIPHERAL INSTANCE="my_timer_0"/>
        <PERIPHERAL INSTANCE="graph_acc_0"/>
      </PERIPHERALS>
      <INTERRUPTINFO TYPE="TARGET">
        <SOURCE INSTANCE="xps_intc_0" INTC_INDEX="0"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" HWVERSION="1.04.a" INSTANCE="mb_plb" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="plb_v46">
      <DESCRIPTION TYPE="SHORT">Processor Local Bus (PLB) 4.6</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plb_v46_v1_04_a/doc/plb_v46.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_PLBV46_NUM_MASTERS" TYPE="integer" VALUE="2">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_PLBV46_NUM_SLAVES" TYPE="integer" VALUE="12">
          <DESCRIPTION>Number of PLB Slaves</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PLBV46_MID_WIDTH" TYPE="integer" VALUE="1">
          <DESCRIPTION>PLB Master ID Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_PLBV46_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_PLBV46_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_DCR_INTFCE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Include DCR Interface and Error Registers</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="6" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0b1111111111">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="7" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0b0000000000">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_DCR_AWIDTH" TYPE="integer" VALUE="10">
          <DESCRIPTION>DCR Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_DCR_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>DCR Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
          <DESCRIPTION>External Reset Active High </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>IRQ Active State </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_NUM_CLK_PLB2OPB_REARB" TYPE="integer" VALUE="5">
          <DESCRIPTION>&lt;qt&gt;Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus&lt;/qt&gt;</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_ADDR_PIPELINING_TYPE" TYPE="integer" VALUE="1">
          <DESCRIPTION>Enable Address Pipelining Type</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_FAMILY" TYPE="string" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_P2P" TYPE="integer" VALUE="0">
          <DESCRIPTION>Optimize PLB for Point-to-point Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_ARB_TYPE" TYPE="integer" VALUE="0">
          <DESCRIPTION>Selects the Arbitration Scheme</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="50000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="PLB_Clk" RIGHT="0" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="SYS_Rst" RIGHT="0" SIGIS="RST" SIGNAME="sys_bus_reset"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_Rst" DIR="O" MPD_INDEX="2" NAME="PLB_Rst" SIGIS="RST" SIGNAME="mb_plb_PLB_Rst"/>
        <PORT DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="O" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="3" MSB="0" NAME="SPLB_Rst" RIGHT="11" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_MPLB_Rst" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="4" MSB="0" NAME="MPLB_Rst" RIGHT="1" SIGIS="RST" SIGNAME="mb_plb_MPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="5" NAME="PLB_dcrAck" SIGNAME="__NOC__"/>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="PLB_dcrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="9" MPD_INDEX="7" MSB="0" NAME="DCR_ABus" RIGHT="9" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_AWIDTH-1]"/>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="DCR_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="DCR_Read" SIGNAME="__NOC__"/>
        <PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="10" NAME="DCR_Write" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="mb_plb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="11" MSB="0" NAME="M_ABus" RIGHT="63" SIGNAME="mb_plb_M_ABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="12" MSB="0" NAME="M_UABus" RIGHT="63" SIGNAME="mb_plb_M_UABus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*32)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="13" MSB="0" NAME="M_BE" RIGHT="7" SIGNAME="mb_plb_M_BE" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_RNW" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="14" MSB="0" NAME="M_RNW" RIGHT="1" SIGNAME="mb_plb_M_RNW" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_abort" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="15" MSB="0" NAME="M_abort" RIGHT="1" SIGNAME="mb_plb_M_abort" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_busLock" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="16" MSB="0" NAME="M_busLock" RIGHT="1" SIGNAME="mb_plb_M_busLock" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="M_TAttribute" RIGHT="31" SIGNAME="mb_plb_M_TAttribute" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*16)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_lockErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="18" MSB="0" NAME="M_lockErr" RIGHT="1" SIGNAME="mb_plb_M_lockErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="19" MSB="0" NAME="M_MSize" RIGHT="3" SIGNAME="mb_plb_M_MSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_priority" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="20" MSB="0" NAME="M_priority" RIGHT="3" SIGNAME="mb_plb_M_priority" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_rdBurst" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="21" MSB="0" NAME="M_rdBurst" RIGHT="1" SIGNAME="mb_plb_M_rdBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_request" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="M_request" RIGHT="1" SIGNAME="mb_plb_M_request" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="23" MSB="0" NAME="M_size" RIGHT="7" SIGNAME="mb_plb_M_size" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="5" MPD_INDEX="24" MSB="0" NAME="M_type" RIGHT="5" SIGNAME="mb_plb_M_type" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*3)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_wrBurst" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="25" MSB="0" NAME="M_wrBurst" RIGHT="1" SIGNAME="mb_plb_M_wrBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_M_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="26" MSB="0" NAME="M_wrDBus" RIGHT="63" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="27" MSB="0" NAME="Sl_addrAck" RIGHT="11" SIGNAME="mb_plb_Sl_addrAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="23" MPD_INDEX="28" MSB="0" NAME="Sl_MRdErr" RIGHT="23" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="23" MPD_INDEX="29" MSB="0" NAME="Sl_MWrErr" RIGHT="23" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="I" ENDIAN="BIG" LEFT="0" LSB="23" MPD_INDEX="30" MSB="0" NAME="Sl_MBusy" RIGHT="23" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="31" MSB="0" NAME="Sl_rdBTerm" RIGHT="11" SIGNAME="mb_plb_Sl_rdBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="32" MSB="0" NAME="Sl_rdComp" RIGHT="11" SIGNAME="mb_plb_Sl_rdComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="33" MSB="0" NAME="Sl_rdDAck" RIGHT="11" SIGNAME="mb_plb_Sl_rdDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="383" MPD_INDEX="34" MSB="0" NAME="Sl_rdDBus" RIGHT="383" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="47" MPD_INDEX="35" MSB="0" NAME="Sl_rdWdAddr" RIGHT="47" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*4-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="I" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="36" MSB="0" NAME="Sl_rearbitrate" RIGHT="11" SIGNAME="mb_plb_Sl_rearbitrate" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_SSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="23" MPD_INDEX="37" MSB="0" NAME="Sl_SSize" RIGHT="23" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*2-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_wait" DIR="I" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="38" MSB="0" NAME="Sl_wait" RIGHT="11" SIGNAME="mb_plb_Sl_wait" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="39" MSB="0" NAME="Sl_wrBTerm" RIGHT="11" SIGNAME="mb_plb_Sl_wrBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="40" MSB="0" NAME="Sl_wrComp" RIGHT="11" SIGNAME="mb_plb_Sl_wrComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="41" MSB="0" NAME="Sl_wrDAck" RIGHT="11" SIGNAME="mb_plb_Sl_wrDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="I" ENDIAN="BIG" LEFT="0" LSB="23" MPD_INDEX="42" MSB="0" NAME="Sl_MIRQ" RIGHT="23" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="43" MSB="0" NAME="PLB_MIRQ" RIGHT="1" SIGNAME="mb_plb_PLB_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="44" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="45" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="46" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:(C_PLBV46_DWIDTH/8)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MAddrAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_MAddrAck" RIGHT="1" SIGNAME="mb_plb_PLB_MAddrAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MTimeout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="48" MSB="0" NAME="PLB_MTimeout" RIGHT="1" SIGNAME="mb_plb_PLB_MTimeout" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="49" MSB="0" NAME="PLB_MBusy" RIGHT="1" SIGNAME="mb_plb_PLB_MBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="PLB_MRdErr" RIGHT="1" SIGNAME="mb_plb_PLB_MRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="51" MSB="0" NAME="PLB_MWrErr" RIGHT="1" SIGNAME="mb_plb_PLB_MWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRdBTerm" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="52" MSB="0" NAME="PLB_MRdBTerm" RIGHT="1" SIGNAME="mb_plb_PLB_MRdBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRdDAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="PLB_MRdDAck" RIGHT="1" SIGNAME="mb_plb_PLB_MRdDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="54" MSB="0" NAME="PLB_MRdDBus" RIGHT="63" SIGNAME="mb_plb_PLB_MRdDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="55" MSB="0" NAME="PLB_MRdWdAddr" RIGHT="7" SIGNAME="mb_plb_PLB_MRdWdAddr" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*4)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MRearbitrate" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="56" MSB="0" NAME="PLB_MRearbitrate" RIGHT="1" SIGNAME="mb_plb_PLB_MRearbitrate" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MWrBTerm" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="57" MSB="0" NAME="PLB_MWrBTerm" RIGHT="1" SIGNAME="mb_plb_PLB_MWrBTerm" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MWrDAck" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="58" MSB="0" NAME="PLB_MWrDAck" RIGHT="1" SIGNAME="mb_plb_PLB_MWrDAck" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MSSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="59" MSB="0" NAME="PLB_MSSize" RIGHT="3" SIGNAME="mb_plb_PLB_MSSize" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*2)-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="O" MPD_INDEX="60" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_RNW" DIR="O" MPD_INDEX="61" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="O" MPD_INDEX="62" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_abort" DIR="O" MPD_INDEX="63" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_busLock" DIR="O" MPD_INDEX="64" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="65" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="O" MPD_INDEX="66" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_masterID" DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="67" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:C_PLBV46_MID_WIDTH-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_MSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="68" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="69" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="70" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="O" MPD_INDEX="71" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="O" MPD_INDEX="72" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="O" MPD_INDEX="73" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="74" MSB="0" NAME="PLB_rdPrim" RIGHT="11" SIGNAME="mb_plb_PLB_rdPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="75" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="76" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="77" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="O" MPD_INDEX="78" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="79" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="80" MSB="0" NAME="PLB_wrPrim" RIGHT="11" SIGNAME="mb_plb_PLB_wrPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SaddrAck" DIR="O" MPD_INDEX="81" NAME="PLB_SaddrAck" SIGNAME="mb_plb_PLB_SaddrAck"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SMRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="82" MSB="0" NAME="PLB_SMRdErr" RIGHT="1" SIGNAME="mb_plb_PLB_SMRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SMWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="83" MSB="0" NAME="PLB_SMWrErr" RIGHT="1" SIGNAME="mb_plb_PLB_SMWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SMBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="84" MSB="0" NAME="PLB_SMBusy" RIGHT="1" SIGNAME="mb_plb_PLB_SMBusy" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SrdBTerm" DIR="O" MPD_INDEX="85" NAME="PLB_SrdBTerm" SIGNAME="mb_plb_PLB_SrdBTerm"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SrdComp" DIR="O" MPD_INDEX="86" NAME="PLB_SrdComp" SIGNAME="mb_plb_PLB_SrdComp"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SrdDAck" DIR="O" MPD_INDEX="87" NAME="PLB_SrdDAck" SIGNAME="mb_plb_PLB_SrdDAck"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SrdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="88" MSB="0" NAME="PLB_SrdDBus" RIGHT="31" SIGNAME="mb_plb_PLB_SrdDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SrdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="89" MSB="0" NAME="PLB_SrdWdAddr" RIGHT="3" SIGNAME="mb_plb_PLB_SrdWdAddr" VECFORMULA="[0:3]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_Srearbitrate" DIR="O" MPD_INDEX="90" NAME="PLB_Srearbitrate" SIGNAME="mb_plb_PLB_Srearbitrate"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_Sssize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="91" MSB="0" NAME="PLB_Sssize" RIGHT="1" SIGNAME="mb_plb_PLB_Sssize" VECFORMULA="[0:1]"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_Swait" DIR="O" MPD_INDEX="92" NAME="PLB_Swait" SIGNAME="mb_plb_PLB_Swait"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SwrBTerm" DIR="O" MPD_INDEX="93" NAME="PLB_SwrBTerm" SIGNAME="mb_plb_PLB_SwrBTerm"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SwrComp" DIR="O" MPD_INDEX="94" NAME="PLB_SwrComp" SIGNAME="mb_plb_PLB_SwrComp"/>
        <PORT DEF_SIGNAME="mb_plb_PLB_SwrDAck" DIR="O" MPD_INDEX="95" NAME="PLB_SwrDAck" SIGNAME="mb_plb_PLB_SwrDAck"/>
        <PORT DIR="O" MPD_INDEX="96" NAME="Bus_Error_Det" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="DCR" BUSSTD_PSF="DCR" IS_VALID="FALSE" MPD_INDEX="0" NAME="SDCR" TYPE="SLAVE"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1023" BASENAME="C_BASEADDR" BASEVALUE="0b1111111111" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0b0000000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x08" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SDCR"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="1.00.a" INSTANCE="ilmb" IPTYPE="BUS" MHS_INDEX="2" MODCLASS="BUS" MODTYPE="lmb_v10">
      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
          <DESCRIPTION>Active High External Reset</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="50000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="LMB_Clk" RIGHT="0" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="SYS_Rst" RIGHT="0" SIGNAME="sys_bus_reset"/>
        <PORT DEF_SIGNAME="ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="ilmb_LMB_Rst"/>
        <PORT DEF_SIGNAME="ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT DEF_SIGNAME="ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="ilmb_M_ReadStrobe"/>
        <PORT DEF_SIGNAME="ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="ilmb_M_WriteStrobe"/>
        <PORT DEF_SIGNAME="ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="ilmb_M_AddrStrobe"/>
        <PORT DEF_SIGNAME="ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT DEF_SIGNAME="ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
        <PORT DEF_SIGNAME="ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
        <PORT DEF_SIGNAME="ilmb_Sl_Ready" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="10" MSB="0" NAME="Sl_Ready" RIGHT="0" SIGNAME="ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT DEF_SIGNAME="ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="12" NAME="LMB_ReadStrobe" SIGNAME="ilmb_LMB_ReadStrobe"/>
        <PORT DEF_SIGNAME="ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="13" NAME="LMB_WriteStrobe" SIGNAME="ilmb_LMB_WriteStrobe"/>
        <PORT DEF_SIGNAME="ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="14" NAME="LMB_AddrStrobe" SIGNAME="ilmb_LMB_AddrStrobe"/>
        <PORT DEF_SIGNAME="ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="15" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT DEF_SIGNAME="ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT DEF_SIGNAME="ilmb_LMB_Ready" DIR="O" MPD_INDEX="17" NAME="LMB_Ready" SIGNAME="ilmb_LMB_Ready"/>
        <PORT DEF_SIGNAME="ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="1.00.a" INSTANCE="dlmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
      <DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/doc/lmb_v10.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
          <DESCRIPTION>Active High External Reset</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="50000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="LMB_Clk" RIGHT="0" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="SYS_Rst" RIGHT="0" SIGNAME="sys_bus_reset"/>
        <PORT DEF_SIGNAME="dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="dlmb_LMB_Rst"/>
        <PORT DEF_SIGNAME="dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT DEF_SIGNAME="dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="dlmb_M_ReadStrobe"/>
        <PORT DEF_SIGNAME="dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="dlmb_M_WriteStrobe"/>
        <PORT DEF_SIGNAME="dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="dlmb_M_AddrStrobe"/>
        <PORT DEF_SIGNAME="dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT DEF_SIGNAME="dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
        <PORT DEF_SIGNAME="dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
        <PORT DEF_SIGNAME="dlmb_Sl_Ready" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="10" MSB="0" NAME="Sl_Ready" RIGHT="0" SIGNAME="dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
        <PORT DEF_SIGNAME="dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT DEF_SIGNAME="dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="12" NAME="LMB_ReadStrobe" SIGNAME="dlmb_LMB_ReadStrobe"/>
        <PORT DEF_SIGNAME="dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="13" NAME="LMB_WriteStrobe" SIGNAME="dlmb_LMB_WriteStrobe"/>
        <PORT DEF_SIGNAME="dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="14" NAME="LMB_AddrStrobe" SIGNAME="dlmb_LMB_AddrStrobe"/>
        <PORT DEF_SIGNAME="dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="15" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT DEF_SIGNAME="dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT DEF_SIGNAME="dlmb_LMB_Ready" DIR="O" MPD_INDEX="17" NAME="LMB_Ready" SIGNAME="dlmb_LMB_Ready"/>
        <PORT DEF_SIGNAME="dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE HWVERSION="2.10.b" INSTANCE="dlmb_cntlr" IPTYPE="PERIPHERAL" MHS_INDEX="4" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
      <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_b/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00007fff">
          <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="2" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x80000000">
          <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="SLMB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="dlmb_LMB_Rst"/>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="dlmb_LMB_AddrStrobe"/>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="dlmb_LMB_ReadStrobe"/>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="dlmb_LMB_WriteStrobe"/>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="dlmb_Sl_Ready"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Rst" DIR="O" MPD_INDEX="10" NAME="BRAM_Rst_A" SIGNAME="dlmb_port_BRAM_Rst"/>
        <PORT BUS="BRAM_PORT" CLKFREQUENCY="50000000" DEF_SIGNAME="dlmb_port_BRAM_Clk" DIR="O" MPD_INDEX="11" NAME="BRAM_Clk_A" SIGNAME="dlmb_port_BRAM_Clk"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_EN" DIR="O" MPD_INDEX="12" NAME="BRAM_EN_A" SIGNAME="dlmb_port_BRAM_EN"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="13" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="dlmb_port_BRAM_WEN" VECFORMULA="[0:(C_LMB_DWIDTH/8)-1]"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="15" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE"/>
        <BUSINTERFACE BUSNAME="dlmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="32767" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00007fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="32768" SIZEABRV="32K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SLMB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="2.10.b" INSTANCE="ilmb_cntlr" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
      <DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v2_10_b/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00007fff">
          <DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="2" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0x80000000">
          <DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="SLMB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="ilmb_LMB_Rst"/>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="ilmb_LMB_AddrStrobe"/>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="ilmb_LMB_ReadStrobe"/>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="ilmb_LMB_WriteStrobe"/>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="ilmb_Sl_Ready"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Rst" DIR="O" MPD_INDEX="10" NAME="BRAM_Rst_A" SIGNAME="ilmb_port_BRAM_Rst"/>
        <PORT BUS="BRAM_PORT" CLKFREQUENCY="50000000" DEF_SIGNAME="ilmb_port_BRAM_Clk" DIR="O" MPD_INDEX="11" NAME="BRAM_Clk_A" SIGNAME="ilmb_port_BRAM_Clk"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_EN" DIR="O" MPD_INDEX="12" NAME="BRAM_EN_A" SIGNAME="ilmb_port_BRAM_EN"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="13" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="ilmb_port_BRAM_WEN" VECFORMULA="[0:(C_LMB_DWIDTH/8)-1]"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="15" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
        <PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE"/>
        <BUSINTERFACE BUSNAME="ilmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="32767" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00007fff" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="32768" SIZEABRV="32K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SLMB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="lmb_bram" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY" MODTYPE="bram_block">
      <DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x8000">
          <DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>Data Width of Port A and B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32">
          <DESCRIPTION>Address Width of Port A and B</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4">
          <DESCRIPTION>Number of Byte Write Enables</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="ilmb_port_BRAM_Rst"/>
        <PORT BUS="PORTA" CLKFREQUENCY="50000000" DEF_SIGNAME="ilmb_port_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="ilmb_port_BRAM_Clk"/>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="ilmb_port_BRAM_EN"/>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="ilmb_port_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
        <PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="dlmb_port_BRAM_Rst"/>
        <PORT BUS="PORTB" CLKFREQUENCY="50000000" DEF_SIGNAME="dlmb_port_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="dlmb_port_BRAM_Clk"/>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="dlmb_port_BRAM_EN"/>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="dlmb_port_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
        <PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ilmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET"/>
        <BUSINTERFACE BUSNAME="dlmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET"/>
      </BUSINTERFACES>
    </MODULE>
    <MODULE HWVERSION="2.00.a" INSTANCE="LEDs_8Bit" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio">
      <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="6" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81440000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="7" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8144ffff">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="7" MHS_INDEX="0" MPD_INDEX="44" MSB="0" NAME="GPIO_IO_O" RIGHT="7" SIGNAME="fpga_0_LEDs_8Bit_GPIO_IO_O_pin" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="43" MSB="0" NAME="GPIO_IO_I" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="45" MSB="0" NAME="GPIO_IO_T" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="46" MSB="0" NAME="GPIO2_IO_I" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="GPIO2_IO_O" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="GPIO2_IO_T" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="IO" ENDIAN="BIG" IS_THREE_STATE="TRUE" LEFT="0" LSB="7" MPD_INDEX="49" MSB="0" NAME="GPIO_IO" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" ENDIAN="BIG" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="GPIO2_IO" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2168717312" BASENAME="C_BASEADDR" BASEVALUE="0x81440000" HIGHDECIMAL="2168782847" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8144ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="2.00.a" INSTANCE="LED_7SEGMENT" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio">
      <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="6" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81460000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="7" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8146ffff">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="12">
          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="11" MHS_INDEX="0" MPD_INDEX="44" MSB="0" NAME="GPIO_IO_O" RIGHT="11" SIGNAME="fpga_0_LED_7SEGMENT_GPIO_IO_O_pin" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="43" MSB="0" NAME="GPIO_IO_I" RIGHT="11" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="11" MPD_INDEX="45" MSB="0" NAME="GPIO_IO_T" RIGHT="11" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="46" MSB="0" NAME="GPIO2_IO_I" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="GPIO2_IO_O" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="GPIO2_IO_T" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="IO" ENDIAN="BIG" IS_THREE_STATE="TRUE" LEFT="0" LSB="11" MPD_INDEX="49" MSB="0" NAME="GPIO_IO" RIGHT="11" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" ENDIAN="BIG" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="GPIO2_IO" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2168848384" BASENAME="C_BASEADDR" BASEVALUE="0x81460000" HIGHDECIMAL="2168913919" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8146ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="2.00.a" INSTANCE="Push_Buttons_3Bit" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio">
      <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="6" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81420000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="7" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8142ffff">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="3">
          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="2" MHS_INDEX="0" MPD_INDEX="43" MSB="0" NAME="GPIO_IO_I" RIGHT="2" SIGNAME="fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="44" MSB="0" NAME="GPIO_IO_O" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="45" MSB="0" NAME="GPIO_IO_T" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="46" MSB="0" NAME="GPIO2_IO_I" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="GPIO2_IO_O" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="GPIO2_IO_T" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="IO" ENDIAN="BIG" IS_THREE_STATE="TRUE" LEFT="0" LSB="2" MPD_INDEX="49" MSB="0" NAME="GPIO_IO" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" ENDIAN="BIG" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="GPIO2_IO" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2168586240" BASENAME="C_BASEADDR" BASEVALUE="0x81420000" HIGHDECIMAL="2168651775" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8142ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="2.00.a" INSTANCE="Switches_8Bit" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="PERIPHERAL" MODTYPE="xps_gpio">
      <DESCRIPTION TYPE="SHORT">XPS General Purpose IO</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the PLBV46 bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_gpio_v2_00_a/doc/xps_gpio.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="6" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81400000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="7" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8140ffff">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="10" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
          <DESCRIPTION>GPIO Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="14" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="17" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Channel 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="7" MHS_INDEX="0" MPD_INDEX="43" MSB="0" NAME="GPIO_IO_I" RIGHT="7" SIGNAME="fpga_0_Switches_8Bit_GPIO_IO_I_pin" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="44" MSB="0" NAME="GPIO_IO_O" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="45" MSB="0" NAME="GPIO_IO_T" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]"/>
        <PORT DIR="I" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="46" MSB="0" NAME="GPIO2_IO_I" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="47" MSB="0" NAME="GPIO2_IO_O" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="GPIO2_IO_T" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]"/>
        <PORT DIR="IO" ENDIAN="BIG" IS_THREE_STATE="TRUE" LEFT="0" LSB="7" MPD_INDEX="49" MSB="0" NAME="GPIO_IO" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO_WIDTH-1)]">
          <DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" ENDIAN="BIG" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="GPIO2_IO" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_GPIO2_WIDTH-1)]">
          <DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2168455168" BASENAME="C_BASEADDR" BASEVALUE="0x81400000" HIGHDECIMAL="2168520703" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8140ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.01.a" INSTANCE="RS232_PORT" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="PERIPHERAL" MODTYPE="xps_uartlite">
      <DESCRIPTION TYPE="SHORT">XPS UART (Lite)</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_uartlite_v1_01_a/doc/xps_uartlite.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_SPLB_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
          <DESCRIPTION>Clock Frequency of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="6" MPD_INDEX="2" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x84000000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="7" MPD_INDEX="3" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8400ffff">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="6" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="11" NAME="C_BAUDRATE" TYPE="INTEGER" VALUE="9600">
          <DESCRIPTION>UART Lite Baud Rate </DESCRIPTION>
          <DESCRIPTION>Baud Rate</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_DATA_BITS" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>Number of Data Bits in a Serial Frame</DESCRIPTION>
          <DESCRIPTION>Data Bits</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_USE_PARITY" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Parity </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="14" NAME="C_ODD_PARITY" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Parity Type </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="42" MSB="0" NAME="RX" RIGHT="0" SIGNAME="fpga_0_RS232_PORT_RX_pin">
          <DESCRIPTION>Serial Data In</DESCRIPTION>
        </PORT>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="43" MSB="0" NAME="TX" RIGHT="0" SIGNAME="fpga_0_RS232_PORT_TX_pin">
          <DESCRIPTION>Serial Data Out</DESCRIPTION>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="3" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="4" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="5" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="6" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="8" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="10" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="11" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="12" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="13" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="14" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="15" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="16" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="17" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="33" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="34" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="35" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="37" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="38" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="40" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT DIR="O" MPD_INDEX="44" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2214592512" BASENAME="C_BASEADDR" BASEVALUE="0x84000000" HIGHDECIMAL="2214658047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8400ffff" MEMTYPE="REGISTER" MINSIZE="0x10" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="3.01.a" INSTANCE="Micron_RAM" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="MEMORY_CNTLR" MODTYPE="xps_mch_emc">
      <DESCRIPTION TYPE="SHORT">XPS Multi-Channel External Memory Controller(SRAM/Flash)</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Xilinx Multi-CHannel (MCH) PLBV46 external memory controller</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_mch_emc_v3_01_a/doc/xps_mch_emc.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="C_NUM_BANKS_MEM" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of Memory Banks </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_NUM_CHANNELS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Number of MCH Channels </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_PRIORITY_MODE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Arbitration Mode Between PLB and MCH Interface </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_INCLUDE_PLB_IPIF" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Include PLB Slave Interface </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_INCLUDE_WRBUF" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Include Write Buffer</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="6" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_MCH_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>MCH and PLB Address Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Smallest Master Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_MCH_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Data Bus Width of MCH</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_MCH_SPLB_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="20000">
          <DESCRIPTION>MCH and PLB Clock Period </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="14" NAME="C_MEM0_BASEADDR" TYPE="std_logic_vector" VALUE="0x82000000">
          <DESCRIPTION>Base Address of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="15" NAME="C_MEM0_HIGHADDR" TYPE="std_logic_vector" VALUE="0x82ffffff">
          <DESCRIPTION>High Address of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="16" NAME="C_MEM1_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Base Address of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="17" NAME="C_MEM1_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>High Address of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="18" NAME="C_MEM2_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Base Address of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="19" NAME="C_MEM2_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>High Address of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="20" NAME="C_MEM3_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff">
          <DESCRIPTION>Base Address of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="21" NAME="C_MEM3_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
          <DESCRIPTION>High Address of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="22" NAME="C_PAGEMODE_FLASH_0" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Page mode flash enable of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="23" NAME="C_PAGEMODE_FLASH_1" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Page mode flash enable of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="24" NAME="C_PAGEMODE_FLASH_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Page mode flash enable of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="25" NAME="C_PAGEMODE_FLASH_3" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Page mode flash enable of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="26" NAME="C_INCLUDE_NEGEDGE_IOREGS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Use Falling Edge IO Register in Interface Signals </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="27" NAME="C_MEM0_WIDTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Data Bus Width of Bank 0 </DESCRIPTION>
          <DESCRIPTION>Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="28" NAME="C_MEM1_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Data Bus Width of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="29" NAME="C_MEM2_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Data Bus Width of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="30" NAME="C_MEM3_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Data Bus Width of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="31" NAME="C_MAX_MEM_WIDTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Maximum Data Bus Width </DESCRIPTION>
          <DESCRIPTION>Maximum Data Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="32" NAME="C_INCLUDE_DATAWIDTH_MATCHING_0" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Execute Multiple Memory Accesses To Match Bank 0 Data Bus Width To PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="33" NAME="C_INCLUDE_DATAWIDTH_MATCHING_1" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 1 Data Bus Width To PLB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="34" NAME="C_INCLUDE_DATAWIDTH_MATCHING_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 2 Data Bus Width To PLB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="35" NAME="C_INCLUDE_DATAWIDTH_MATCHING_3" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 3 Data Bus Width To PLB Data Bus Width </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="36" NAME="C_SYNCH_MEM_0" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Bank 0 is Synchronous </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="37" NAME="C_SYNCH_PIPEDELAY_0" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Pipeline Latency of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="38" NAME="C_TCEDV_PS_MEM_0" TYPE="INTEGER" VALUE="85000">
          <DESCRIPTION>TCEDV of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="39" NAME="C_TAVDV_PS_MEM_0" TYPE="INTEGER" VALUE="85000">
          <DESCRIPTION>TAVDV of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="40" NAME="C_TPACC_PS_FLASH_0" TYPE="INTEGER" VALUE="25000">
          <DESCRIPTION>TPACC of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="41" NAME="C_THZCE_PS_MEM_0" TYPE="INTEGER" VALUE="8000">
          <DESCRIPTION>THZCE of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="42" NAME="C_THZOE_PS_MEM_0" TYPE="INTEGER" VALUE="8000">
          <DESCRIPTION>THZOE of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="43" NAME="C_TWC_PS_MEM_0" TYPE="INTEGER" VALUE="85000">
          <DESCRIPTION>TWC of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="44" NAME="C_TWP_PS_MEM_0" TYPE="INTEGER" VALUE="55000">
          <DESCRIPTION>TWP of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="45" NAME="C_TLZWE_PS_MEM_0" TYPE="INTEGER" VALUE="5000">
          <DESCRIPTION>TLZWE of Bank 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="46" NAME="C_SYNCH_MEM_1" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Bank 1 is Synchronous </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="47" NAME="C_SYNCH_PIPEDELAY_1" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Pipeline Latency of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="48" NAME="C_TCEDV_PS_MEM_1" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TCEDV of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="49" NAME="C_TAVDV_PS_MEM_1" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TAVDV of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="50" NAME="C_TPACC_PS_FLASH_1" TYPE="INTEGER" VALUE="25000">
          <DESCRIPTION>TPACC of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="51" NAME="C_THZCE_PS_MEM_1" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZCE of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="52" NAME="C_THZOE_PS_MEM_1" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZOE of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="53" NAME="C_TWC_PS_MEM_1" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TWC of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="54" NAME="C_TWP_PS_MEM_1" TYPE="INTEGER" VALUE="12000">
          <DESCRIPTION>TWP of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="55" NAME="C_TLZWE_PS_MEM_1" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>TLZWE of Bank 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="56" NAME="C_SYNCH_MEM_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Bank 2 is Synchronous </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="57" NAME="C_SYNCH_PIPEDELAY_2" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Pipeline Latency of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="58" NAME="C_TCEDV_PS_MEM_2" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TCEDV of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="59" NAME="C_TAVDV_PS_MEM_2" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TAVDV of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="60" NAME="C_TPACC_PS_FLASH_2" TYPE="INTEGER" VALUE="25000">
          <DESCRIPTION>TPACC of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="61" NAME="C_THZCE_PS_MEM_2" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZCE of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="62" NAME="C_THZOE_PS_MEM_2" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZOE of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="63" NAME="C_TWC_PS_MEM_2" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TWC of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="64" NAME="C_TWP_PS_MEM_2" TYPE="INTEGER" VALUE="12000">
          <DESCRIPTION>TWP of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="65" NAME="C_TLZWE_PS_MEM_2" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>TLZWE of Bank 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="66" NAME="C_SYNCH_MEM_3" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Bank 3 is Synchronous </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="67" NAME="C_SYNCH_PIPEDELAY_3" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Pipeline Latency of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="68" NAME="C_TCEDV_PS_MEM_3" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TCEDV of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="69" NAME="C_TAVDV_PS_MEM_3" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TAVDV of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="70" NAME="C_TPACC_PS_FLASH_3" TYPE="INTEGER" VALUE="25000">
          <DESCRIPTION>TPACC of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="71" NAME="C_THZCE_PS_MEM_3" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZCE of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="72" NAME="C_THZOE_PS_MEM_3" TYPE="INTEGER" VALUE="7000">
          <DESCRIPTION>THZOE of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="73" NAME="C_TWC_PS_MEM_3" TYPE="INTEGER" VALUE="15000">
          <DESCRIPTION>TWC of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="74" NAME="C_TWP_PS_MEM_3" TYPE="INTEGER" VALUE="12000">
          <DESCRIPTION>TWP of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="75" NAME="C_TLZWE_PS_MEM_3" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>TLZWE of Bank 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="76" NAME="C_MCH0_PROTOCOL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Interface Protocol of Ch 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="77" NAME="C_MCH0_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Access Buffer of Ch 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="78" NAME="C_MCH0_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Read Data Buffer Depath of Ch 0 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="79" NAME="C_MCH1_PROTOCOL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Interface Protocol of Ch 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="80" NAME="C_MCH1_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Access Buffer of Ch 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="81" NAME="C_MCH1_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Read Data Buffer of Ch 1 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="82" NAME="C_MCH2_PROTOCOL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Interface Protocol of Ch 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="83" NAME="C_MCH2_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Access Buffer of Ch 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="84" NAME="C_MCH2_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Read Data Buffer of Ch 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="85" NAME="C_MCH3_PROTOCOL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Interface Protocol of Ch 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="86" NAME="C_MCH3_ACCESSBUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Access Buffer of Ch 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="87" NAME="C_MCH3_RDDATABUF_DEPTH" TYPE="INTEGER" VALUE="16">
          <DESCRIPTION>Depth of Read Data Buffer of Ch 3 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="88" NAME="C_XCL0_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cacheline Size of Ch0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="89" NAME="C_XCL0_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer Type of Ch0</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="90" NAME="C_XCL1_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cacheline Size of Ch1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="91" NAME="C_XCL1_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer Type of Ch1</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="92" NAME="C_XCL2_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cacheline Size of Ch2</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="93" NAME="C_XCL2_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer Type of Ch2</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="94" NAME="C_XCL3_LINESIZE" TYPE="INTEGER" VALUE="4">
          <DESCRIPTION>Cacheline Size of Ch3</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="95" NAME="C_XCL3_WRITEXFER" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Write Transfer Type of Ch3</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="50000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="1" MSB="0" NAME="RdClk" RIGHT="0" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="31" MHS_INDEX="1" MPD_INDEX="78" MSB="0" NAME="Mem_A" RIGHT="31" SIGNAME="0b000000000 &amp; fpga_0_Micron_RAM_Mem_A_pin_vslice_9_31_concat" VECFORMULA="[0:(C_MCH_SPLB_AWIDTH-1)]">
          <DESCRIPTION>Memory Address Bus</DESCRIPTION>
        </PORT>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="2" MPD_INDEX="81" MSB="0" NAME="Mem_OEN" RIGHT="0" SIGNAME="fpga_0_Micron_RAM_Mem_OEN_pin" VECFORMULA="[0:(C_NUM_BANKS_MEM-1)]">
          <DESCRIPTION>Memory Output Enable</DESCRIPTION>
        </PORT>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="3" MPD_INDEX="82" MSB="0" NAME="Mem_WEN" RIGHT="0" SIGNAME="fpga_0_Micron_RAM_Mem_WEN_pin">
          <DESCRIPTION>Memory Write Enable</DESCRIPTION>
        </PORT>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="1" MHS_INDEX="4" MPD_INDEX="84" MSB="0" NAME="Mem_BEN" RIGHT="1" SIGNAME="fpga_0_Micron_RAM_Mem_BEN_pin" VECFORMULA="[0:((C_MAX_MEM_WIDTH/8)-1)]">
          <DESCRIPTION>Memory Byte Enable</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" ENDIAN="BIG" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="0" LSB="15" MHS_INDEX="5" MPD_INDEX="90" MSB="0" NAME="Mem_DQ" RIGHT="15" SIGNAME="fpga_0_Micron_RAM_Mem_DQ_pin" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]">
          <DESCRIPTION>Memory Data Bus</DESCRIPTION>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="MCH_SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="2" NAME="MCH_SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="3" NAME="MCH0_Access_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="MCH0_Access_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="MCH0_Access_Write" SIGNAME="__NOC__"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="6" NAME="MCH0_Access_Full" SIGNAME="__NOC__"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="7" NAME="MCH0_ReadData_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="MCH0_ReadData_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="MCH0_ReadData_Read" SIGNAME="__NOC__"/>
        <PORT BUS="MCH0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="10" NAME="MCH0_ReadData_Exists" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="11" NAME="MCH1_Access_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="MCH1_Access_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="13" NAME="MCH1_Access_Write" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="MCH1_Access_Full" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="MCH1_ReadData_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="MCH1_ReadData_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="17" NAME="MCH1_ReadData_Read" SIGNAME="__NOC__"/>
        <PORT BUS="MCH1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="18" NAME="MCH1_ReadData_Exists" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="19" NAME="MCH2_Access_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="20" MSB="0" NAME="MCH2_Access_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="21" NAME="MCH2_Access_Write" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="22" NAME="MCH2_Access_Full" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="23" NAME="MCH2_ReadData_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="24" MSB="0" NAME="MCH2_ReadData_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="25" NAME="MCH2_ReadData_Read" SIGNAME="__NOC__"/>
        <PORT BUS="MCH2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="26" NAME="MCH2_ReadData_Exists" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="MCH3_Access_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="MCH3_Access_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="MCH3_Access_Write" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="30" NAME="MCH3_Access_Full" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="MCH3_ReadData_Control" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="MCH3_ReadData_Data" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_MCH_NATIVE_DWIDTH-1)]"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="MCH3_ReadData_Read" SIGNAME="__NOC__"/>
        <PORT BUS="MCH3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="MCH3_ReadData_Exists" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="36" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="37" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="38" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="39" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="40" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="41" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="42" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="43" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="44" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="45" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="47" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="48" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="49" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="51" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="52" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="53" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="54" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="56" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="57" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="58" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="59" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="60" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="61" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="62" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="63" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="64" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="65" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="66" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="67" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="68" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="69" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="70" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="71" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="72" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="73" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="74" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="75" MSB="0" NAME="Mem_DQ_I" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="76" MSB="0" NAME="Mem_DQ_O" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]"/>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="77" MSB="0" NAME="Mem_DQ_T" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:(C_MAX_MEM_WIDTH-1)]"/>
        <PORT DIR="O" MPD_INDEX="79" NAME="Mem_RPN" SIGNAME="__NOC__">
          <DESCRIPTION>Memory Reset/Power Down</DESCRIPTION>
        </PORT>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="80" MSB="0" NAME="Mem_CEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[0:(C_NUM_BANKS_MEM-1)]">
          <DESCRIPTION>Memory Chip Enable Active Low</DESCRIPTION>
        </PORT>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="83" MSB="0" NAME="Mem_QWEN" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:((C_MAX_MEM_WIDTH/8)-1)]">
          <DESCRIPTION>Memory Qualified Write Enable</DESCRIPTION>
        </PORT>
        <PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="85" MSB="0" NAME="Mem_CE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[0:(C_NUM_BANKS_MEM-1)]">
          <DESCRIPTION>Memory Chip Enable Active High</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="86" NAME="Mem_ADV_LDN" SIGNAME="__NOC__">
          <DESCRIPTION>Memory Advanced Burst Address/Load New Address</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="87" NAME="Mem_LBON" SIGNAME="__NOC__">
          <DESCRIPTION>Memory Linear/Interleaved Burst Order</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="88" NAME="Mem_CKEN" SIGNAME="__NOC__">
          <DESCRIPTION>Memory Clock Enable</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="89" NAME="Mem_RNW" SIGNAME="__NOC__">
          <DESCRIPTION>Memory Read Not Write</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="1" NAME="MCH0" TYPE="TARGET"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="2" NAME="MCH1" TYPE="TARGET"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="3" NAME="MCH2" TYPE="TARGET"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_VALID="FALSE" MPD_INDEX="4" NAME="MCH3" TYPE="TARGET"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2181038080" BASENAME="C_MEM0_BASEADDR" BASEVALUE="0x82000000" HIGHDECIMAL="2197815295" HIGHNAME="C_MEM0_HIGHADDR" HIGHVALUE="0x82ffffff" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="16777216" SIZEABRV="16M">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
            <SLAVE BUSINTERFACE="MCH0"/>
            <SLAVE BUSINTERFACE="MCH1"/>
            <SLAVE BUSINTERFACE="MCH2"/>
            <SLAVE BUSINTERFACE="MCH3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MEM1_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_MEM1_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
            <SLAVE BUSINTERFACE="MCH0"/>
            <SLAVE BUSINTERFACE="MCH1"/>
            <SLAVE BUSINTERFACE="MCH2"/>
            <SLAVE BUSINTERFACE="MCH3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MEM2_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_MEM2_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
            <SLAVE BUSINTERFACE="MCH0"/>
            <SLAVE BUSINTERFACE="MCH1"/>
            <SLAVE BUSINTERFACE="MCH2"/>
            <SLAVE BUSINTERFACE="MCH3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_MEM3_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_MEM3_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
            <SLAVE BUSINTERFACE="MCH0"/>
            <SLAVE BUSINTERFACE="MCH1"/>
            <SLAVE BUSINTERFACE="MCH2"/>
            <SLAVE BUSINTERFACE="MCH3"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.02.a" INSTANCE="xps_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="PERIPHERAL" MODTYPE="xps_timer">
      <DESCRIPTION TYPE="SHORT">XPS Timer/Counter</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Timer counter with PLBV46 interface</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_timer_v1_02_a/doc/xps_timer.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>The Width of Counter in Timer</DESCRIPTION>
          <DESCRIPTION>Count Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Only One Timer is present</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>TRIG0 Active Level</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>TRIG1 Active Level</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>GEN0 Active Level</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="6" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>GEN1 Active Level</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x83c00000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x83c0ffff">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
          <DESCRIPTION>Capture Trig 0</DESCRIPTION>
        </PORT>
        <PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
          <DESCRIPTION>Capture Trig 1</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
          <DESCRIPTION>Generate Out 0</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
          <DESCRIPTION>Generate Out 1</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
          <DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
        </PORT>
        <PORT DIR="O" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="7" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="8" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:C_SPLB_AWIDTH-1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="10" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="11" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="12" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="13" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="16" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="17" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="18" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="19" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="20" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="21" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="22" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="23" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="24" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="25" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="26" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="28" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="29" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:C_SPLB_AWIDTH-1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="30" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="31" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="32" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="33" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="34" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="35" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="36" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="37" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="38" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="39" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="40" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="42" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="43" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="44" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="45" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="46" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="47" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="48" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2210398208" BASENAME="C_BASEADDR" BASEVALUE="0x83c00000" HIGHDECIMAL="2210463743" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x83c0ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="4.00.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="IP" MODTYPE="clock_generator">
      <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_00_a/doc/clock_generator.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e">
          <DESCRIPTION>Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="3s1200e">
          <DESCRIPTION>Device</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="fg320">
          <DESCRIPTION>Package</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-4">
          <DESCRIPTION>Speed Grade</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="50000000">
          <DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="50000000">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Varaible Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION> Varaible Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION> Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION>Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
          <DESCRIPTION> Variable Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Clock Deskew</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Required Phase</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Required Group</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE">
          <DESCRIPTION>Buffered</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE">
          <DESCRIPTION>Variable Phase Shift</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1">
          <DESCRIPTION>External Reset</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="93" NAME="C_CLK_GEN" VALUE="UPDATE">
          <DESCRIPTION>C_CLK_GEN</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="50000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="CLKIN" RIGHT="0" SIGIS="CLK" SIGNAME="dcm_clk_s"/>
        <PORT CLKFREQUENCY="50000000" DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="CLKOUT0" RIGHT="0" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="2" MPD_INDEX="23" MSB="0" NAME="RST" RIGHT="0" SIGIS="RST" SIGNAME="sys_rst_s"/>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="3" MPD_INDEX="24" MSB="0" NAME="LOCKED" RIGHT="0" SIGNAME="Dcm_all_locked"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE HWVERSION="1.00.g" INSTANCE="mdm_0" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="DEBUG" MODTYPE="mdm">
      <DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v1_00_g/doc/mdm.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Specifies the JTAG user-defined register used </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Specifies the Bus Interface for the JTAG UART </DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x84400000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x8440ffff">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="12" NAME="C_OPB_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>OPB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="13" NAME="C_OPB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>OPB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="14" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Number of MicroBlaze debug ports </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="15" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Enable JTAG UART </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="16" NAME="C_UART_WIDTH" TYPE="INTEGER" VALUE="8">
          <DESCRIPTION>UART Data size </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="17" NAME="C_WRITE_FSL_PORTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Write FSL Port</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="1" MSB="0" NAME="Debug_SYS_Rst" RIGHT="0" SIGNAME="Debug_SYS_Rst"/>
        <PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/>
        <PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="4" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="5" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="8" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="9" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="10" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="11" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="12" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="13" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="14" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="15" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="17" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="19" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="20" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="22" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="23" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="24" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="25" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="26" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="28" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="30" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="31" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="32" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="33" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="34" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="35" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="36" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="37" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="39" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="40" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="41" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="42" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="43" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="44" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="OPB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="47" NAME="OPB_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="48" MSB="0" NAME="OPB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_OPB_AWIDTH-1]"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="49" MSB="0" NAME="OPB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:C_OPB_DWIDTH/8-1]"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="OPB_RNW" SIGNAME="__NOC__"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="OPB_select" SIGNAME="__NOC__"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="OPB_seqAddr" SIGNAME="__NOC__"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="53" MSB="0" NAME="OPB_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_OPB_DWIDTH-1]"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="54" MSB="0" NAME="MDM_DBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_OPB_DWIDTH-1]"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="MDM_errAck" SIGNAME="__NOC__"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="56" NAME="MDM_retry" SIGNAME="__NOC__"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="MDM_toutSup" SIGNAME="__NOC__"/>
        <PORT BUS="SOPB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="MDM_xferAck" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Clk" DIR="O" MPD_INDEX="59" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Clk"/>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDI" DIR="O" MPD_INDEX="60" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_mdm_bus_Dbg_TDI"/>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_TDO" DIR="I" MPD_INDEX="61" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_mdm_bus_Dbg_TDO"/>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="62" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="4" SIGNAME="microblaze_0_mdm_bus_Dbg_Reg_En" VECFORMULA="[0:4]"/>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Capture" DIR="O" MPD_INDEX="63" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Capture"/>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Shift" DIR="O" MPD_INDEX="64" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Shift"/>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Dbg_Update" DIR="O" MPD_INDEX="65" NAME="Dbg_Update_0" SIGNAME="microblaze_0_mdm_bus_Dbg_Update"/>
        <PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_mdm_bus_Debug_Rst" DIR="O" MPD_INDEX="66" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_mdm_bus_Debug_Rst"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="68" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="69" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="70" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="72" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Update_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="76" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="78" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Update_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="83" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="84" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="86" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Update_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="91" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="92" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="93" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="94" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Update_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_Rst_4" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="Dbg_Clk_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="101" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="102" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Update_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_Rst_5" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="107" NAME="Dbg_Clk_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="110" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Update_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_Rst_6" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="115" NAME="Dbg_Clk_7" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="116" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="117" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="118" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Update_7" SIGNAME="__NOC__"/>
        <PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="123" NAME="bscan_tdi" SIGNAME="bscan_tdi"/>
        <PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="124" NAME="bscan_reset" SIGNAME="bscan_reset"/>
        <PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="125" NAME="bscan_shift" SIGNAME="bscan_shift"/>
        <PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="126" NAME="bscan_update" SIGNAME="bscan_update"/>
        <PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="127" NAME="bscan_capture" SIGNAME="bscan_capture"/>
        <PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="128" NAME="bscan_sel1" SIGNAME="bscan_sel1"/>
        <PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="129" NAME="bscan_drck1" SIGNAME="bscan_drck1"/>
        <PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="130" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/>
        <PORT BUS="SFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="131" NAME="FSL0_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="132" NAME="FSL0_S_READ" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="133" MSB="0" NAME="FSL0_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="SFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="134" NAME="FSL0_S_CONTROL" SIGNAME="__NOC__"/>
        <PORT BUS="SFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="135" NAME="FSL0_S_EXISTS" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="136" NAME="FSL0_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="FSL0_M_WRITE" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="138" MSB="0" NAME="FSL0_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
        <PORT BUS="MFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="FSL0_M_CONTROL" SIGNAME="__NOC__"/>
        <PORT BUS="MFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="140" NAME="FSL0_M_FULL" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="144" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="145" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="146" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="147" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/>
        <PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="148" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
        <BUSINTERFACE BUSNAME="microblaze_0_mdm_bus" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="4" NAME="MBDEBUG_0" TYPE="INITIATOR"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="OPB" BUSSTD_PSF="OPB" IS_VALID="FALSE" MPD_INDEX="1" NAME="SOPB" TYPE="SLAVE"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="2" NAME="SFSL0" TYPE="SLAVE"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="3" NAME="MFSL0" TYPE="MASTER"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_1" TYPE="INITIATOR"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_2" TYPE="INITIATOR"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_3" TYPE="INITIATOR"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_4" TYPE="INITIATOR"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_5" TYPE="INITIATOR"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="10" NAME="MBDEBUG_6" TYPE="INITIATOR"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG2" IS_VALID="FALSE" MPD_INDEX="11" NAME="MBDEBUG_7" TYPE="INITIATOR"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="12" NAME="XMTC" TYPE="INITIATOR"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2218786816" BASENAME="C_BASEADDR" BASEVALUE="0x84400000" HIGHDECIMAL="2218852351" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8440ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
            <SLAVE BUSINTERFACE="SOPB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="2.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
      <DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v2_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="lx">
          <DESCRIPTION>Device Subfamily</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4">
          <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4">
          <DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION>
        </PARAMETER>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>External Reset Active High </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1">
          <DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="50000000" DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="Slowest_sync_clk" RIGHT="0" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="Ext_Reset_In" RIGHT="0" SIGIS="RST" SIGNAME="sys_rst_s"/>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="2" MPD_INDEX="3" MSB="0" NAME="MB_Debug_Sys_Rst" RIGHT="0" SIGIS="RST" SIGNAME="Debug_SYS_Rst"/>
        <PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="3" MPD_INDEX="10" MSB="0" NAME="Dcm_locked" RIGHT="0" SIGNAME="Dcm_all_locked"/>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="4" MPD_INDEX="17" MSB="0" NAME="MB_Reset" RIGHT="0" SIGIS="RST" SIGNAME="mb_reset"/>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="5" MPD_INDEX="18" MSB="0" NAME="Bus_Struct_Reset" RIGHT="0" SIGIS="RST" SIGNAME="sys_bus_reset" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="6" MPD_INDEX="19" MSB="0" NAME="Peripheral_Reset" RIGHT="0" SIGIS="RST" SIGNAME="sys_periph_reset" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
        <PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR"/>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR"/>
      </BUSINTERFACES>
    </MODULE>
    <MODULE HWVERSION="1.01.b" INSTANCE="xps_ps2_0" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="PERIPHERAL" MODTYPE="xps_ps2">
      <DESCRIPTION TYPE="SHORT">XPS PS2 Interface</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">PLBV46 to PS2 Adapter</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_ps2_v1_01_b/doc/xps_ps2.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x86a00000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x86a0ffff">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>Enable Port 2 </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_SPLB_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
          <DESCRIPTION>Clock Frequency of PLB Slave</DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="42" MSB="0" NAME="IP2INTC_Irpt_1" RIGHT="0" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="xps_ps2_0_IP2INTC_Irpt_1"/>
        <PORT DIR="IO" ENDIAN="BIG" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="56" MSB="0" NAME="PS2_1_DATA" RIGHT="0" SIGNAME="xps_ps2_0_PS2_1_DATA">
          <DESCRIPTION>PS2 1 Data IO</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" ENDIAN="BIG" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="0" LSB="0" MHS_INDEX="2" MPD_INDEX="57" MSB="0" NAME="PS2_1_CLK" RIGHT="0" SIGNAME="xps_ps2_0_PS2_1_CLK">
          <DESCRIPTION>PS2 1 Clock IO</DESCRIPTION>
        </PORT>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="43" NAME="IP2INTC_Irpt_2" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="44" NAME="PS2_1_DATA_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="45" NAME="PS2_1_DATA_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="46" NAME="PS2_1_DATA_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="47" NAME="PS2_1_CLK_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="48" NAME="PS2_1_CLK_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="49" NAME="PS2_1_CLK_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="50" NAME="PS2_2_DATA_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="51" NAME="PS2_2_DATA_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="52" NAME="PS2_2_DATA_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="53" NAME="PS2_2_CLK_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="54" NAME="PS2_2_CLK_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="55" NAME="PS2_2_CLK_T" SIGNAME="__NOC__"/>
        <PORT DIR="IO" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="58" NAME="PS2_2_DATA" SIGNAME="__NOC__">
          <DESCRIPTION>PS2 2 Data IO</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="59" NAME="PS2_2_CLK" SIGNAME="__NOC__">
          <DESCRIPTION>PS2 2 Clock IO</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2258632704" BASENAME="C_BASEADDR" BASEVALUE="0x86a00000" HIGHDECIMAL="2258698239" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x86a0ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="0"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="2.01.a" INSTANCE="xps_intc_0" IPTYPE="PERIPHERAL" MHS_INDEX="18" MODCLASS="INTERRUPT_CNTLR" MODTYPE="xps_intc">
      <DESCRIPTION TYPE="SHORT">XPS Interrupt Controller</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">intc core attached to the PLBV46</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/xps_intc_v2_01_a/doc/xps_intc.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e">
          <DESCRIPTION>Device Family</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="1" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81800000">
          <DESCRIPTION>Base Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="2" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8180ffff">
          <DESCRIPTION>High Address</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="3" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="4" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="5" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Number of PLB Masters</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
          <DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
          <DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="10" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="2">
          <DESCRIPTION>Number of Interrupt Inputs </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111100">
          <DESCRIPTION>Type of Interrupt for Each Input </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
          <DESCRIPTION>Type of Each Edge Senstive Interrupt </DESCRIPTION>
        </PARAMETER>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
          <DESCRIPTION>Type of Each Level Sensitive Interrupt </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="14" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Support IPR </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="15" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Support SIE </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="16" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Support CIE </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="17" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>Support IVR </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="18" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1">
          <DESCRIPTION>IRQ Output Use Level </DESCRIPTION>
        </PARAMETER>
        <PARAMETER MPD_INDEX="19" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1">
          <DESCRIPTION>The Sense of IRQ Output </DESCRIPTION>
        </PARAMETER>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="0" MPD_INDEX="42" MSB="1" NAME="Intr" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="xps_ps2_0_IP2INTC_Irpt_1 &amp; my_timer_0_IP2INTC_Irpt" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]"/>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="43" MSB="0" NAME="Irq" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="microblaze_0_INTERRUPT"/>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="3" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="4" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="5" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="6" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="8" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="10" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="11" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="12" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="13" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="14" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="15" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="16" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="17" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="32" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="33" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="34" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="35" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="37" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="38" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="40" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2172649472" BASENAME="C_BASEADDR" BASEVALUE="0x81800000" HIGHDECIMAL="2172715007" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8180ffff" MEMTYPE="REGISTER" MINSIZE="0x20" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
        <SOURCE INSTANCE="xps_ps2_0" PRIORITY="0" SIGNAME="xps_ps2_0_IP2INTC_Irpt_1"/>
        <SOURCE INSTANCE="my_timer_0" PRIORITY="1" SIGNAME="my_timer_0_IP2INTC_Irpt"/>
        <TARGET INSTANCE="microblaze_0"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="my_timer_0" IPTYPE="PERIPHERAL" MHS_INDEX="19" MODCLASS="PERIPHERAL" MODTYPE="my_timer">
      <DESCRIPTION TYPE="SHORT">MY_TIMER</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_local"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0xc0a00000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc0a0ffff"/>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="6" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_SPLB_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="20000"/>
        <PARAMETER MPD_INDEX="11" NAME="C_INCLUDE_DPHASE_TIMER" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="42" MSB="0" NAME="IP2INTC_Irpt" RIGHT="0" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="my_timer_0_IP2INTC_Irpt"/>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="3231711232" BASENAME="C_BASEADDR" BASEVALUE="0xc0a00000" HIGHDECIMAL="3231776767" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xc0a0ffff" MEMTYPE="REGISTER" MINSIZE="0x200" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
      <INTERRUPTINFO TYPE="SOURCE">
        <TARGET INSTANCE="xps_intc_0" INTC_INDEX="0" PRIORITY="1"/>
      </INTERRUPTINFO>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="graph_acc_0" IPTYPE="PERIPHERAL" MHS_INDEX="20" MODCLASS="PERIPHERAL" MODTYPE="graph_acc">
      <LICENSEINFO ICON_NAME="ps_core_local"/>
      <PARAMETERS>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0xc1e00000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0xc1e0ffff"/>
        <PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER MPD_INDEX="6" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER MPD_INDEX="9" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_SPLB_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="20000"/>
        <PARAMETER MPD_INDEX="11" NAME="C_INCLUDE_DPHASE_TIMER" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan3e"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="HS" RIGHT="0" SIGNAME="graph_acc_0_HS"/>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="0" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="VS" RIGHT="0" SIGNAME="graph_acc_0_VS"/>
        <PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="7" MHS_INDEX="2" MPD_INDEX="2" MSB="0" NAME="VGA_rgb" RIGHT="7" SIGNAME="graph_acc_0_VGA_rgb" VECFORMULA="[0:7]"/>
        <PORT BUS="SPLB" CLKFREQUENCY="50000000" DEF_SIGNAME="clk_50_0000MHz" DIR="I" MPD_INDEX="3" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_50_0000MHz"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="4" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="7" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="8" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="9" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="10" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MPD_INDEX="11" MSB="0" NAME="PLB_masterID" RIGHT="0" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="12" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="13" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="14" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="15" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="16" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="17" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="18" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="19" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="20" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="21" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="22" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="23" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="24" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="25" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="26" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="28" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="29" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="31" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="32" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="33" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="34" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="35" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="36" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="38" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="39" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="40" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="42" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="43" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
        <PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="44" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE"/>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="3252682752" BASENAME="C_BASEADDR" BASEVALUE="0xc1e00000" HIGHDECIMAL="3252748287" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xc1e0ffff" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="SPLB"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
  </MODULES>

</EDKSYSTEM>