Release 12.2 par M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

NEPTUNUS-6::  Tue Oct 04 11:38:01 2011

par -w -intstyle ise -ol high -t 1 top_map.ncd top.ncd top.pcf 


Constraints file: top.pcf.
Loading device for application Rf_Device from file '3s1200e.nph' in environment C:\Xilinx\12.2\ISE_DS\ISE\.
   "top" is an NCD, version 3.2, device xc3s1200e, package fg320, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)


Device speed data version:  "PRODUCTION 1.27 2010-06-22".


Design Summary Report:

 Number of External IOBs                          90 out of 250    36%

   Number of External Input IOBs                 14

      Number of External Input IBUFs             14
        Number of LOCed External Input IBUFs     14 out of 14    100%


   Number of External Output IOBs                58

      Number of External Output IOBs             58
        Number of LOCed External Output IOBs     58 out of 58    100%


   Number of External Bidir IOBs                 18

      Number of External Bidir IOBs              18
        Number of LOCed External Bidir IOBs      18 out of 18    100%


   Number of BSCANs                          1 out of 1     100%
   Number of BUFGMUXs                        2 out of 24      8%
   Number of DCMs                            1 out of 8      12%
   Number of MULT18X18SIOs                   3 out of 28     10%
   Number of RAMB16s                        19 out of 28     67%
   Number of Slices                       6148 out of 8672   70%
      Number of SLICEMs                    362 out of 4336    8%



Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 14 secs 
Finished initial Timing Analysis.  REAL time: 16 secs 


Starting Placer
Total REAL time at the beginning of Placer: 16 secs 
Total CPU  time at the beginning of Placer: 15 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:ac54e46d) REAL time: 20 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:ac54e46d) REAL time: 20 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:a51ae57f) REAL time: 20 secs 

Phase 4.2  Initial Clock and IO Placement

Phase 4.2  Initial Clock and IO Placement (Checksum:c7ac8c9b) REAL time: 25 secs 

Phase 5.30  Global Clock Region Assignment
Phase 5.30  Global Clock Region Assignment (Checksum:c7ac8c9b) REAL time: 25 secs 

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:c7ac8c9b) REAL time: 25 secs 

Phase 7.8  Global Placement
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Phase 7.8  Global Placement (Checksum:b4fd419e) REAL time: 3 mins 9 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:b4fd419e) REAL time: 3 mins 9 secs 

Phase 9.18  Placement Optimization
Phase 9.18  Placement Optimization (Checksum:52be7d07) REAL time: 5 mins 10 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:52be7d07) REAL time: 5 mins 10 secs 

Total REAL time to Placer completion: 5 mins 12 secs 
Total CPU  time to Placer completion: 5 mins 8 secs 
Writing design to file top.ncd



Starting Router


Phase  1  : 45285 unrouted;      REAL time: 5 mins 34 secs 

Phase  2  : 41905 unrouted;      REAL time: 5 mins 52 secs 

Phase  3  : 15288 unrouted;      REAL time: 6 mins 14 secs 

Phase  4  : 18219 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 6 secs 

Phase  5  : 0 unrouted; (Setup:3679, Hold:0, Component Switching Limit:0)     REAL time: 9 mins 21 secs 

Updating file: top.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Setup:3679, Hold:0, Component Switching Limit:0)     REAL time: 9 mins 32 secs 

Phase  7  : 0 unrouted; (Setup:3679, Hold:0, Component Switching Limit:0)     REAL time: 9 mins 44 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 11 mins 50 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 11 mins 53 secs 

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 12 mins 
WARNING:Route:455 - CLK Net:Inst_system/mdm_0/Dbg_Update_1 may have excessive skew because 
      9 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:fpga_0_clk_1_sys_clk_pin_IBUF may have excessive skew because 
      4 CLK pins and 0 NON_CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 12 mins 1 secs 
Total CPU time to Router completion: 11 mins 54 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|Inst_system/clk_50_0 |              |      |      |            |             |
|              000MHz | BUFGMUX_X1Y10| No   | 2775 |  0.212     |  0.381      |
+---------------------+--------------+------+------+------------+-------------+
|Inst_system/mdm_0/Db |              |      |      |            |             |
|             g_Clk_1 |  BUFGMUX_X1Y0| No   |  109 |  0.138     |  0.317      |
+---------------------+--------------+------+------+------------+-------------+
|Inst_system/mdm_0/Db |              |      |      |            |             |
|          g_Update_1 |         Local|      |   24 |  1.882     |  3.794      |
+---------------------+--------------+------+------+------------+-------------+
|fpga_0_clk_1_sys_clk |              |      |      |            |             |
|           _pin_IBUF |         Local|      |    4 |  0.539     |  1.993      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_Inst_system_clock_generator_0_clock_ge | SETUP       |     0.042ns|    19.958ns|       0|           0
  nerator_0_SIG_DCM0_CLK0 = PERIOD          | HOLD        |     0.676ns|            |       0|           0
  TIMEGRP         "Inst_system_clock_genera |             |            |            |        |            
  tor_0_clock_generator_0_SIG_DCM0_CLK0"    |             |            |            |        |            
        TS_sys_clk_pin HIGH 50%             |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | SETUP       |    18.212ns|     1.788ns|       0|           0
  pin" 50 MHz HIGH 50%                      | HOLD        |     0.408ns|            |       0|           0
                                            | MINLOWPULSE |    14.000ns|     6.000ns|       0|           0
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin                 |     20.000ns|      6.000ns|     19.958ns|            0|            0|            3|      3593254|
| TS_Inst_system_clock_generator|     20.000ns|     19.958ns|          N/A|            0|            0|      3593254|            0|
| _0_clock_generator_0_SIG_DCM0_|             |             |             |             |             |             |             |
| CLK0                          |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 12 mins 9 secs 
Total CPU time to PAR completion: 12 mins 2 secs 

Peak Memory Usage:  278 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 0

Writing design to file top.ncd



PAR done!
