Release 12.2 - xst M.63c (nt)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "dlmb_wrapper_xst.prj"
Verilog Include Directory          : {"C:\Temp\Bomberman\pcores\" "C:\Xilinx\12.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc3s1200efg320-4
Output File Name                   : "../implementation/dlmb_wrapper.ngc"

---- Source Options
Top Module Name                    : dlmb_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation/dlmb_wrapper}

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/hdl/vhdl/lmb_v10.vhd" in Library lmb_v10_v1_00_a.
Entity <lmb_v10> compiled.
Entity <lmb_v10> (Architecture <IMP>) compiled.
Compiling vhdl file "C:/Temp/Bomberman/hdl/dlmb_wrapper.vhd" in Library work.
Entity <dlmb_wrapper> compiled.
Entity <dlmb_wrapper> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <dlmb_wrapper> in library <work> (architecture <STRUCTURE>).

Analyzing hierarchy for entity <lmb_v10> in library <lmb_v10_v1_00_a> (architecture <IMP>) with generics.
	C_EXT_RESET_HIGH = 1
	C_LMB_AWIDTH = 32
	C_LMB_DWIDTH = 32
	C_LMB_NUM_SLAVES = 1


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <dlmb_wrapper> in library <work> (Architecture <STRUCTURE>).
Entity <dlmb_wrapper> analyzed. Unit <dlmb_wrapper> generated.

Analyzing generic Entity <lmb_v10> in library <lmb_v10_v1_00_a> (Architecture <IMP>).
	C_EXT_RESET_HIGH = 1
	C_LMB_AWIDTH = 32
	C_LMB_DWIDTH = 32
	C_LMB_NUM_SLAVES = 1
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/hdl/vhdl/lmb_v10.vhd" line 145: Instantiating black box module <SRL16>.
    Set user-defined property "INIT =  FFFF" for instance <POR_SRL_I> in unit <lmb_v10>.
WARNING:Xst:2211 - "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/hdl/vhdl/lmb_v10.vhd" line 159: Instantiating black box module <FDS>.
Entity <lmb_v10> analyzed. Unit <lmb_v10> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <lmb_v10>.
    Related source file is "C:/Xilinx/12.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v1_00_a/hdl/vhdl/lmb_v10.vhd".
Unit <lmb_v10> synthesized.


Synthesizing Unit <dlmb_wrapper>.
    Related source file is "C:/Temp/Bomberman/hdl/dlmb_wrapper.vhd".
Unit <dlmb_wrapper> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 1
 Flip-Flops                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <dlmb_wrapper> ...

Mapping all equations...
Building and optimizing final netlist ...

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 1
 Flip-Flops                                            : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : ../implementation/dlmb_wrapper.ngc
Output Format                      : ngc
Optimization Goal                  : speed
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 211

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
# FlipFlops/Latches                : 1
#      FDS                         : 1
# Shift Registers                  : 1
#      SRL16                       : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                        1  out of   8672     0%  
 Number of Slice Flip Flops:              1  out of  17344     0%  
 Number of 4 input LUTs:                  1  out of  17344     0%  
    Number used as logic:                 0
    Number used as Shift registers:       1
 Number of IOs:                         211
 Number of bonded IOBs:                   0  out of    250     0%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
LMB_Clk                            | NONE(dlmb/POR_FF_I)    | 2     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.014ns (Maximum Frequency: 249.128MHz)
   Minimum input arrival time before clock: 0.911ns
   Maximum output required time after clock: 0.591ns
   Maximum combinational path delay: 0.000ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'LMB_Clk'
  Clock period: 4.014ns (frequency: 249.128MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               4.014ns (Levels of Logic = 0)
  Source:            dlmb/POR_SRL_I (FF)
  Destination:       dlmb/POR_FF_I (FF)
  Source Clock:      LMB_Clk rising
  Destination Clock: LMB_Clk rising

  Data Path: dlmb/POR_SRL_I to dlmb/POR_FF_I
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     SRL16:CLK->Q          1   3.706   0.000  dlmb/POR_SRL_I (dlmb/srl_time_out)
     FDS:D                     0.308          dlmb/POR_FF_I
    ----------------------------------------
    Total                      4.014ns (4.014ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'LMB_Clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              0.911ns (Levels of Logic = 0)
  Source:            SYS_Rst (PAD)
  Destination:       dlmb/POR_FF_I (FF)
  Destination Clock: LMB_Clk rising

  Data Path: SYS_Rst to dlmb/POR_FF_I
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:S                     0.911          dlmb/POR_FF_I
    ----------------------------------------
    Total                      0.911ns (0.911ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'LMB_Clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              0.591ns (Levels of Logic = 0)
  Source:            dlmb/POR_FF_I (FF)
  Destination:       LMB_Rst (PAD)
  Source Clock:      LMB_Clk rising

  Data Path: dlmb/POR_FF_I to LMB_Rst
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              0   0.591   0.000  dlmb/POR_FF_I (LMB_Rst)
    ----------------------------------------
    Total                      0.591ns (0.591ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 104 / 104
-------------------------------------------------------------------------
Delay:               0.000ns (Levels of Logic = 0)
  Source:            M_AddrStrobe (PAD)
  Destination:       LMB_AddrStrobe (PAD)

  Data Path: M_AddrStrobe to LMB_AddrStrobe
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    ----------------------------------------
    Total                      0.000ns (0.000ns logic, 0.000ns route)

=========================================================================


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.92 secs
 
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Total memory usage is 147384 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    1 (   0 filtered)

